National Semiconductor DS90C3202 Specifications Download Page 10 | Manualshive

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AC Timing Diagrams

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20147113

RegisterAddress 29d/1dh bit [2:1] = 00b

FIGURE 12. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Enabled

20147114

FIGURE 13. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Disabled

DS90C3202

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Summary of Contents for DS90C3202

Page 1: ...MHz the maximum trans mission rate of each LVDS line is 945 Mbps for an aggregate throughput rate of 9 45 Gbps 945 Mbytes s This allows the dual 10 bit LVDS Receiver to support resolutions up to HDTV Features n Up to 9 45 Gbit s data throughput n 8 MHz to 135 MHz input clock support n Supports up to QXGA panel resolutions n Supports HDTV panel resolutions and frame rates up to 1920 x 1080p n LVDS ...

Page 2: ...S Receiver receives input RGB video data and control signal timing SELECTABLE OUTPUT DATA STROBE The Receiver output data edge strobe can be latched on the rising or falling edges of clock signal The dedicated RFB pin is used to program output strobe select on the rising edge of RCLK or the falling edge of RCLK 2 WIRE SERIAL COMMUNICATION INTERFACE Optional Two Wire serial interface programming al...

Page 3: ...0 VDD V Input Clock Frequency f 8 135 MHz Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Units CMOS TTL DC SPECIFICATIONS Rx outputs control inputs and outputs VIH High Level Input Voltage 2 0 VDD V VIL Low Level Input Voltage 0 0 8 V VOH High Level Output Voltage Rx clock out IOH 4 mA 2 4 V Rx ...

Page 4: ...ute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the device should be operated at these limits The tables of Electrical Characteristics specify conditions for device operation Note 2 Typical values are given for VDD 3 3V and T A 25 C Note 3 Current into device pins is defined as positive Current out of device pins is d...

Page 5: ...ures 11 12 Rx clock out 0 4T 0 5T 0 6T ns RCOL RCLK OUT Low Time Figures 11 12 Rx clock out 0 4T 0 5T 0 6T ns RSRC RxOUT Setup to RCLK OUT Figures 11 12 Notes 8 9 Register addr 29d 1dh 2 1 00b Default 2 60 0 5T ns RHRC RxOUT Hold to RCLK OUT Figures 11 12 Notes 8 9 Register addr 29d 1dh 2 1 00b Default 3 60 0 5T ns RSRC RHRC Programmable Adjustment Register addr 29d 1dh 2 1 01b Figures 13 14 Notes...

Page 6: ...D TF S2CLK and S2DAT Fall Time RP 4 7KΩ CL 50pF 0 3 us SU STA Start Condition Setup Time RP 4 7KΩ CL 50pF 0 6 us HD STA Start Condition Hold Time RP 4 7KΩ CL 50pF 0 6 us HD STO Stop Condition Hold Time RP 4 7KΩ CL 50pF 0 6 us SC SD Clock Falling Edge to Data RP 4 7KΩ CL 50pF 0 us SD SC Data to Clock Rising Edge RP 4 7KΩ CL 50pF 0 1 us SCL SD S2CLK Low to S2DAT Data Valid RP 4 7KΩ CL 50pF 0 1 0 9 u...

Page 7: ...URE 2 Worst Case Test Pattern 20147104 FIGURE 3 Incremental Test Pattern 20147105 FIGURE 4 Typical and Max ICC with Worse Case and Incremental Pattern 20147106 FIGURE 5 LVCMOS LVTTL Output Load and Transition Times DS90C3202 www national com 7 ...

Page 8: ...AC Timing Diagrams Continued 20147107 FIGURE 6 Receiver Phase Lock Loop Wake up Time 20147108 FIGURE 7 Powerdown Delay 20147109 FIGURE 8 Receiver Propagation Delay DS90C3202 www national com 8 ...

Page 9: ...typically 10 ps 40 ps per foot media dependent Please see National s AN 1217 for more details Note 11 Cycle to cycle jitter is less than 100 ps worse case estimate Note 12 ISI is dependent on interconnect length may be zero FIGURE 10 Receiver Input Tolerance and Sampling Window 20147112 Register address 29d 1dh bit 2 1 00b FIGURE 11 Receiver RSRC and RHRC Output Setup Hold Time PTO Disabled DS90C3...

Page 10: ...20147113 RegisterAddress 29d 1dh bit 2 1 00b FIGURE 12 Receiver RSRC and RHRC Output Setup Hold Time PTO Enabled 20147114 FIGURE 13 Receiver RSRC and RHRC Output Setup Hold Time Adjustment PTO Disabled DS90C3202 www national com 10 ...

Page 11: ...AC Timing Diagrams Continued 20147115 FIGURE 14 Receiver RSRC and RHRC Output Setup Hold Time Adjustment PTO Enabled DS90C3202 www national com 11 ...

Page 12: ...AC Timing Diagrams Continued 20147116 FIGURE 15 LVDS Input Mapping DS90C3202 www national com 12 ...

Page 13: ...AC Timing Diagrams Continued 20147117 FIGURE 16 Receiver RITOL Min and Max DS90C3202 www national com 13 ...

Page 14: ...Pin Diagram DS90C3202 Receiver 20147118 DS90C3202 www national com 14 ...

Page 15: ...vel data output 21 RXED4 O P LVTTL O P LVTTL level data output 22 RXED5 O P LVTTL O P LVTTL level data output 23 RXED6 O P LVTTL O P LVTTL level data output 24 VSSR0 GND RX LOGIC Ground pin for logic 25 VDDR0 VDD RX LOGIC Power supply for logic 26 RXEC0 O P LVTTL O P LVTTL level data output 27 RXEC1 O P LVTTL O P LVTTL level data output 28 RXEC2 O P LVTTL O P LVTTL level data output 29 RXEC3 O P L...

Page 16: ...LVTTL O P PWR Power supply pin for LVTTL outputs and digital circuitry 66 RXOD1 O P LVTTL O P LVTTL level data output 67 RXOD2 O P LVTTL O P LVTTL level data output 68 RXOD3 O P LVTTL O P LVTTL level data output 69 RXOD4 O P LVTTL O P LVTTL level data output 70 RXOD5 O P LVTTL O P LVTTL level data output 71 RXOD6 O P LVTTL O P LVTTL level data output 72 RXOC0 O P LVTTL O P LVTTL level data output ...

Page 17: ... differential data input 109 RXOE I P LVDS I P Negative LVDS differential data input 110 RXOE I P LVDS I P Positive LVDS differential data input 111 VSSL GND LVDS PWR Ground pin for LVDS 112 VSSL GND LVDS PWR Ground pin for LVDS 113 VDDL VDD LVDS PWR Power supply pin for LVDS 114 VDDL VDD LVDS PWR Power supply pin for LVDS 115 RCLKIN I P LVDS I P Negative LVDS differential clock input 116 RCLKIN I...

Page 18: ...nterface mod ule to read repeatedly The data byte has the most significant bit first At the end of a read the DS90C3202 can accept either Acknowledge or No Acknowledge from the Master No Acknowledge is typi cally used as a signal for the slave that the Master has read its last byte The master must generate a Start by sending the 7 bit slave address plus a 0 first and wait for acknowledge from DS90...

Page 19: ...elay per step adjustment towards Tsetup improvement 23d 17h R W None 7 Reserved 0000_0000 6 4 LVDS input skew control for RXO channel B 000 default applies to no delay added ONE buffer delay per step adjustment towards Thold improvements 3 Reserved 2 0 LVDS input skew control for RXO channel C 000 default applies to no delay added ONE buffer delay per step adjustment towards Thold improvements 24d...

Page 20: ... LVTTL output transition time control for RXE 0 Tr Tf 1 5ns default 1 Tr Tf 2 5ns 0 LVTTL output transition time control for RXO 0 Tr Tf 1 5ns default 1 Tr Tf 2 5ns 29d 1dh R W None 7 3 Reserved 0000_0000 2 1 LVTTL output setup and hold time control 00 balanced setup and hold time default 01 setup time is increased from default position by 1UI hold time is reduced from default position by 1UI 10 s...

Page 21: ...ailable after 1K of CLK cycles detected PLL generated strobes are within 0 5UI respect to REFCLK 01 LVTLL Outputs available after 2K of CLK cycles detected 00 default LVTTL Outputs available after 1K of CLK cycles detected 0000_0000 5 0 default to select the size of wait counter between 1K or 2K default is 1K 4 I O disable control for RXO channel A 1 disable 0 enable default 3 I O disable control ...

Page 22: ...a significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness BANNED SUBSTANCE COMPLIANCE National Semiconductor follows the provisions of the Product Stewardship Guide for Customers CSP 9 111C2 and Bann...

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