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4.0 RESTRICTIONS USING LOOPBACK

Since the NIC is a half-duplex device, several compromises
were required for the implementation of loopback diagnos-
tics. The restrictions placed on the use of loopback diagnos-
tics are as follows:

1. The FIFO is split into two halves to allow some buffering

of incoming data. The NIC transmits through one half of
the FIFO and receives through the second half. Only the
last five bytes of a packet can be examined in the FIFO
(see Section 5) since the DMA does not store the loop-
back packet in memory. Thus loopback can be consid-
ered a modified form of transmission.

2. Splitting of the FIFO has some bus latency implications.

The FIFO depth is halved, thus reducing the amount of
allowed bus latency. The Loopback Select bit (D3) in the
Data Configuration Register should be set to allow all lo-
cal DMA transfers to continue until the FIFO is filled. In
cases where the latency constraints cannot be accom-
modated, small 7 byte packets can be transmitted. In ad-
dition, the FIFO must only be read (by successfully read-
ing port 06h) during loopback mode; reading the FIFO in
other modes will result in the NIC’s failing to issue the
ACK signal properly.

3. The receiver and the transmitter share the CRC logic,

thus the NIC cannot generate and check the CRC simul-
taneously. That is, if the Inhibit CRC bit is not set in the
Transmit Configuration Register, the NIC will generate
and append the CRC. Software must then be used to
verify the CRC by comparing the CRC from the FIFO with
a previously calculated CRC. On the other hand, if the
Inhibit CRC bit is set in the Transmit Configuration Regis-
ter, the NIC receiver will verify the CRC appended by soft-
ware.

4. Address recognition logic must be checked indirectly

through a small series of tests (for further explanation see
Group III Loopback Tests: Address Recognition).

5. Between consecutive transmissions in loopback mode,

the NIC must be reset to guarantee alignment of the FIFO
pointers when data is read from the FIFO. The following
series of steps must be taken to reset the NIC and realign
the FIFO pointers:

a) Set the Transmit Configuration Register to 00h.

b) Reset the Command Register to 21h, followed by a

wait state of at least 1.5 ms for the NIC to reset.

c) Program the desired loopback mode into the Transmit

Configuration Register.

6. Loopback only operates with byte wide transfers, thus

special considerations must be made with word wide
transfers. Since the FIFO is split, only half of each word is
transferred into the transmit portion of the FIFO. The Byte
Order Select bit in the Data Configuration Register can be
used to select which half of the word is written into the
FIFO (see

Figure 4 ). Although a word is transferred to

the NIC, only a byte is transmitted in the loopback packet.
To properly transfer all the bytes in the loopback packet,
the byte count must be 2 times the actual number of
bytes assembled in the loopback packet.

7. During heavily loaded network conditions, external loop-

back through the TPI or CTI could fail due to interference
from the network.

5.0 ALIGNMENT OF DATA IN THE FIFO

During loopback, eight bytes of the FIFO are used for trans-
mission and eight bytes are used for reception. Reception of
the packet begins at location zero, and after the pointer
reaches the last location in the receive portion of the FIFO,
the pointer wraps back to location zero, overwriting the pre-
viously received data (see

Figure 5 ). The pointer continues

to circulate through the FIFO until the last byte is received.
The NIC then appends the lower receive byte count and two
copies of the upper receive byte count into the next three
locations in the FIFO. Thus, only the last five bytes of the
received packet may be retrieved.

Note:

Although the size limit of a loopback packet is 64 Kbytes, the byte
counter rolls over at 2048 bytes.

TL/F/12034 – 6

FIGURE 5. Continuously Circulating FIFO

Write Pointer during Loopback

To achieve the packet alignment shown in

Figure 6 below,

the packet length should be (N

*

8)

a

5 bytes (i.e. 13, 21,

etc.). If the CRC is appended, the second through fifth byte
will be the CRC appended by the NIC. This allows the CRC
to be extracted from the NIC and compared to a previously
calculated value for verification.

FIFO

FIFO

LOCATION

CONTENTS

0

Byte (N

*

8)

a

1

First Byte Read

1

Byte (N

*

8)

a

2 (CRC 1)

Second Byte Read

2

Byte (N

*

8)

a

3 (CRC 2)

#

3

Byte (N

*

8)

a

4 (CRC 3)

#

4

Byte (N

*

8)

a

5 (CRC 4)

#

5

Lower Byte Count

#

6

Upper Byte Count

#

7

Upper Byte Count

Last Byte Read

FIGURE 6. Alignment of Packet in

FIFO Following Loopback

4

Summary of Contents for DP8390

Page 1: ...that generates the tests Appendix A This document also discusses varia tions in loopback results caused by several common config uration errors Throughout this document the term NIC refers to the con...

Page 2: ...TL F 12034 2 FIGURE 2 Loopback Mode 2 Through the Encoder Decoder TL F 12034 3 FIGURE 3 Loopback Mode 3 Through the TPI or CTI 2...

Page 3: ...isters TBCR0 and TBCR1 are decremented 2 The NIC generates 56 bits of preamble followed by an 8 bit Start of Frame Delimiter 3 Data is transferred from the FIFO to the serializer 4 If the Inhibit CRC...

Page 4: ...Register to 21h followed by a wait state of at least 1 5 ms for the NIC to reset c Program the desired loopback mode into the Transmit Configuration Register 6 Loopback only operates with byte wide t...

Page 5: ...er to 21h If the NIC is currently receiving a packet it will wait for the reception of the current packet to complete before it will reset Thus a wait state of at least 1 5 ms is necessary to insure t...

Page 6: ...tus Register is set The packet received bit is set only if status is written to memory In loopback this action does not occur hence the Packet Received bit remains 0 for all loopback modes Internal Lo...

Page 7: ...SR ISR Mode 3 CTI 06H 1FH 0CH 02H 08H If the coax cable is disconnected the results will differ from those listed in Section 6 1 as follows Loopback Path TCR RCR TSR RSR ISR Mode 1 NIC 02H 1FH 40H 02H...

Page 8: ...cription in Section 6 1 When executed the FIFO and register contents are printed to an output file output txt unless specified differently Refer to AN 874 Writing Drivers for the DP8390 NIC Family of...

Page 9: ...TL F 12034 8 9...

Page 10: ...TL F 12034 9 10...

Page 11: ...TL F 12034 10 11...

Page 12: ...ional Semiconductor National Semiconductor National Semiconductores National Semiconductor Corporation GmbH Japan Ltd Hong Kong Ltd Do Brazil Ltda Australia Pty Ltd 2900 Semiconductor Drive Livry Garg...

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