2.0 LOOPBACK MODES
Loopback modes are selected by programming bits LB0
and LB1 in the Transmit Configuration Register.
Figures 1,
2, and 3 illustrate the loopback paths using the DP83902 as
an example. The NIC family supports three modes of loop-
back:
MODE 1 (LB1
e
0, LB2
e
1):
Internal loopback through
the Controller Module only
(Figure 1 ) . The Controller Mod-
ule’s serializer is connected to the deserializer.
MODE 2 (LB1
e
1, LB2
e
0):
Internal loopback through
the ENDEC Module
(Figure 2 ) . The NIC provides a control
(LPBK) that forces the ENDEC module or the DP8391 SNI
to loop back all signals.
MODE 3 (LB1
e
1, LB2
e
1):
External loopback through
the TPI or DP8392 CTI
(Figure 3 ) . For coaxial cable, pack-
ets are transmitted to the cable to check all of the transmit
and receive paths and the cable itself. For twisted pair ca-
ble, packets are looped internal to the TPI.
3.0 LOOPBACK OPERATION IN THE NIC
To initiate a loopback test, a packet must first be assembled
and transferred into the NIC buffer memory. Next, the
Transmit Page Start Register, Transmit Byte Count Regis-
ters, Transmit Configuration Register, and Data Configura-
tion Register must be programmed. Finally, the transmit
command is issued to the Command Register, causing the
following operations to occur:
3.1 Transmitter Actions
1. Data is transferred from memory by local DMA until the
FIFO is filled. Subsequent burst transfers to refill the
FIFO are initiated when the number of bytes in the FIFO
drops below the programmed threshold. During the trans-
fers the Transmit Byte Count Registers (TBCR0 and
TBCR1) are decremented.
2. The NIC generates 56 bits of preamble followed by an
8-bit Start of Frame Delimiter.
3. Data is transferred from the FIFO to the serializer.
4. If the Inhibit CRC bit is set in the Transmit Configuration
Register, no CRC is calculated by the NIC. In this case, a
software CRC can be appended after the data field in
buffer memory. If the Inhibit CRC bit is not set, the NIC
calculates and appends four bytes of CRC to the end of
the data field.
5. At the end of transmission, the Packet Transmitted bit is
set in the Interrupt Status Register.
3.2 Receiver Actions
1. After the preamble and Start of Frame Delimiter have
been decoded, the incoming packet starts filling the
FIFO. See Section 5.0 for a description of the packet
storage in the FIFO. The packet is not stored in buffer
memory.
2. The receive byte count is incremented for each incoming
byte.
3. If the Inhibit CRC bit is set in the Transmit Configuration
Register, the receiver checks the incoming packet for
CRC errors. If the Inhibit CRC bit is not set in the Transmit
Configuration Register, the receiver does not check for
CRC errors and the CRC error bit is set in the Receive
Status Register.
4. At the end of receive, the receive byte count is written
into the FIFO and the Receive Status Register is updated.
The Packet Received Intact bit is typically set in the Re-
ceive Status Register even if the address does not
match. If CRC errors are forced, the packet’s destination
address must match the address filters in order for the
CRC error bit in the Receive Status Register to be set.
RAM
TL/F/12034 – 4
DCR Bits WTS
e
‘‘1’’ and BOS
e
‘‘0’’
RAM
TL/F/12034 – 5
DCR Bits WTS
e
‘‘1’’ and BOS
e
‘‘1’’
FIGURE 4. Packet Assembly for Loopback Word Wide Transfers
3
