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Summary of Contents for DP8390

Page 1: ...that generates the tests Appendix A This document also discusses varia tions in loopback results caused by several common config uration errors Throughout this document the term NIC refers to the con...

Page 2: ...TL F 12034 2 FIGURE 2 Loopback Mode 2 Through the Encoder Decoder TL F 12034 3 FIGURE 3 Loopback Mode 3 Through the TPI or CTI 2...

Page 3: ...isters TBCR0 and TBCR1 are decremented 2 The NIC generates 56 bits of preamble followed by an 8 bit Start of Frame Delimiter 3 Data is transferred from the FIFO to the serializer 4 If the Inhibit CRC...

Page 4: ...Register to 21h followed by a wait state of at least 1 5 ms for the NIC to reset c Program the desired loopback mode into the Transmit Configuration Register 6 Loopback only operates with byte wide t...

Page 5: ...er to 21h If the NIC is currently receiving a packet it will wait for the reception of the current packet to complete before it will reset Thus a wait state of at least 1 5 ms is necessary to insure t...

Page 6: ...tus Register is set The packet received bit is set only if status is written to memory In loopback this action does not occur hence the Packet Received bit remains 0 for all loopback modes Internal Lo...

Page 7: ...SR ISR Mode 3 CTI 06H 1FH 0CH 02H 08H If the coax cable is disconnected the results will differ from those listed in Section 6 1 as follows Loopback Path TCR RCR TSR RSR ISR Mode 1 NIC 02H 1FH 40H 02H...

Page 8: ...cription in Section 6 1 When executed the FIFO and register contents are printed to an output file output txt unless specified differently Refer to AN 874 Writing Drivers for the DP8390 NIC Family of...

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Page 12: ...ional Semiconductor National Semiconductor National Semiconductores National Semiconductor Corporation GmbH Japan Ltd Hong Kong Ltd Do Brazil Ltda Australia Pty Ltd 2900 Semiconductor Drive Livry Garg...

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