Figure 3. FFT display of the signal in Figure 2 showing
performance of the ADC14071. From this display, the noise floor
can be estimated and spurious signals can be identified. Note
the display of SINAD, SNR, THD and SFDR to the right of the
plot.
JUMPER
FUNCTION
PINS 1 & 2
SHORTED
PINS 2 & 3
SHORTED
JP1
Input Select
Select
Transformer
Select Op-
Amp Circuit
JP2 & JP3
Select Input
to drive ADC
Select
Transformer
Select Op-
Amp Circuit
JP4
Select Clock
Source
External
Clock
On-Board
Clock
JP5
Ext. Clock
Termination
50-Ohm
Termination
No
Termination
Table 1. Jumper settings.
4.2.6 Troubleshooting
4.2.4 Getting Consistent Readings
"Error Transmitting", "Parallel Port Time Out Error" and/or
"Failed to communicate with the board on LPT1" errors mean
communication was unsuccessful. Try the following:
Artifacts can result when we perform an FFT on a digitized
waveform, producing inconsistent results when testing
repeatedly. The presence of these artifacts means that the
ADC under test may perform better than our measurements
would indicate.
•
Be sure that the ADC14071 board is connected to a
parallel printer port supporting ECP or EPP modes and
has power.
We can eliminate the need for windowing and get more
consistent results if we observe the proper ratios between the
input and sampling frequencies. This greatly increases the
spectral resolution of the FFT, allowing us to more accurately
evaluate the spectral response of the A/D converter. When
we do this, however, we must be sure that the input signal
has high spectral purity and stability and that the sampling
clock signal is extremely stable with minimal jitter. Coherent
sampling of a periodic waveform occurs when an integer
number of cycles exists in the sample window. The
relationship between the number of cycles sampled (CY), the
number of samples taken (SS), the signal input frequency
(fin) and the sample rate (fs), for coherent sampling, is
•
Be sure that a jumper is present on J4.
•
Ascertain that a 14MHz clock oscillator is properly
inserted into the socket at Y1, or that a TTL-level clock
signal is present at J2. Check to see that LED D5 is on.
•
Be sure cable connections are solid.
•
Be sure that the board to computer cable is one with all
wires present
•
Be sure the correct parallel port is selected.
•
Reset the evaluation board by pressing button S1 and
try again.
•
Be sure that the parallel port jumper within the
computer or BIOS settings is set to enable bi-directional
EPP or ECP modes.
CY
SS
f
in
f
s
=
If there is no output from the ADC14071, perform the
following:
CY, the number of cycles in the data record, must be an
integer number and SS, the number of samples in the record,
must be a factor of 2 integer. For optimum results, CY should
also be a prime number.
•
Be sure proper voltages and polarities are at the correct
pins of power connector P2. Check for correct voltages
at TP6, TP7 and TP8 at the top center of the board.
•
Look at the min/max code note at the upper right of the
data window. If the signal level is very low and does not
cross zero, it will be off the screen. If this is the case,
press
ALT
,-V, A and set the Y-axis min and max so that
the plot may be viewed. If you set the min higher than
the max, the program will abort.
Further, fin (signal input frequency) and fs (sampling rate)
should be locked to each other. If they come from the same
generator, whatever frequency instability (jitter) is present in
the two signals will cancel each other.
Windowing (an FFT Option under WaveVision) should be
turned off for coherent sampling.
•
Be sure clock signal is present at TP4.
•
Check for presence of jumpers on JP1, JP2 and JP3.
4.2.5 Jumper Information
Table 1 indicates the function and use of the jumpers on the
ADC14071 evaluation board.
•
Reset the evaluation board by pressing button S1 and
try again.
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