7.4 Hardware Schematics
F
igur
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8.
I
nput
P
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es
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ng,
R
e
fe
re
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a
nd Te
st
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ti
on
of
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h
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A
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14071 Eva
lua
ti
on B
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rd
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it
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1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
OR
D
13(
M
S
B
)
D1
2
D1
1
D1
0
DR
V
D
DR
G
N
D
D9
D8
D8
D6
D5
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RM
BY1
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IN
+
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IN
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N
D
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A
V
A
V
A
AG
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N
D
PD
CL
K
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V
A
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D
AGN
D
AGN
D
V
D
N/C
D0 (
LS
B)
D1
D2
D3
D4
DRG
ND
N/C
V
RE
F
+ BY
N/C
V
RE
F
- BY
N/C
V
RE
F I
N
AGN
D
V
A
N/C
N/C
N/C
DRG
ND
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