6.0 Computer-Board Communications
Communication between the board and computer is through
a parallel port connection at connector P1. The board
responds to commands from the computer and uploads data
requested by the computer.
The RAM address is incremented by PLD U6, which clocks
the ADC14071 output data into RAM. The PLD counts the
number of words it clocks into RAM. Once the requested
number of words has been acquired and loaded into RAM,
the board uploads the data to the host computer.
Figure 6. Code uncertainty when the ADC input voltage
is near a code transition point.
5.1.2.2 Rising / Falling Symmetry
7.0 Circuit Description and Hardware Schematics
The ideal analog-to-digital converter will give the same code
when digitizing a given input voltage whether that voltage is
approached from a lower voltage or from a higher voltage. If a
triangle wave is presented to the ADC, the falling side of the
waveform should be a mirror image of the rising side at the
input and at the output. In practice, however, this may not be
the case. Noise anywhere in the system may cause the rising
and falling slopes to differ, as can the signal source itself.
Looking at the WaveVision data display of a digitized triangle
wave will show how symmetrical the two slopes are with
respect to each other
provided the input signal has
symmetrical slopes. Choose your generator with care as
many triangle wave signal generators have non-symmetrical
slopes.
Figure 7 shows the block diagram of the ADC14071
evaluation board. U6 (a programmable logic device) controls
I/O and interprets instructions from a host PC that is
operating under WaveVision control. After receiving a
command from the host PC, the U6 interprets it, performs the
operation requested and returns the results. The board
operates from supplies of ±12V to ±15V.
The hardware schematic is divided into two sections: The
Input, Reference and Test Device Section, and the Control,
Memory, Communications and Power Supply Section.
7.1 Input, Reference and Test Device Section
Figure 8 shows the input processing, reference and test
device circuitry. The Analog Input at J2 will be presented to
the converter through any signal conditioning circuitry that you
may build or use. No anti-aliasing filter is included with the
board. You should add such a filter, if needed.
5.2 The FFT Plot
The readings of SINAD, SNR, THD and SFDR (Spurious-
Free Dynamic Range) are only meaningful for a single
frequency sine wave input to the ADC and are only accurate
to the extent that the input waveform to the ADC14071 is
clean (contains a single frequency) and is stable.
Note that this board allows selection of a transformer or
operational amplifiers for single-ended to differential
conversion of the input signal to drive the ADC14071.
Because the transformer is a high frequency one and not
designed for low frequency operation, we recomment that the
transformer be used only for input frequencies above 500kHz.
5.2.1 Dynamic Performance Estimates
The dynamic performance as indicated by SINAD, SNR, THD
and SFDR are estimates rather than absolute figures
because their accuracy depends upon how much of the
ADC14071's dynamic input range is used, how many
samples are taken and at what point in the waveform the first
and last samples are taken.
7.2 Control, Memory, Communications and Power Supply
Section
The Control, Memory, Communications and Power Supply
Section is shown in
Figure 9. The PLD controls the functions
of the evaluation board.
If the input is reduced below a full scale swing such that the
minimum and maximum codes obtained at the output are
±6500 rather than the full scale values of zero and -8192 and
+8191, only about 80% of the code range is used. The result
is an apparent degradation of SNR. On the other hand, if the
input exceeds the input dynamic range such that the top or
bottom (or both) of the input signal is clipped at the
ADC14071's input, THD, SFDR and SINAD will be degraded.
Output data from the ADC14071 is clocked directly into RAM
(U7). The stored data is read from RAM and sent to the host
computer by U6.
Power is brought to the board at P2. The board is protected
with series diodes in the power supply lines.
Furthermore, apparent performance may be limited by the
purity of the input signal used, or by the non-linearities of any
op-amp, transformer, or other component(s) in the signal
conditioning circuitry.
The ADC14071 will operate with clock frequencies of 25kHz
to 8MHz. U6 will divide the on-board clock oscillator by either
2 or 4. For a board clock rate of 14MHz, U6 provides ADC
clock rates of 7MHz or 3.5MHz. The board will function with
clock oscillators in the range of 50kHz to 32MHz, as long as
the ADC14071 clock frequency is in the range of 25kHz to
8MHz. The ADC14071 is specified only for 7MSPS.
5.2.2 Bandwidth Estimation
If a constant amplitude frequency sweep is applied at the
Analog Input (J1) and the signal at the ADC input is digitized
and displayed, the data display on your computer monitor will
show any frequency dependent amplitude variation. If you
then perform an FFT on this data, you can effectively see the
amplitude response in the form of a Bode plot.
7.3 The Reset Button
The Reset button (S1) is used to reset U6. This button should
be pressed after applying power to the board and any time the
system does not appear to be working properly.
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