National Semiconductor ADC081500DEV, Instruction Manual

Page: 21 / 27

21 www.national.com
10.2 Expansion Header
A 72 pin Future Bus Expansion Header is provided on the rear panel to allow easy connection to a third
party microprocessor board to allow for the reading and analysis of the data captured by the FPGA.
The signals connector to this expansion bus will be as follows
PIN DESCRIPTION PIN DESCRIPTION
A1 I2C - SDA B1 GROUND
A2 I2C - SCL B2 GROUND
A3 SSP - SERIAL DATA B3 GROUND
A4 SSP - SERIAL CLOCK B4 GROUND
A5 FPGA RESET B5 GROUND
A6 READ FIFO B6 GROUND
A7 WRITE FIFO B7 GROUND
A8 FIFO FULL B8 GROUND
A9 FIFO EMPTY B9 GROUND
A10 ADC DCLK RESET B10 GROUND
A11 FPGA CONF DONE B11 GROUND
A12 FPGA JTAG – TMS B12 GROUND
A13 FPGA JTAG - TCK B13 GROUND
A14 FPGA JTAG – TDI B14 GROUND
A15 FPGA JTAG – TDO B15 GROUND
A16 notSHUTDOWN B16 GROUND
A17 3.3V SUPPLY B17 GROUND
A18 12V SUPPLY B18 GROUND
C1 DATA BUS A P0 (LVDS or CMOS) D1 DATA BUS A N0 (LVDS or CMOS)
C2 DATA BUS A P1 (LVDS or CMOS) D2 DATA BUS A N1 (LVDS or CMOS)
C3 DATA BUS A P2 (LVDS or CMOS) D3 DATA BUS A N2 (LVDS or CMOS)
C4 DATA BUS A P3 (LVDS or CMOS) D4 DATA BUS A N3 (LVDS or CMOS)
C5 DATA BUS A P4 (LVDS or CMOS) D5 DATA BUS A N4 (LVDS or CMOS)
C6 DATA BUS A P5 (LVDS or CMOS) D6 DATA BUS A N5 (LVDS or CMOS)
C7 DATA BUS A P6 (LVDS or CMOS) D7 DATA BUS A N6 (LVDS or CMOS)
C8 DATA BUS A P7 (LVDS or CMOS) D8 DATA BUS A N7 (LVDS or CMOS)
C9 INPUT STROBE P D9 INPUT STROBE N
C10 DATA BUS B P0 (LVDS or CMOS) D10 DATA BUS B N0 (LVDS or CMOS)
C11 DATA BUS B P1 (LVDS or CMOS) D11 DATA BUS B N1 (LVDS or CMOS)
C12 DATA BUS B P2 (LVDS or CMOS) D12 DATA BUS B N2 (LVDS or CMOS)
C13 DATA BUS B P3 (LVDS or CMOS) D13 DATA BUS B N3 (LVDS or CMOS)
C14 DATA BUS B P4 (LVDS or CMOS) D14 DATA BUS B N4 (LVDS or CMOS)
C15 DATA BUS B P5 (LVDS or CMOS) D15 DATA BUS B N5 (LVDS or CMOS)
C16 DATA BUS B P6 (LVDS or CMOS) D16 DATA BUS B N6 (LVDS or CMOS)
C17 DATA BUS B P7 (LVDS or CMOS) D17 DATA BUS B N7 (LVDS or CMOS)
C18 OUTPUT STROBE P D18 OUTPUT STROBE N
The Data busses on this header can be configured as follows
•
Two 8 bit busses with LVDS differential signaling, plus two LVDS strobes
•
Four 8 bit busses with LVCMOS (3.3V IO) signaling plus four CMOS strobes
All control signals on pins A1 to A15 will be at LVCMOS 3.3V levels.