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PXIe-4480/4481 User Manual

Timing Engines

When you create a task in software, that software task interacts with a timing engine in the 
PXIe-4480/4481 hardware. There are a total of three timing engines in hardware that can be 
operated simultaneously, meaning that three separate tasks can be executed simultaneously, 
each with different sampling rates and triggering settings. This provides the user with a 
significant amount of freedom in running multiple sample rates, but there are some limitations:

The reference clock source must be the same for all tasks, because there is only one 
reference clock per module.

A task can only use analog input channels that are not already being used by other tasks.

Digital Triggering

You can configure the PXIe-4480/4481 module to start an acquisition in response to a digital 
trigger signal from one of the PXI Express backplane trigger lines or the PFI from the front 
connector. The trigger circuit can respond either to a rising or a falling edge.

Analog Triggering

Analog triggering allows you to trigger your application based on an input signal and trigger 
level you define. You can configure the analog trigger circuitry to monitor any input channel 
acquiring data. Choosing an input channel as the trigger channel does not change the input 
channel acquisition specifications.

The analog trigger signal can be used as a reference trigger only. In a reference-triggered 
acquisition, you configure the module to acquire a certain number of pre-trigger samples and a 
certain number of post-trigger samples. Reference-triggered acquisitions can therefore only be 
configured as finite tasks. The analog trigger on the PXIe-4480/4481 cannot be used as a start 
trigger. This restriction is a result of the way the module compensates for the filter group delay.

When using an analog reference trigger, the module first waits for the specified number of 
pre-trigger samples to be acquired. Once enough pre-trigger samples are acquired, the reference 
trigger will occur the next time the analog trigger condition is met. You also can route the 
resulting reference trigger event to supported digital terminals. Refer to the 

Device Routes 

tab 

in NI-MAX for additional information.

During repetitive triggering on a waveform, you might observe jitter because of the uncertainty 
of where a trigger level falls compared to the actual digitized data. Although this trigger jitter is 
usually never greater than one sample period

1

, it might be significant when the sample rate is 

only twice the bandwidth of interest. This jitter usually has no effect on data processing, and you 
can decrease this jitter by sampling at a higher rate.

You can use several analog triggering modes with the PXIe-4480/4481 modules, including 
analog edge, analog edge with hysteresis, and window triggering.

1   

For multidevice tasks, trigger jitter when sampling at 20 MS/s may be two sample periods due to hardware 

limitations. At all other supported sample rates, jitter is never greater than one sample period.

Summary of Contents for PXIe-4480

Page 1: ...Dynamic Signal Acquisition PXIe 4480 4481 User Manual 6 Channel 24 bit 1 25 MS s DSA Analog Input PXIe 4480 4481 User Manual October 2016 376368A 01...

Page 2: ...support phone numbers email addresses and current events National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 683 0100 For further support infor...

Page 3: ...TLE OR NON INFRINGEMENT AND ANY WARRANTIES THAT MAY ARISE FROM USAGE OF TRADE OR COURSE OF DEALING NI DOES NOT WARRANT GUARANTEE OR MAKE ANY REPRESENTATIONS REGARDING THE USE OF OR THE RESULTS OF THE...

Page 4: ...ependent from NI and have no agency partnership or joint venture relationship with NI Patents For patents covering NI products technology refer to the appropriate location Help Patents in your softwar...

Page 5: ...nsducer Electronic Data Sheet 2 11 Voltage Excitation 2 11 Fault Conditions 2 13 IEPE Open and IEPE Short 2 13 Voltage Excitation Current Limit 2 13 Overtemperature Detection 2 14 Chapter 3 Signal Acq...

Page 6: ...Mode 3 8 Data Throughput 3 9 Timing and Triggering 3 10 Sample Clock Timebase 3 10 External Clock 3 10 Timing Engines 3 11 Digital Triggering 3 11 Analog Triggering 3 11 Triggering and Filter Delay 3...

Page 7: ...on and harshness NVH measurements High speed blast and pressure events Underwater transient acoustic measurements The PXIe 4480 offers a large set of sensor conditioning features including charge meas...

Page 8: ...cessories Accessories for the PXIe 4480 and PXIe 4481 include the following shielded InfiniBand 12x cables SHB12X 6BNC 6 BNC analog inputs SHB12X 6MXLRM 6 mini XLR analog inputs SHB12X 6RJ50 6 RJ50 an...

Page 9: ...I 0 5 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 AI 0 AI 0 AI 1 AI 1 AI 2 AI 2 AI 3 AI 3 AI 4 AI 4 AI 5 AI 5 S1 S3 S5 S7 S9 S11 S13 S15 S17 S19 S21 S23...

Page 10: ...to 5 AI 0 5 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 AI 0 AI 0 AI 1 AI 1 AI 2 AI 2 AI 3 AI 3 AI 4 AI 4 AI 5 AI 5 S1 S3 S5 S7 S9 S11 S13 S15 S17 S19 S2...

Page 11: ...ESERVED Reserved for accessories or other use Table 2 2 RJ50 Connector Pin Assignments RJ50 Modular Plug Pin Number Diagram Pin Signal Name Signal Description 1 NC No connect 2 AI Positive analog inpu...

Page 12: ...ption 1 AI Positive analog input signal 0 to 5 2 AI Negative analog input signal 0 to 5 Table 2 4 mXLR Connector Pin Assignments mXLR Male Connector Pin Diagram Pin Signal Name Signal Description 1 GN...

Page 13: ...ber The module is being accessed The Access LED flashes amber for 75 ms when the module is accessed Green Module is ready to be accessed by software Active Off Module is not acquiring or preparing to...

Page 14: ...nalog Input Block Diagram Filter Select Charge Amplifier Lowpass Filter Charge Out Charge In Excitation Voltage 10 V 25 V Adj 9 5 V to 12 V EX 0 5 GND EX 0 5 Voltage Charge Voltage Charge 4mA 10mA 20m...

Page 15: ...lock diagram Depending on the connector type connect the signals as described in the Connecting Signals section Figure 2 4 PXIe 4481 Analog Input Block Diagram AI 0 5 AI 0 5 1 62 M ADC 1 62 M 50 AC DC...

Page 16: ...gnal source is floating use the pseudodifferential input configuration The pseudodifferential configuration provides a ground reference connection for the floating source by connecting a 50 resistor f...

Page 17: ...setup Configure the channels based on the signal source reference or DUT configuration Refer to Table 2 7 to determine how to configure the channel For maximum flexibility the module s input configura...

Page 18: ...oupling any DC offset present in the source signal is passed to the ADC The DC coupled configuration is usually best if the signal source has only small amounts of offset voltage or if the DC content...

Page 19: ...able of parameters and sensor information TEDS sensors have two modes of operation Analog mode allows the sensors to operate as transducers measuring physical phenomena Digital mode allows you to writ...

Page 20: ...V It is also possible to utilize the voltage excitation source to excite a passive full bridge strain gage as shown in Figure 2 9 Refer to Table 2 8 for a guide to connecting signals from the PXIe 448...

Page 21: ...the attached signal source Common connection issues that can occur include open and short circuits An open circuit occurs if there is a disconnect between the signal source and the module resulting i...

Page 22: ...ing acquired may be compromised while the PXIe 4480 4481 is displaying an overtemperature condition If an overtemperature condition is detected the hardware will turn the Active LED red and set a flag...

Page 23: ...ta is decimated to the requested user sample rate and digital filters are applied to filter out frequency content above the Nyquist frequency Frequency domain mode is used any time the requested sampl...

Page 24: ...ng frequency components above the Nyquist limit The undesirable effect of the digitizer modulating out of band components into the Nyquist bandwidth is aliasing The greatest danger of aliasing is that...

Page 25: ...with that event is available at the output of the acquisition and filtering process This delay is called the group delay In order to simplify the process of acquiring data from the PXIe 4480 4481 modu...

Page 26: ...passed through the same analog front end circuitry as in a frequency domain mode acquisition This means that time domain mode can use all of the same analog channel configurations available on the PXI...

Page 27: ...e program it to the PXIe 4480 4481 It is required that the filter have the following characteristics Have between 1 and 36 coefficients Filters larger than 36 coefficients are not allowed due to hardw...

Page 28: ...modulator noise Refer to the PXIe 4480 4481 Specifications for more information about the default filter and the performance of time domain mode when using the default filter Step response is affecte...

Page 29: ...sample rate than 20 MS s When hardware decimates it does so by returning every nth sample coming out of the filter For example to produce a sample rate of 5 MS s n 4 the hardware drops the first thre...

Page 30: ...al FIR filter always operates at 20 MS s regardless of the final rate returned to the user after decimation Therefore it is possible for aliasing to occur when using the lower sample rates supported b...

Page 31: ...is transferred for every sample To improve efficiency the PXIe 4480 4481 supports packing the sample data so that this unused byte is eliminated This can be controlled by setting NI DAQmx Channel Pro...

Page 32: ...idth for example at least 500 MB s slot bandwidth and a sufficient system bandwidth to operate all devices installed in the system If a PXI Express remote controller is selected it should use a x4 or...

Page 33: ...n a reference triggered acquisition you configure the module to acquire a certain number of pre trigger samples and a certain number of post trigger samples Reference triggered acquisitions can theref...

Page 34: ...eases as sample rates decrease Synchronization Some applications require tight synchronization between input and output operations on multiple modules Synchronization is important to minimize skew bet...

Page 35: ...d Synchronization Synchronization Type to Slave and that of the Master to Master 7 Query DAQmx Timing More Synchronization Pulse Synchronization Time on all modules being synchronized choose the maxim...

Page 36: ...y your systems accuracy and reliability requirements and provides warranty sparing and calibration services to help you maintain accuracy and minimize downtime over the life of your system Visit ni co...

Page 37: ...tions Engineers make sure every question submitted online receives an answer Software Support Service Membership The Standard Service Program SSP is a renewable one year subscription included with alm...

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