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National Instruments
7
8-Slot NI PXIe-1082 Backplane Installation Guide
System Reference Clock
The NI PXIe-1082 chassis supplies PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 to every peripheral slot with an independent driver for
each signal.
An independent buffer (having a source impedance matched to the
backplane and a skew of less than 500 ps between slots) drives PXI_CLK10
to each peripheral slot. You can use this common reference clock signal to
synchronize multiple modules in a measurement or control system.
An independent buffer drives PXIe_CLK100 to each peripheral slot. These
clocks are matched in skew to less than 100 ps. The differential pair must
be terminated on the peripheral with LVPECL termination for the buffer to
drive PXIe_CLK100 so that when there is no peripheral or a peripheral that
does not connect to PXIe_CLK100, no clock is being driven on the pair to
that slot. Refer to Figure 5 for a termination example.
Figure 5.
CLK100 Termination
An independent buffer drives PXIe_SYNC100 to each peripheral slot. The
differential pair must be terminated on the peripheral with LVPECL
termination for the buffer to drive PXIe_SYNC100 so that when there is
no peripheral or a peripheral that does not connect to PXIe_SYNC100, no
SYNC100 signal is being driven on the pair to that slot. Refer to Figure 5
for a termination example.
In summary, PXI_CLK10 is driven to every slot. PXIE_CLK100 and
PXIE_SYNC100 are driven to every peripheral slot.
CLK100 –
50
Ω
50
Ω
47
Ω
0.01
μ
F
+
–
