8-Slot NI PXIe-1062Q Backplane Installation Guide
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Figure 3.
PXI Trigger Bus and Local Bus Connectivity Diagram
PXI Trigger Bus
All slots share eight trigger lines.You can use these trigger lines in a variety
of ways. For example, you can use triggers to synchronize the operation of
several different PXI peripheral modules. In other applications, one module
can control carefully timed sequences of operations performed on other
modules in the system. Modules can pass triggers to one another, allowing
precisely timed responses to asynchronous external events the system is
monitoring or controlling.
System Reference Clock
The NI PXIe-1062Q chassis supplies the PXI 10 MHz system clock
signal (PXI_CLK10) independently driven to each peripheral slot, and
PXIe_CLK100 and PXIe_SYNC100 to the hybrid slots and system
timing slot.
An independent buffer (having a source impedance matched to the
backplane and a skew of less than 250 ps between slots) drives PXI_CLK10
to each peripheral slot. Refer to Figure 4 for the PXI_CLK10 routing
configuration. You can use this common reference clock signal to
synchronize multiple modules in a measurement or control system.
An independent buffer drives PXIe_CLK100 to the hybrid peripheral slots
and system timing slot. Refer to Figure 4 for the routing configuration of
PXIe_CLK100. These clocks are matched in skew to less than 100 ps. The
differential pair must be terminated on the peripheral with LVPECL
termination for the buffer to drive PXIe_CLK100, so that when there is no
peripheral or a peripheral that does not connect to PXIe_CLK100, no clock
is driven on the pair to that slot.
P1
P2
P1
P2
P1
P2
P1
XP3
XP4
P1
P2
XP3
XP2
XP1
XP4
P1
XP3
XP4
XP3
TP2
XP4
Trigger
Bus
Trigger
Bus
Trigger
Bus
Trigger
Bus
Trigger
Bus
PXI_LB
(12:0)
PXI_LB
(12:0)
Trigger
Bus
Trigger
Bus
PXI_LB6
PXI_LB6
PXI_LB6
PXI_LB6
PXI_LB6
8
7
6
5
4
3
2
1
