8-Slot NI PXIe-1062Q Backplane Installation Guide
8
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To synchronize the system to an external clock, you can drive PXI_CLK10
from an external source through the PXI_CLK10_IN pin on the system
timing slot. Refer to Table 10,
XP4 Connector Pinout for the System Timing
, for the pinout. When a 10 MHz clock is detected on this pin, the
backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 signals to this external clock and distributes these signals
to the slots. (Refer to Figure 4 for the distribution of PXI_CLK10,
PXIe_CLK100, and PXIe_SYNC100.) Refer to
for the specification information for an external clock provided on the
PXI_CLK10_IN pin of the system timing slot.
You also can drive a 10 MHz clock on the 10 MHz REF IN pin of connector
J27. When a 10 MHz clock is detected on this connector, the backplane
automatically phase-locks the PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 signals to this external clock and distributes these signals
to the slots. (Refer to Figure 4 for the distribution of PXI_CLK10,
PXIe_CLK100, and PXIe_SYNC100.) Refer to
for the specification information for an external clock provided on the
10 MHz REF IN pin of connector J27.
If the 10 MHz clock is present on both the PXI_CLK10_IN pin of the
system timing slot and the 10 MHz REF IN pin of connector J27, the signal
on the system timing slot is selected. Refer to Table 1, which explains how
the backplane selects the 10 MHz clocks.
A copy of the backplane PXI_CLK10 is exported to the 10 MHz REF OUT
pin of connector J27. An independent buffer drives this clock. Refer to
for the specification information for the 10 MHz
REF OUT signal on connector J27.
Table 1.
Backplane External Clock Input Truth Table
System Timing Slot
PXI_CLK10_IN
Connector J27
10 MHz REF IN
Backplane PXI_CLK10,
PXIe_CLK100, and PXIe_SYNC100
No clock present
No clock present
Backplane generates its own clocks
No clock present
10 MHz clock present
PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 all phase-locked to
connector J27—10 MHz REF IN
10 MHz clock present
No clock present
PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 all phase-locked to
system timing slot—PXI_CLK10_IN
10 MHz clock present
10 MHz clock present
PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 all phase-locked to
system timing slot—PXI_CLK10_IN
