Chapter 1
Introduction
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National Instruments Corporation
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the connectivity between the bus interface and the fixed I/O, including any
timing, triggering, processing, and custom I/O required by the application.
Timing, triggering, processing, and custom I/O is provided by consuming
logic in the FPGA. Each fixed I/O resource used by the application
consumes a small portion of the FPGA logic, which is used to perform
basic control of the fixed I/O resource. The bus interface also consumes a
small portion of the FPGA logic to provide software access to the device.
The remaining FPGA logic is available for higher-level functions such as
timing, triggering, and counting. Each of these functions consumes varying
amounts of logic. For example, a typical 32-bit counter consumes 20 times
more logic than a DIO resource, while an 8-bit counter consumes five times
more logic than a DIO resource. Figures 1-2 and 1-3 illustrate the logic
used by the FPGA in two different applications. The application shown in
Figure 1-2 requires many fixed I/O resources, leaving little logic left over
for higher-level functions. The application in Figure 1-3 uses relatively few
I/O resources and has enough logic left over for several large functions.
Figure 1-2.
FPGA Logic Use in an Application with Many Fixed I/O Resources
Bus Interface
DIO<8..15>
DIO<0..7>
AI0
AI1
AI2
AI3
AO3
AO2
AO1
AO0
