©
National Instruments Corporation
7
NI 6583R User Guide and Specifications
Block Diagrams
Figures 4 through 7 show the data flow through the NI 6583R. Single-ended data lines use standardized
voltage levels to interpret data as either a binary zero or a one in high-speed digital data transfers.
Differential data lines provide a low-noise, low-power, low-amplitude differential method for
high-speed digital data transfer.
Figure 4.
Clock Input Signals
Figure 5.
Differential Data and PFI Lines
DDC A STROBE
UserGclkLvds on
NI FlexRIO
FPGA Module
(I/O Module Clock 1)
UserGclkLvttl on
NI FlexRIO
FPGA Module
(I/O Module Clock 0)
DDC B STROBE
DDC B STROBE
100
Ω
Data from
NI FlexRIO
FPGA Module
(GPIO Output)
Direction Control
from NI FlexRIO
FPGA Module
(GPIO Direction)
Data to
NI FlexRIO
FPGA Module
(GPIO Input)
DDC B Channel
DDC B Channel
100
Ω
Summary of Contents for NI 6583R
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