National Instruments NI-5752B, Getting Started Manual

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Component-Level Intellectual Property (CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. FlexRIO devices support two types of CLIP: user-defined and socketed.
•
User-defined CLIP
allows you to insert HDL IP into an FPGA target, enabling VHDL
code to communicate directly with an FPGA VI.
• Socketed CLIP provides the same IP integration of the user-defined CLIP, but it also
allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter
module socketed CLIP allows your IP to communicate directly with both the FPGA VI
and the external adapter module connector interface.
The FlexRIO adapter module ships with socketed CLIP items that add module I/O to the
LabVIEW project.
NI 5752/5752B CLIP
The NI 5752/5752B ships with the following CLIP items:
1. NI 5752 IO Module—This CLIP provides access to thirty-two analog input channels,
sixteen digital output lines, and two digital input lines. This CLIP also contains a SPI
interface to program the ADC registers. In the NI 5752/5752B IO Module CLIP, each
Sample Clock cycle generates a sample from the analog input channels. The following
clock sources are available and are selectable using the
SampleClkSrcSelect control.
• 50 MHz onboard oscillator
• DStarA through IOModSyncClock
• External clock through the front panel SMB connector
Only external sample clock rates from 25 MHz to 50 MHz are supported with this CLIP.
Each 12-bit sample is output to LabVIEW as an I16 data type. The 12-bit data is left-
justified and padded with 4 zeros in the LSBs. The data is clocked out of the CLIP on
Data Clock.
2. NI 5752 Multidevice Synchronization—This CLIP provides access to thirty-two analog
input channels, sixteen digital output lines and two digital input lines. This CLIP also
contains a SPI interface to program the ADC registers. For applications requiring
synchronization across multiple NI 5752/5752B modules, this CLIP is recommended. For
more details on multidevice synchronization, refer to KnowledgeBase
5AN9QBLY
at
ni.com/support .
In the NI 5752/5752B Multidevice Synchronization CLIP, each Sample Clock cycle
generates a sample from the analog input channels. DStarA is the only Sample Clock that
is routed. Only Sample Clock rates from 25 MHz to 50 MHz are supported with this
CLIP. Each 12-bit sample is output to LabVIEW as an I16 data type. The 12-bit data is
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