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Register-Level Programming

Appendix E

Lab-PC+ User Manual

E-32

© National Instruments Corporation

Port B direction
1 = input
0 = output

Group B Mode
0 = Mode 0
1 = Mode 1

1

X

X

1/0

1

1/0

X

1/0

7

6

5

4

3

2

1

0

Port C bits (PC2-PC0) 
1 = input
0 = output

During a Mode 2 data transfer, the status of the handshaking lines and interrupt signals can be
obtained by reading Port C.  The Port C status-word bit definitions for a Mode 2 transfer are
shown next.

Port C status-word bit definitions for bidirectional data path (Port A only):

7

6

5

4

3

2

1

0

OBFA*

INTE1

IBFA

INTE2

INTRA

I/O

I/O

I/O

Bit

Name

Description

7

OBFA*

Output buffer full.  Low indicates that the CPU has written data out
to Port A.

6

INTE1

Interrupt enable bit for output.  If this bit is set, interrupts are
enabled from the 8255A for OBF*.  Controlled by bit set/reset of
PC6.

5

IBFA

Input buffer full.  High indicates that data has been loaded into the
input latch of Port A.

4

INTE2

Interrupt enable bit for input.  If this bit is set, interrupts are
enabled from the 8255A for IBF.  Controlled by bit set/reset of
PC4.

3

INTRA

Interrupt request status.  If INTE1 is high and IBFA is high, this bit
is high, indicating that an interrupt request is asserted for input
transfers.  If INTE2 is high and OBFA* is high, this bit is high,
indicating that an interrupt request is asserted for output transfers.

2-0

I/O

Extra I/O status lines available if Port B is not configured for
Mode 1.

Summary of Contents for Lab-PC+

Page 1: ... Copyright 1992 1996 National Instruments Corporation All Rights Reserved Lab PC User Manual Low Cost Multifunction I O Board for ISA June 1996 Edition Part Number 320502B 01 ...

Page 2: ...m 02 757 00 20 Canada Ontario 519 622 9310 Canada Québec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 95 800 010 0793 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 200 51 51 Taiwan 02 377 1200 U K 016...

Page 3: ...any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AM...

Page 4: ...r or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instr...

Page 5: ... Level Programming 1 3 Optional Equipment 1 4 Unpacking 1 4 Chapter 2 Configuration and Installation 2 1 Board Configuration 2 1 PC Bus Interface 2 1 Base I O Address Selection 2 3 DMA Channel Selection 2 6 Interrupt Selection 2 7 Analog I O Configuration 2 8 Analog Output Configuration 2 9 Bipolar Output Selection 2 9 Unipolar Output Selection 2 10 Analog Input Configuration 2 10 Input Mode 2 10 ...

Page 6: ... Sources NRSE Configuration 3 11 Common Mode Signal Rejection Considerations 3 12 Analog Output Signal Connections 3 12 Digital I O Signal Connections 3 13 Port C Pin Connections 3 15 Timing Specifications 3 16 Mode 1 Input Timing 3 18 Mode 1 Output Timing 3 19 Mode 2 Bidirectional Timing 3 20 Timing Connections 3 21 Data Acquisition Timing Connections 3 21 General Purpose Timing Signal Connection...

Page 7: ... 5 4 Unipolar Input Calibration Procedure 5 5 Analog Output Calibration 5 6 Board Configuration 5 6 Bipolar Output Calibration Procedure 5 6 Unipolar Output Calibration Procedure 5 8 Appendix A Specifications A 1 Appendix B OKI 82C53 Data Sheet B 1 Appendix C OKI 82C55A Data Sheet C 1 Appendix D Register Map and Descriptions D 1 Appendix E Register Level Programming E 1 Appendix F Customer Communi...

Page 8: ...tions for Floating Signal Sources 3 11 Figure 3 6 Single Ended Input Connections for Grounded Signal Sources 3 12 Figure 3 7 Analog Output Signal Connections 3 13 Figure 3 8 Digital I O Connections 3 15 Figure 3 9 EXTCONV Signal Timing 3 21 Figure 3 10 Posttrigger Data Acquisition Timing Case 1 3 22 Figure 3 11 Posttrigger Data Acquisition Timing Case 2 3 22 Figure 3 12 Pretrigger Data Acquisition...

Page 9: ...ttling Time Versus Gain 4 7 Table 4 2 Lab PC Maximum Recommended Data Acquisition Rates 4 8 Table 4 3 Bipolar Analog Input Signal Range Versus Gain 4 8 Table 4 4 Unipolar Analog Input Signal Range Versus Gain 4 8 Table 5 1 Voltage Values of ADC Input 5 4 Table D 1 Lab PC Register Map D 2 Table E 1 Unipolar Input Mode A D Conversion Values Straight Binary Coding E 4 Table E 2 Bipolar Input Mode A D...

Page 10: ...ctional overview of the Lab PC and explains the operation of each functional unit making up the Lab PC This chapter also explains the basic operation of the Lab PC circuitry Chapter 5 Calibration discusses the calibration procedures for the Lab PC analog input and analog output circuitry Appendix A Specifications lists the specifications of the Lab PC Appendix B OKI 82C53 Data Sheet contains the m...

Page 11: ...ction to a key concept This text denotes text for which you supply the appropriate word or value such as in Windows 3 x italic monospace Italic text in this font denotes that you must supply the appropriate words or values in the place of these items monospace Bold text in this font denotes the messages and responses that the computer automatically prints to the screen This font also emphasizes li...

Page 12: ...s Software documentation Examples of software documentation you may have are the LabVIEW and LabWindows CVI documentation sets and the NI DAQ documentation After you set up your hardware system use either the application software LabVIEW or LabWindows CVI or the NI DAQ documentation to help you write your application If you have a large and complicated system it is worthwhile to look through the s...

Page 13: ...a logging The 12 bit ADC is useful in high resolution applications such as chromatography temperature measurement and DC voltage measurement The analog output channels can be used to generate experiment stimuli and are also useful for machine and process control and analog function generation The 24 TTL compatible digital I O lines can be used for switching external devices such as transistors and...

Page 14: ...ies of functions for using LabWindows CVI with National Instruments DAQ hardware is included with the NI DAQ software kit The LabWindows CVI Data Acquisition libraries are functionally equivalent to the NI DAQ software Using LabVIEW or LabWindows CVI software will greatly reduce the development time for your data acquisition and control application NI DAQ Driver Software The NI DAQ driver software...

Page 15: ...Cstation NI DAQ Driver Software DAQ or SCXI Hardware Personal Computer or Workstation Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware You can use your Lab PC board together with other PC AT EISA DAQCard and DAQPad Series DAQ and SCXI hardware with NI DAQ software for PC compatibles Register Level Programming The final option for programming any National Ins...

Page 16: ...s and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold and relays For more specific information about these products refer to your National Instruments catalogue or call the office nearest you Unpacking Your Lab PC board is shipped in an antistatic package to prevent electrostatic damage to the board Electrostatic discharge can damage several components on...

Page 17: ...tor diagram in Figure 2 1 shows the Lab PC jumper settings Jumpers W3 and W4 configure the analog input circuitry Jumpers W1 and W2 configure the analog output circuitry Jumpers W6 and W5 select the DMA channel and the interrupt level respectively PC Bus Interface The Lab PC is configured at the factory to a base I O address of hex 260 to use DMA Channel 3 and to use interrupt level 5 These settin...

Page 18: ...ter 2 Lab PC User Manual 2 2 National Instruments Corporation 1 2 3 4 7 8 9 5 6 13 12 11 10 1 Assembly Number 5 W2 8 Serial Number 11 W6 2 Spare Fuse 6 W3 9 J1 12 W5 3 U1 7 W4 10 Fuse 13 Product Name 4 W1 Figure 2 1 Parts Locator Diagram ...

Page 19: ...by National Instruments software packages for use with the Lab PC The Lab PC uses the base I O address space hex 260 through 27F with the factory setting Note Verify that this space is not already used by other equipment installed in your computer If any equipment in your computer uses this base I O address space you must change the base I O address of the Lab PC or of the other device If you chan...

Page 20: ...Switch Settings The five least significant bits of the address A4 through A0 are decoded by the Lab PC to select the appropriate Lab PC register To change the base I O address remove the plastic cover on U1 press each switch to the desired position check each switch to make sure the switch is pressed down all the way and replace the plastic cover Record the new Lab PC base I O address in Appendix ...

Page 21: ... 11F 0 1 0 0 1 120 120 13F 0 1 0 1 0 140 140 15F 0 1 0 1 1 160 160 17F 0 1 1 0 0 180 180 19F 0 1 1 0 1 1A0 1A0 1BF 0 1 1 1 0 1C0 1C0 1DF 0 1 1 1 1 1E0 1E0 1FF 1 0 0 0 0 200 200 21F 1 0 0 0 1 220 220 23F 1 0 0 1 0 240 240 25F 1 0 0 1 1 260 260 27F 1 0 1 0 0 280 280 29F 1 0 1 0 1 2A0 2A0 2BF 1 0 1 1 0 2C0 2C0 2DF 1 0 1 1 1 2E0 2E0 2FF 1 1 0 0 0 300 300 31F 1 1 0 0 1 320 320 33F 1 1 0 1 0 340 340 35F...

Page 22: ...oes not use and cannot be configured to use the 16 bit DMA channels on the PC AT I O channel Each DMA channel consists of two signal lines as shown in Table 2 3 Table 2 3 DMA Channels for the Lab PC DMA Channel DMA Acknowledge DMA Request 1 DACK1 DRQ1 2 DACK2 DRQ2 3 DACK3 DRQ3 Note In most personal computers DMA Channel 2 is reserved for the disk drives Therefore you should avoid using this channe...

Page 23: ... line The Lab PC can share interrupt lines with other devices by using a tristate driver to drive its selected interrupt line The Lab PC hardware supports interrupt lines IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 and IRQ9 Note Do not use interrupt line 6 Interrupt line 6 is used by the diskette drive controller on most IBM PC and compatible computers Once you have selected an interrupt level place the interrupt ju...

Page 24: ... asserting an interrupt line on the PC I O channel IRQ W5 3 4 5 6 7 9 Figure 2 6 Interrupt Jumper Setting for Disabling Interrupts Analog I O Configuration The Lab PC is shipped from the factory with the following configuration Referenced single ended input mode 5 V input range Bipolar analog output 5 V output range Table 2 4 lists all the available analog I O jumper configurations for the Lab PC ...

Page 25: ...gle ended RSE factory setting Nonreferenced single ended NRSE Differential DIFF W4 A B W4 B C W4 B C Analog Output Configuration Two ranges are available for the analog outputs bipolar 5 V and unipolar 0 to 10 V Jumper W1 controls output Channel 0 and W2 controls output Channel 1 Bipolar Output Selection You can select the bipolar 5 V output configuration for either analog output channel by settin...

Page 26: ...B U Figure 2 8 Unipolar Output Jumper Configuration Analog Input Configuration You can select different analog input configurations by using the jumper and register bit software settings as shown in Table 2 4 The following sections describe each of the analog input categories in detail Input Mode The Lab PC features three different input modes referenced single ended RSE input non referenced singl...

Page 27: ...the negative input of the instrumentation amplifier referenced to analog ground While reading the following paragraphs you may find it helpful to refer to Analog Input Signal Connections in Chapter 3 Signal Connections which contains diagrams showing the signal paths for the three configurations DIFF Input Four Channels DIFF input means that each input signal has its own reference and the differen...

Page 28: ...ntial amplifier is tied to analog ground This configuration is useful when measuring floating signal sources See Types of Signal Sources in Chapter 3 Signal Connections With this input configuration the Lab PC can monitor eight different analog input channels To select the RSE input configuration clear the SE __ D bit as described in the Command Register 4 bit description in Appendix D Register Ma...

Page 29: ...following jumper W4 B C Jumper is in standby position and negative input of instrumentation amplifier is tied to multiplexed output This configuration is shown in Figure 2 11 W4 A B C RSE NRSE DIFF Figure 2 11 NRSE Input Configuration Considerations in using the NRSE configuration are discussed in Chapter 3 Signal Connections Note that in this mode the return path of the signal is through the nega...

Page 30: ...Selection You can select the unipolar 0 to 10 V input configuration by setting the following jumper Analog Input W3 B C This configuration is shown in Figure 2 13 A B C W3 B U Figure 2 13 Unipolar Input Jumper Configuration Note If you are using a software package such as NI DAQ or LabWindows CVI you may need to reconfigure your software to reflect any changes in jumper or switch settings ...

Page 31: ...ansion slot cover on the back panel of the computer 4 Insert the Lab PC into an 8 bit or a 16 bit slot 5 Screw the mounting bracket of the Lab PC to the back panel rail of the computer 6 Check the installation 7 Replace the cover The Lab PC board is installed You are now ready to install and configure your software If you are using NI DAQ refer to your NI DAQ release notes Find the installation an...

Page 32: ...PC I O connector This connector is located on the back panel of the Lab PC board and is accessible at the rear of the PC after the board has been properly installed Warning Connections that exceed any of the maximum ratings of input or output signals on the Lab PC may result in damage to the Lab PC board and to the computer This includes connecting any power signals to ground and vice versa Nation...

Page 33: ...1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 DGND DAC1 OUT AGND ACH6 ACH4 ACH2 ACH5 AISENSE AIGND ACH7 PC4 PC5 PC6 PC7 EXTTRIG OUTB0 EXTCONV 5 V CLKB2 GA TB2 OUTB2 CCLKB1 GA TB1 COUTB1 GA TB0 DGND DAC0 OUT ACH1 ACH3 ACH0 EXTUPDA TE Figure 3 1 Lab PC I O Connector Pin Assignments Signal Connection Descriptions The following list describes the connector pins on the Lab PC I O connector by pin number and gi...

Page 34: ... A PA7 is the MSB PA0 the LSB 22 29 PB0 through PB7 Bidirectional data lines for Port B PB7 is the MSB PB0 the LSB 30 37 PC0 through PC7 Bidirectional data lines for Port C PC7 is the MSB PC0 the LSB 38 EXTTRIG External control signal to start a timed conversion sequence Input 39 EXTUPDATE External control signal to update DAC outputs Input 40 EXTCONV External control signal to trigger A D convers...

Page 35: ...anges and maximum ratings apply to inputs ACH 0 7 Input signal range Bipolar input 5 gain V Unipolar input 0 to 10 gain V Maximum input voltage rating 45 V powered on or off Exceeding the input signal range for gain settings greater than 1 will not damage the input circuitry as long as the maximum input voltage rating of 45 V is not exceeded For example with a gain of 10 the input signal range is ...

Page 36: ...ns All signals must be referenced to ground either at the source device or at the Lab PC If you have a floating source you must use a ground referenced input connection at the Lab PC If you have a grounded source you must use a non referenced input connection at the Lab PC Types of Signal Sources When configuring the input mode of the Lab PC and making signal connections you should first determine...

Page 37: ...ate this ground potential difference from the measured signal Input Configurations The Lab PC can be configured for one of three input modes NRSE RSE or DIFF The following sections discuss the use of single ended and differential measurements and considerations for measuring both floating and ground referenced signal sources Table 3 1 summarizes the recommended input configurations for both types ...

Page 38: ...nals to the Lab PC are greater than 15 ft Any of the input signals requires a separate ground reference point or return signal The signal leads travel through noisy environments Differential signal connections reduce picked up noise and increase common mode signal and noise rejection With these connections input signals can float within the common mode limits of the input instrumentation amplifier...

Page 39: ...Differential Input Connections for Grounded Signal Sources With this type of connection the instrumentation amplifier rejects both the common mode noise in the signal and the ground potential difference between the signal source and the Lab PC ground shown as Vcm in Figure 3 3 Differential Connections for Floating Signal Sources Figure 3 4 shows how to connect a floating signal source to a Lab PC ...

Page 40: ...reate a return path to ground for the bias currents of the instrumentation amplifier If a return path is not provided the instrumentation amplifier bias currents charge up stray capacitances resulting in uncontrollable drift and possible saturation in the amplifier Typically values from 10 kΩ to 100 kΩ are used A resistor from each input to ground as shown in Figure 3 4 provides bias current retur...

Page 41: ...reference signal at the source If any of the preceding criteria are not met using DIFF input configuration is recommended You can jumper configure the Lab PC for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal sources in this case the Lab PC provides the reference ground point for the external signal The NRS...

Page 42: ...nal local ground reference is connected to the negative input of the Lab PC instrumentation amplifier The ground point of the signal should therefore be connected to the AISENSE pin Any potential difference between the Lab PC ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the instrumentation amplifier and is therefore rejected by the amplif...

Page 43: ...e instrumentation amplifier can reject common mode noise pickup in the leads connecting the signal sources to the Lab PC The common mode input range of the Lab PC instrumentation amplifier is defined as the magnitude of the greatest common mode signal that can be rejected The common mode input range for the Lab PC depends on the size of the differential input signal Vdiff V in V in and the gain se...

Page 44: ...og Output Channels Lab PC Board DAC1 OUT AGND 11 12 VOUT 1 VOUT 0 Load Load Figure 3 7 Analog Output Signal Connections Digital I O Signal Connections Pins 13 through 37 of the I O connector are digital I O signal pins Digital I O on the Lab PC is designed around the 8255A integrated circuit The 8255A is a general purpose peripheral interface containing 24 programmable I O pins These pins represen...

Page 45: ...ines Absolute maximum voltage input rating 5 5 V with respect to DGND 0 5 V with respect to DGND Logical Inputs and Outputs Digital I O lines Minimum Maximum Input logic low voltage 0 3 V 0 8 V Input logic high voltage 2 2 V 5 3 V Output logic low voltage 0 4 V at output current 2 5 mA Output logic high voltage 3 7 V at output current 2 5 mA Darlington drive current 2 5 mA 4 0 mA REXT 700 Ω VEXT 1...

Page 46: ...and sensing external device states such as the switch in Figure 3 8 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 3 8 Port C Pin Connections The signals assigned to Port C depend on the mode in which the 8255A is programmed In Mode 0 Port C is considered as two 4 bit I O ports In Modes 1 and 2 Port C is used for status and hand...

Page 47: ...put transfers The handshaking lines OBF and ACK are used to synchronize output transfers The following signals are used in the timing diagrams shown later in this chapter Name Type Description STB Input Strobe input A low signal on this handshaking line loads data into the input latch IBF Output Input buffer full A high signal on this handshaking line indicates that data has been loaded into the i...

Page 48: ...n the 8255A is requesting service during a data transfer The appropriate interrupt enable signals must be set to generate this signal RD Internal Read signal This signal is the read signal generated from the control lines of the PC I O channel WR Internal Write signal This signal is the write signal generated from the control lines of the PC I O channel DATA Bidirectional Data lines at the specifi...

Page 49: ...ications for an input transfer in Mode 1 are as follows DATA RD INTR IBF STB T1 T2 T4 T7 T6 T3 T5 Name Description Minimum Maximum T1 STB pulse width 500 T2 STB 0 to IBF 1 300 T3 Data before STB 1 0 T4 STB 1 to INTR 1 300 T5 Data after STB 1 180 T6 RD 0 to INTR 0 400 T7 RD 1 to IBF 0 300 All timing values are in nanoseconds ...

Page 50: ... timing specifications for an output transfer in Mode 1 are as follows WR OBF INTR ACK DATA T1 T2 T3 T4 T5 T6 Name Description Minimum Maximum T1 WR 0 to INTR 0 450 T2 WR 1 to output 350 T3 WR 1 to OBF 0 650 T4 ACK 0 to OBF 1 350 T5 ACK pulse width 300 T6 ACK 1 to INTR 1 350 All timing values are in nanoseconds ...

Page 51: ...re as follows T1 T6 T7 T3 T4 T10 T2 T5 T8 T9 WR OBF INTR ACK STB IBF RD DATA Name Description Minimum Maximum T1 WR 1 to OBF 0 650 T2 Data before STB 1 0 T3 STB pulse width 500 T4 STB 0 to IBF 1 300 T5 Data after STB 1 180 T6 ACK 0 to OBF 1 350 T7 ACK pulse width 300 T8 ACK 0 to output 300 T9 ACK 1 to output float 20 250 T10 RD 1 to IBF 0 300 All timing values are in nanoseconds ...

Page 52: ...er Timer referred to as A1 is used as a sample counter in conjunction with Counter 0 for data acquisition These counters are not available for general use In addition to counter A0 EXTCONV can be used to externally time conversions See Appendix E Register Level Programming for the programming sequence needed to enable this input Figure 3 9 shows the timing requirements for the EXTCONV input An A D...

Page 53: ...how a controlled acquisition mode data acquisition sequence that is Sample Counter A1 disables further A D conversions after the programmed count 3 in the examples shown in Figures 3 10 and 3 11 expires The counter is not loaded with the programmed count until the first falling edge following a rising edge on the clock input therefore two extra conversion pulses are generated as shown in Figures 3...

Page 54: ...ows a pretrigger data acquisition timing sequence tw 50 nsec minimum EXTTRIG EXTCONV CONVERT Sample Counter V IH V IL 4 tw tw 3 2 1 0 Figure 3 12 Pretrigger Data Acquisition Timing Because both pretrigger and posttrigger modes use EXTTRIG input only one mode can be used at a time If neither PRETRIG nor HWTRIG is set high this signal has no effect The final external control signal EXTUPDATE is used...

Page 55: ...Figure 3 14 illustrates a timing sequence where EXTUPDATE is being used to generate an interrupt EXTUPDATE CNTINT TMRINTCLR Figure 3 14 EXTUPDATE Signal Timing for Generating Interrupts The following rating applies to the EXTCONV EXTTRIG and EXTUPDATE signals Absolute maximum voltage input rating 0 5 to 7 0 V with respect to DGND General Purpose Timing Signal Connections and General Purpose Counte...

Page 56: ...to determine the number of edges that have occurred Counter operation can be gated on and off during event counting Figure 3 15 shows connections for a typical event counting operation where a switch is used to gate the counter on and off 5 V I O Connector CLK GATE OUT DGND Lab PC Board Counter from Group B 4 7 kΩ 13 Signal Source Switch Figure 3 15 Event Counting Application with External Switch ...

Page 57: ...en equals the count value divided by the gate period Figure 3 16 shows the connections for a frequency measurement application You can also use a second counter to generate the gate signal in this application In this case program the second counter for a one shot mode This scheme needs an external inverter to make the output pulse of the second counter active high 5 V I O Connector CLK GATE OUT DG...

Page 58: ...OH output logic high voltage 3 7 V minimum VOL output logic low voltage 0 45 V maximum IOH output source current at VOH 1 mA maximum IOL output sink current at VOL 4 mA maximum tsc tpwh tpwl tgsu tgh tgwh tgwl toutc toutg CLK GATE OUT VOH V IH V IL VIH V OL V IL tsc tpwh tpwl tgsu tgh tgwh tgwl toutg toutc clock period clock high level clock low level gate setup time gate hold time gate high level...

Page 59: ...able This section contains information and guidelines for designing custom cables The Lab PC I O connector is a 50 pin male ribbon cable header The manufacturer part numbers used by National Instruments for this header are as follows Electronic Products Division 3M part number 3596 5002 T B Ansley Corporation part number 609 500 The mating connector for the Lab PC is a 50 position polarized ribbon...

Page 60: ...tion of the Lab PC circuitry Functional Overview The block diagram in Figure 4 1 shows a functional overview of the Lab PC board Data Address 12 Bit D A 12 Bit D A 1 MHz Timebase 2 MHz Timebase Control Signals 12 12 8 8253 Ctr Timer Group B PC I O Channel Interface FIFO 16 8253 Ctr Timer Group A 8255A Digital Interface 8 Input Mux Pgm Gain 12 Bit A D 10 5 10 MHz Oscillator 12 1 1 PC I O Channel Ba...

Page 61: ... some of the timing I O circuitry The internal data and control buses interconnect the components The theory of operation for each of these components is explained in the remainder of this chapter The theory of operation for the data acquisition circuitry is included with the discussion of the analog input circuitry PC I O Channel Interface Circuitry The PC I O channel consists of an address bus a...

Page 62: ...h SA9 to generate the board enable signal and uses lines SA0 through SA4 plus timing signals to generate the onboard register select signals and read write signals The data buffers control the direction of data transfer on the bidirectional data lines based on whether the transfer is a read or write The interrupt control circuitry routes any enabled interrupts to the selected interrupt request lin...

Page 63: ...ata Acquisition Circuitry The Lab PC provides eight channels of analog input with software programmable gain and 12 bit A D conversion Using the timing circuitry the Lab PC can also automatically time multiple A D conversions Figure 4 3 shows a block diagram of the analog input and data acquisition circuitry Sample and Hold Amp PC I O Channel Mux Counter Data Acquisition Timing Command Registers M...

Page 64: ...ersion is complete the value is saved in the A D FIFO for later reading and the ADC is free to start a new conversion Secondly the A D FIFO can collect up to 512 A D conversion values before any information is lost thus allowing software some extra time 512 times the sample interval to catch up with the hardware If more than 512 values are stored in the A D FIFO without the A D FIFO being read fro...

Page 65: ...d As stated in Appendix E Register Level Programming only Counter A0 is required for data acquisition operations in freerun acquisition mode The software must keep track of the number of conversions that have occurred and turn off Counter A0 after the required number of conversions have been obtained In controlled acquisition mode two counters Counters A0 and A1 are required for a data acquisition...

Page 66: ...uracy will not be achieved The settling time is a function of the gain selected The Lab PC data acquisition timing circuitry detects when data acquisition rates are high enough to cause A D conversions to be lost If this is the case this circuitry sets an overrun error flag in the Lab PC Status Register If the recommended data acquisition rates in Table 4 2 are exceeded an error flag is not automa...

Page 67: ...that voltage levels on all the channels included in the scan sequence are within range for the given gain and are driven by low impedance sources The signal ranges for the possible gains are shown in Table 4 3 and Table 4 4 Signal levels outside the ranges shown in Table 4 3 on the channels included in the scan sequence adversely affect the input settling time Similarly greater settling time may b...

Page 68: ...analog output channel contains a 12 bit DAC The DAC in each analog output channel generates a voltage proportional to the input Vref multiplied by the digital code loaded into the DAC Each DAC can be loaded with a 12 bit digital code by writing to the DAC0 L and H and DAC1 L and H Registers on the Lab PC board The voltage output from the two DACs is available at the Lab PC I O connector DAC0 OUT a...

Page 69: ...is designed around an 8255A integrated circuit Figure 4 5 shows a block diagram of the digital I O circuitry The 8255A is a general purpose PPI containing 24 programmable I O pins These pins represent the three 8 bit I O ports A B and C of the 8255A as well as PA 0 7 PB 0 7 and PC 0 7 on the Lab PC I O connector The 8255A also has a control register to configure each of the three I O ports on the ...

Page 70: ...ch digital I O line When the ports are not enabled the digital I O lines act as high impedance inputs Timing I O Circuitry The Lab PC uses two 8253 Counter Timer integrated circuits for data acquisition timing and for general purpose timing I O functions One of these is used internally for data acquisition timing and the other is available for general use Figure 4 6 shows a block diagram of both g...

Page 71: ...MUX CTR RD CTR WR Data 8 PC I O Channel 8253 Counter Timer Group B OUTB0 OUTB2 GATEB2 CLKB2 GATEB1 Scan Interval General Purpose Counter CLKB1 OUTB1 GATEB0 Timebase Extension General Purpose Counter CLKB0 5 V MUX MUX MUX EXTUPDATE EXTTRIG EXTCONV COUTB1 I O Connector CLKA2 OUTA0 Sample Interval Counter CLKA0 GATEA0 CLKA1 Sample Counter GATEA1 OUTA1 GATEA2 DAC Timing OUTA2 2 MHz Source Figure 4 6 T...

Page 72: ...e CLK pin of Counter B1 is driven by the same signal that is driving CLKA0 The OUTB1 pin on the I O connector initiates scan sequences that are separated by a programmable scan interval time The timebases for Counters B1 and B2 must be supplied externally through the 50 pin I O connector Figure 4 7 shows an example of interval scanning timing OUTB1 OUTA0 GATEA0 ADC CH CONVERT CH1 CH0 CH1 CH0 Sampl...

Page 73: ...e 4 8 Single Channel Interval Timing The 16 bit counters in the 8253 can be diagrammed as shown in Figure 4 9 CLK GATE OUT Counter Figure 4 9 Counter Block Diagram Each counter has a CLK input pin a GATE input pin and an output pin labeled OUT The 8253 counters are numbered 0 through 2 and their GATE CLK and OUT pins are labeled GATE N CLK N and OUT N where N is the counter number ...

Page 74: ... you should calibrate the Lab PC so that its measurement accuracy is within 0 012 of its input range 0 5 LSB According to standard practice the equipment used to calibrate the Lab PC should be 10 times as accurate that is have 0 001 rated accuracy Practically speaking calibration equipment with four times the accuracy of the item under calibration is generally considered acceptable Four times the ...

Page 75: ...1 3 R3 5 R5 7 R7 2 R2 4 R4 6 R6 Figure 5 1 Calibration Trimpot Location Diagram The following trimpots are used to calibrate the analog input circuitry R7 Input offset trim analog input R6 Output offset trim analog input R5 Gain trim analog input The following trimpots are used to calibrate the analog output circuitry R3 Gain trim analog output Channel 1 R4 Offset trim analog output Channel 1 R1 G...

Page 76: ...e correction to the readings at gains higher than one by subtracting the offset errors With this method you can use the board at all available gain levels without recalibrating the input The maximum offset at the gain amplifier is specified at 0 5 mV The maximum possible contribution of the gain amplifier to the total offset is therefore 0 5 mV multiplied by the gain To find the error in LSBs divi...

Page 77: ...he range 5 to 5 V then complete the following procedure in the order given This procedure assumes that ADC readings are in the range 2 048 to 2 047 that is the TWOSADC bit in Command Register 1 is set high The following should be performed with the input configuration set to RSE 1 Input Offset Calibration To adjust the amplifier input offset a Connect ACH0 pin 1 on the I O connector to AISENSE AIG...

Page 78: ...lar Input Calibration Procedure If your board is configured for unipolar input which has an input range of 0 to 10 V then complete the following steps in sequence This procedure assumes that ADC readings are in the range 0 to 4 095 that is the TWOSADC bit in Command Register 1 is cleared The following should be performed with the input configuration set to RSE 1 Input Offset Calibration To adjust ...

Page 79: ...e offsets contributed by each component in the circuitry This error appears as a voltage difference between the desired voltage and the actual output voltage generated and is independent of the D A setting To correct this offset gain error set the D A to negative full scale and adjust a trimpot until the output voltage is the negative full scale value 0 5 LSB Gain error in the analog output circui...

Page 80: ... b Set the analog output channel to 5 V by writing 2 048 to the DAC c Adjust trimpot R4 until the output voltage read is 5 V 2 Adjust the Analog Output Gain Adjust the analog output gain by measuring the output voltage generated with the DAC set at positive full scale 4 095 This output voltage should be V fs 0 5 LSB For bipolar output V fs 4 99756 V and 0 5 LSB 1 22 mV For analog output Channel 0 ...

Page 81: ...with the DAC set at positive full scale 4 095 This output voltage should be V fs 0 5 LSB For unipolar output V fs 9 99756 V and 0 5 LSB 1 22 mV For analog output Channel 0 a Connect the voltmeter between DAC0 OUT pin 10 on the I O connector and AGND pin 11 b Set the analog output channel to 9 99756 V by writing 4 095 to the DAC c Adjust trimpot R1 until the output voltage read is 9 99756 V For ana...

Page 82: ...5 V 0 to 5 V 5 1 V 0 to 2 V 10 0 5 V 0 to 1 V 20 0 25 V 0 to 0 5 V 50 0 1 V 0 to 0 2 V 100 0 05 V 0 to 0 1 V Input coupling DC Overvoltage protection 45 V powered on 45 V powered off Inputs protected ACH 0 7 FIFO buffer size 512 samples Data transfers DMA interrupts programmed I O DMA modes Single transfer Transfer Characteristics Relative accuracy 1 0 LSB typ 1 5 LSB max DNL 0 5 LSB typ 1 LSB max...

Page 83: ... 60 Hz 1 100 75 dB 105 dB Dynamic Characteristics Bandwidth 3 dB 400 kHz for gain 1 40 kHz for gain 100 Settling time to full scale step Gain Accuracy 0 2 LSB 10 20 50 100 14 µs 20 µs 33 µs System noise Gain 5 V Range 1 100 0 3 LSB rms 0 6 LSB rms Stability Recommended warm up time 15 minutes Offset temperature coefficient Pregain 450 µV ºC Postgain 10 µV ºC Gain temperature coefficient 50 ppm ºC ...

Page 84: ...thin 1 2 LSB of the ideal one of its edges may be well beyond 1 LSB thus the ADC would have a relative accuracy of that amount National Instruments tests its boards to ensure that they meet all three linearity specifications defined in this appendix specifications for integral nonlinearity are included primarily to maintain compatibility with a convention of specifications used by other board manu...

Page 85: ...ling DC Output impedance 0 2 Ω max Current drive 2 mA max Protection Short to AGND Power on state 0 V for 5 V range 5 V for 0 to 10 V range Dynamic Characteristics Settling time to FSR for 10 V step 5 µs Slew rate 10 V µs Stability Offset temperature coefficient 30 µV C Gain temperature coefficient internal reference 10 ppm C Explanation of Analog Output Specifications Relative accuracy in a D A s...

Page 86: ...vel Min Max Input low voltage Input high voltage Input low current Vin 0 8 V Input high current Vin 2 2 V 0 3 V 2 2 V 0 8 V 5 3 V 1 0 µA 1 0 µA Output low voltage Iout 2 5 mA Output high voltage Iout 2 5 mA 3 7 V 0 4 V Darlington drive output current Ports B and C only REXT 700 Ω VEXT 1 7 V 2 5 mA min 4 mA max Handshaking 3 wire requires 1 port Power on state Configured as input Data transfers Int...

Page 87: ...t 1 mA 3 7 V 0 45 V Triggers Digital Trigger Compatibility TTL Response Rising edge Pulse width 250 ns Bus Interface Slave Power Requirements from PC 5 VDC 10 180 mA 12 VDC 80 mA 12 VDC 450 mA Power available on rear connector 5 V at 1 A max Physical Dimensions 16 5 by 9 9 cm 6 5 by 3 9 in I O connector 50 pin male Environment Operating temperature 0 to 70 C Storage temperature 55 to 150 C Relativ...

Page 88: ... contains the manufacturer data sheet for the OKI 82C53 System Timing Controller integrated circuit OKI Semiconductor This circuit is used on the Lab PC Copyright OKI Semiconductor 1991 Reprinted with permission of copyright owner All rights reserved OKI Semiconductor Microprocessor Data Book 1990 1991 ...

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Page 100: ...tains the manufacturer data sheet for the OKI 82C55A Programmable Peripheral Interface integrated circuit OKI Semiconductor This circuit is used on the Lab PC Copyright OKI Semiconductor 1991 Reprinted with permission of copyright owner All rights reserved OKI Semiconductor Microprocessor Data Book 1990 1991 ...

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Page 117: ...are package such as NI DAQ NI DSP LabVIEW or LabWindows CVI with your Lab PC you need not read this appendix Refer to your software documentation for programming information Register Map The register map for the Lab PC is given in Table D 1 This table gives the register name the register address offset from the board s base address the type of the register read only write only or read and write an...

Page 118: ... Low Byte Register 06 Write only 8 bit DAC1 High Byte Register 07 Write only 8 bit 8253 Counter Timer Register Group A Counter A0 Data Register 14 Read and write 8 bit Counter A1 Data Register 15 Read and write 8 bit Counter A2 Data Register 16 Read and write 8 bit Counter A Mode Register 17 Write only 8 bit Timer Interrupt Clear Register 0C Write only 8 bit 8253 Counter Timer Register Group B Cou...

Page 119: ...escription Format The remainder of this register description chapter discusses each of the Lab PC registers in the order shown in Table D 1 Each register group is introduced followed by a detailed bit description of each register on the Lab PC For a detailed bit description of each register concerning the 8253 A or B chip on the Lab PC refer to Appendix B OKI 82C53 Data Sheet later in this manual ...

Page 120: ...f the A D and D A circuitry Command Register 3 enables or disables the interrupt and DMA operations Command Register 4 is used to select the analog input mode and also allows certain analog input conversion signals to be externally driven or received at the I O connector The Status Register reports the status of the A D conversion A D conversion error and the status of the interrupts When you star...

Page 121: ... are sampled alternately If this bit is cleared a single analog channel specified by MA 2 0 is sampled during the entire data acquisition operation See Programming Multiple A D Conversions with Channel Scanning in Appendix E Register Level Programming for the correct sequence involved in setting this bit For example in the RSE or NRSE mode of operation if MA 2 0 is 011 and SCANEN is set analog inp...

Page 122: ...10 2 2 3 4 5 011 3 2 3 6 7 100 4 4 5 0 1 101 5 4 5 2 3 110 6 6 7 4 5 111 7 6 7 6 7 In single ended mode RSE or NRSE if SCANEN is set analog channels MA 2 0 through 0 are sampled alternatively If SCANEN is cleared a single analog channel specified by MA 2 0 is sampled during the entire data acquisition operation In DIFF mode if SCANEN is set the analog channel pair corresponding to MA 2 0 specified...

Page 123: ... status of the GATE 0 input on the counter timer chip Counter Group A This bit can be used as a busy indicator for data acquisition operations because conversions are enabled as long as GATE 0 is high and Counter A0 is programmed appropriately 4 DMATC This bit reflects the status of the DMA terminal count If this bit is set and if the TCINTEN bit is set in Command Register 3 then the current inter...

Page 124: ...red This bit is set if a convert command is issued to the ADC while the last conversion is still in progress 0 DAVAIL This bit indicates whether conversion output is available If this bit is set the ADC is finished with the last conversion and the result can be read from the FIFO This bit is cleared if the FIFO is empty After writing to the ADCLR Register this bit is set Two 8 bit readings of FIFO...

Page 125: ... bit selects the binary coding scheme used for the DAC1 data If this bit is set a two s complement binary coding scheme is used for interpreting the 12 bit data Two s complement is useful if a bipolar output range is selected If this bit is cleared a straight binary coding scheme is used Straight binary is useful if a unipolar output range is selected 4 2SDAC0 This bit selects the binary coding sc...

Page 126: ...ared the Counter A0 is disabled except when the HWTRIG mode is used 1 HWTRIG Setting this bit allows the external EXTTRIG signal to start a data acquisition operation that is controlled by Counter A0 and Counter A1 If this bit is set a low to high transition on EXTTRIG enables Counter A0 and thus starts a data acquisition operation To use this mode the SWTRIG and PRETRIG bits should be cleared 0 P...

Page 127: ...Status Register The interrupt is serviced by writing to the A D Clear Register If ERRINTEN is cleared no error interrupts are generated 3 CNTINTEN This bit enables the Counter A2 output or the EXTUPDATE signal to cause interrupts If this bit is set an interrupt occurs when either EXTUPDATE or Counter A2 output makes a low to high transition This interrupt is cleared by writing to the Timer Interru...

Page 128: ...s ready to transfer data and an interrupt request is set via PC3 or PC0 of 8255A See Appendix C OKI 82C55A Data Sheet for details If DIOINTEN is cleared the interrupts from PC3 or PC0 are disabled 0 DMAEN This bit enables and disables the generation of DMA requests If DMAEN is set a DMA request is generated whenever an A D conversion result is available to be read from the FIFO If DMAEN is cleared...

Page 129: ... is cleared on board reset 3 SE __ D This bit along with jumper W4 selects the analog input mode of the Lab PC When clear it selects the single ended mode In this case multiplexer 1 selects Channels 0 7 specified by the channel select bits and multiplexer 2 selects AISENSE AIGND If W4 is configured in SE mode AISENSE AIGND gets tied to analog ground This is the RSE mode If W4 is configured as DIFF...

Page 130: ...e than disconnect the output of Counter B1 from the I O Connector if INTSCAN is clear always clear EOIRCV This bit is cleared on reset 0 INTSCAN This bit selects the DAQ mode When you set this bit the Lab PC performs interval data acquisition If you clear this bit continuous channel scanning is selected If interval channel scanning is selected scan sequences occur during a programmed time interval...

Page 131: ...ed to read the FIFO Reading the FIFO Register returns stored A D conversion results Writing to the Start Convert Register initiates an A D conversion Writing to the A D Clear Register clears the data acquisition circuitry Writing to the DMATC Clear Register clears the interrupt request generated by a DMA terminal count pulse Bit descriptions for the registers making up the Analog Input Register Gr...

Page 132: ...the A D FIFO Register can be read to retrieve a value If the DAVAIL bit is cleared the A D FIFO is empty in which case reading the A D FIFO Register returns meaningless information The values returned by reading the A D FIFO Register are available in two different binary formats straight binary or two s complement binary The binary format used is selected by the TWOSCMP bit in the Command Register...

Page 133: ...ts Low Byte 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description High Byte 7 0 D 15 8 These bits contain the high byte of the 16 bit sign extended two s complement result of a 12 bit A D conversion Values made up of D 15 0 therefore range from 2 048 to 2 047 decimal F800 to 07FF hex Two s complement mode is useful for bipolar analog input readings because the values read reflect the polari...

Page 134: ...s the FIFO and loads the last conversion value into the FIFO All error bits in the Status Register are cleared as well Notice that the FIFO contains one data word after reset so two consecutive FIFO readings are necessary after reset to empty the FIFO The data that is read should be ignored Address Base address 08 hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used ...

Page 135: ...ord Size 8 bit Bit Map Not applicable no bits used Note A D conversions can be initiated in one of two ways by writing to the Start Convert Register or by detecting an active low signal on either the Counter A0 output or the EXTCONV signal If the Start Convert Register is to initiate an A D conversion the Counter A0 output should be initialized to high state which must be followed by an ADCLEAR op...

Page 136: ...ments Corporation DMATC Interrupt Clear Register Writing to the DMA Terminal Count DMATC Clear Register clears the interrupt request asserted when a DMA terminal count pulse is detected Address Base address 0A hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used ...

Page 137: ...making up the Analog Output Register Group are used for loading the two 12 bit DACs in the two analog output channels DAC0 controls analog output Channel 0 DAC1 controls analog output Channel 1 These DACs should be written to individually Bit descriptions of the registers making up the Analog Output Register Group are given on the following pages ...

Page 138: ...ed when an active low pulse occurs on the output of Counter A2 or on the EXTUPDATE line on the I O connector Address Base address 04 hex Load DAC0 low byte Base address 05 hex Load DAC0 high byte Base address 06 hex Load DAC1 low byte Base address 07 hex Load DAC1 high byte Type Write only all Word Size 8 bit all Bit Map DACxH 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 Sign Extension Bits DACxL...

Page 139: ... three counters of Group A control onboard data acquisition timing and waveform generation The three counters of Group B are available for general purpose timing functions Each 8253 has three independent 16 bit counters and one 8 bit Mode Register The Mode Register is used to set the mode of operation for each of the three counters Writing to the Timer Interrupt Clear Register clears the interrupt...

Page 140: ...ation Counter A0 Data Register The Counter A0 Data Register is used for loading and reading back contents of 8253 A Counter 0 Address Base address 14 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7 0 D 7 0 8 bit Counter A0 contents ...

Page 141: ...anual Counter A1 Data Register The Counter A1 Data Register is used for loading and reading back contents of 8253 A Counter 1 Address Base address 15 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7 0 D 7 0 8 bit Counter A1 contents ...

Page 142: ...tion Counter A2 Data Register The Counter A2 Data Register is used for loading and reading back contents of 8253 A Counter A2 Address Base address 16 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7 0 D 7 0 8 bit Counter A2 contents ...

Page 143: ...The Counter A Mode Register selects the counter involved its read load mode its operation mode that is any of the 8253 s six operation modes and the counting mode binary or BCD counting The Counter A Mode Register is an 8 bit register Bit descriptions for each of these bits are given in Appendix B OKI 82C53 Data Sheet Address Base address 17 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 ...

Page 144: ...ration Timer Interrupt Clear Register Writing to the Timer Interrupt Clear Register clears the interrupt request asserted when a low pulse is detected on the Counter A2 output or on EXTUPDATE line Address Base address 0C hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used ...

Page 145: ...ual Counter B0 Data Register The Counter B0 Data Register is used for loading and reading back the contents of 8253 B Counter 0 Address Base address 18 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7 0 D 7 0 8 bit Counter B0 contents ...

Page 146: ...ion Counter B1 Data Register The Counter B1 Data Register is used for loading and reading back the contents of 8253 B Counter 1 Address Base address 19 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7 0 D 7 0 8 bit Counter B1 contents ...

Page 147: ...ual Counter B2 Data Register The Counter B2 Data Register is used for loading and reading back the contents of 8253 B Counter 2 Address Base address 1A hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7 0 D 7 0 8 bit Counter B2 contents ...

Page 148: ...nter B Mode Register selects the counter involved its read load mode its operation mode that is any of the 8253 s six operation modes and the counting mode binary or BCD counting The Counter Mode Register is an 8 bit register Bit descriptions for each of these bits are given in Appendix B OKI 82C53 Data Sheet of this manual Address Base address 1B hex Type Write only Word Size 8 bit Bit Map 7 6 5 ...

Page 149: ... integrated circuit The 8255A is a general purpose peripheral interface containing 24 programmable I O pins These pins represent the three 8 bit I O ports A B and C of the 8255A These ports can be programmed as two groups of 12 signals or as three individual 8 bit ports Bit descriptions for the registers in the Digital I O Register Group are given on the following pages ...

Page 150: ... A is configured for output the Port A Register can be written to in order to control the eight digital I O lines constituting Port A See Programming the Digital I O Circuitry in Appendix E Register Level Programming for information on how to configure Port A for input or output Address Base address 10 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name...

Page 151: ... B is configured for output the Port B Register can be written to in order to control the eight digital I O lines constituting Port B See Programming the Digital I O Circuitry in Appendix E Register Level Programming for information on how to configure Port B for input or output Address Base address 11 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name...

Page 152: ... handshaking latched mode If either Port A or Port B is configured for latched I O some of the bits in Port C are used for handshaking signals See Programming the Digital I O Circuitry in Appendix E Register Level Programming for a description of the individual bits in the Port C Register Address Base address 12 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D...

Page 153: ...utputs as well as selecting simple mode basic I O or handshaking mode strobed I O for transfers See Programming the Digital I O Circuitry in Appendix E Register Level Programming for a description of the individual bits in the Digital Control Register Address Base address 13 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 CW7 CW6 CW5 CW4 CW3 CW2 CW1 CW0 Bit Name Description 7 0 CW 7 0 ...

Page 154: ...rval Counter Data Register and the Interval Counter Strobe Register The Interval Counter Data Register is loaded with the count Writing to the Interval Counter Strobe Register loads this count into the Interval Counter The Interval Counter decrements with each conversion When the count reaches 0 the Interval Counter autoinitializes restoring the original count value Bit descriptions for the regist...

Page 155: ... samples of a single channel that will be acquired between intervals See Programming Multiple A D Conversions in Single Channel Interval Acquisition Mode in Appendix E Register Level Programming for a description of the programming sequence Address Base address 1E hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7 0 D 7 0 Interval Counter cou...

Page 156: ...f the Interval Counter Data Register into the Interval Counter This action arms the Interval Counter which then decrements with each conversion pulse Address Base address 1F hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 Bit Name Description 7 1 0 Each of these bits must be 0 for proper operation of the Lab PC 0 1 This bit must be 1 for proper operation of the Lab PC ...

Page 157: ...specific register bits should be set or cleared without changing the current state of the remaining bits in the register However writing to these registers affects all register bits simultaneously You cannot read these registers to determine which bits have been set or cleared in the past therefore you should maintain a software copy of the write only registers This software copy can then be read ...

Page 158: ...owing state Counter A0 output is high Counter A1 output is high This disables EXTCONV All interrupts are disabled EXTTRIG is disabled The timebase for Counter A0 is the onboard 1 MHz source Analog input circuitry is initialized to RSE mode with a gain of 1 and Channel 0 selected The A D FIFO is cleared The Command Registers are initialized to 00 hex on power up Thus straight binary coding is selec...

Page 159: ...he EXTCONV line To enable Counter A0 and the EXTCONV the SWTRIG bit in Command Register 2 must be set and OUTA1 must be low Alternatively a conversion can be performed by writing to the Start Convert Register Once an A D conversion is initiated the ADC stores the result in the A D FIFO at the end of its conversion cycle or after a rising edge on OUTA0 whichever occurs later In case of EXTCONV init...

Page 160: ...rsion result can be returned from the A D FIFO as a 16 bit two s complement or straight binary value by setting or clearing the TWOSCMP bit in Command Register 1 If the analog input circuitry is configured for the input range 0 to 10 V straight binary mode should be used clear the TWOSCMP bit Straight binary mode returns numbers between 0 and 4 095 decimal when the A D FIFO Register is read If the...

Page 161: ...rred to in this manual as a data acquisition operation Two types of data acquisition operations are available on the Lab PC Controlled acquisition mode Freerun acquisition mode In controlled acquisition mode two counters Counters A0 and A1 are required for a data acquisition operation Counter A0 is used as a sample interval counter while Counter A1 is used as a sample counter In this mode a specif...

Page 162: ...base source for Counter A0 The analog input channel and gain are selected by writing to Command Register 1 The SCANEN bit must be cleared for data acquisition operations on a single channel See the Command Register 1 bit description earlier in this chapter for gain and analog input channel bit patterns If Counter B0 is being used as a timebase for Counter A0 then the TBSEL bit in Command Register ...

Page 163: ...re 8 bit write operations All values given are hexadecimal a Write 34 to the Counter A Mode Register select Counter A0 Mode 2 b Write the least significant byte of the sample interval to the Counter A0 Data Register c Write the most significant byte of the sample interval to the Counter A0 Data Register Use the following sequence to program the sample counter a Write 70 to the Counter A Mode Regis...

Page 164: ...is the A D FIFO is full and cannot accept any more data This condition occurs if the software loop reading the A D FIFO Register is not fast enough to keep up with the A D conversion rate When an overflow occurs at least one A D conversion result is lost An overflow condition has occurred if the OVERFLOW bit in the Status Register is set An overrun condition occurs if a second A D conversion is in...

Page 165: ...ificant byte of the timebase count to the Counter B Data Register c Write the most significant byte of the timebase count to the Counter B Data Register For example programming a timebase of 10 µs requires a timebase count of 10 µs 0 5 µs 20 3 Program the sample interval counter Counter A0 Counter A0 of the 8253 A Counter Timer is used as the sample interval counter A high to low transition on OUT...

Page 166: ...the A D FIFO Register to obtain the result DMA or interrupts can also be used to service the data acquisition operation These topics are discussed in the A D Interrupt Programming and Programming DMA Operation sections later in this appendix Two error conditions may occur during a data acquisition operation an overflow error or an overrun error These error conditions are reported through the Statu...

Page 167: ...onversion data acquisition operation In this mode referred to as posttriggering the sample interval counter is gated off until a low to high edge is sensed on EXTTRIG No samples are collected until EXTTRIG makes its low to high transition Transitions on the EXTCONV line are also ignored until a low to high edge is sensed on EXTRIG followed by a low to high edge on EXTCONV input Using the EXTTRIG S...

Page 168: ...ed under software control Programming in Controlled Acquisition Mode Posttrigger Mode The following programming steps are required for a data acquisition operation in controlled acquisition mode using EXTCONV In the following programming sequence EXTTRIG is used as a posttrigger signal that is data acquisition is not started until a rising edge is detected on the EXTTRIG input 1 Disable EXTCONV an...

Page 169: ... program the counters use the following programming sequence a Write 70 hex to the Counter A Mode Register select Counter A1 Mode 0 This step sets the output of Counter A1 OUTA1 low b Write the least significant byte of M 2 where M is the sample count to the Counter A1 Data Register c Write the most significant byte of M 2 where M is the sample count to the Counter A1 Data Register 6 Select posttr...

Page 170: ...val is too small sample rate is too high An overrun condition has occurred if the OVERRUN bit in the Status Register is low The minimum recommended sampling interval on the Lab PC is 16 µs Both the OVERFLOW and OVERRUN bits in the Status Register are reset by writing to the A D Clear Register Pretrigger Mode The following programming steps are required for a data acquisition operation in controlle...

Page 171: ...o the A D Clear Register also sets the GATA1 bit low A D conversions are not counted until GATA1 is set high by a rising edge on the EXTTRIG input 4 Program Counter A1 and enable EXTCONV input Counter A1 of the 8253 A Counter Timer is used as a sample counter The sample counter counts the number of A D conversions and disable conversions when the programmed count is reached The sample count must b...

Page 172: ... to check the DAVAIL bit An overflow condition occurs if more than 16 A D conversions have been stored in the A D FIFO without the A D FIFO being read that is the A D FIFO is full and cannot accept any more data This condition occurs if the software loop reading the A D FIFO Register is not fast enough to keep up with the A D conversion rate When an overflow occurs at least one A D conversion resu...

Page 173: ...hest channel number in the scan sequence the gain and the input polarity to Command Register 1 The SCANEN bit must be cleared during this first write to Command Register 1 2 Write the same configuration value again to Command Register 1 The SCANEN bit however must be set during the second write to Command Register 1 Scanning can be enabled in either controlled or freerun acquisition mode Either Co...

Page 174: ...egister If you intend to use Counter B1 to generate your scan interval pulses remember to connect a source to the CLKB1 line on the I O connector 4 Finally take the Analog Configuration Register bit pattern used in step 1 set the SCANEN bit and write the value to the Analog Configuration Register As soon as this value is written the interval scanning circuitry is gated on A channel scanning cycle ...

Page 175: ...ng counter All writes are 8 bit write operations All values are hexadecimal a Write 74 to the Counter B Mode Register select Mode 2 b Write the least significant byte of the interval count to the Counter B1 Data Register c Write the most significant byte of the scan interval count to the Counter B1 Data Register 6 Use a software trigger to initiate the operation Note that you must program the samp...

Page 176: ...se the DMA terminal count interrupt set the DMAEN and TCINTEN bits in Command Register 3 If these bits are set an interrupt is generated and the DMATC bit in the Status Register is set whenever the DMATC pulse is detected Writing to the DMATC Clear Register clears this interrupt condition Programming the Analog Output Circuitry The analog output circuitry on the Lab PC uses double buffered DACs Th...

Page 177: ... 2 Configuration and Installation Table E 3 shows the output voltage versus digital code for a unipolar analog output configuration Table E 4 shows the voltage versus digital code for a bipolar analog output configuration The following formula calculates the voltage output versus digital code for a unipolar analog output configuration and straight binary coding Vout 10 0 digital code 4 096 The dig...

Page 178: ...terrupts can be used for writing successive values in a sequence to the DAC Data Registers during a waveform generation operation The CNTINTEN bit in Command Register 3 enables and disables Counter A2 and EXTUPDATE driven interrupts See Chapter 3 Signal Connections for timing requirements on the EXTUPDATE signal The following programming steps are required for waveform generation using interrupts ...

Page 179: ...idual 8 bit ports The following paragraphs include programming information for the Lab PC The three 8 bit ports are divided into two groups Group A and Group B two groups of 12 signals One 8 bit configuration or control word specifies the mode of operation for each group The control bits of Group A configure Port A A0 through A7 and the upper 4 bits nibble of Port C C4 through C7 The control bits ...

Page 180: ...h nibble 1 input 0 output Figure E 1 Control Word Format with Control Word Flag Set to 1 D7 D3 D2 D1 D0 Control Word Flag 0 Bit Set Reset Bit Set Reset 1 set 0 reset Bit Select 000 001 010 111 X X X Figure E 2 Control Word Format with Control Word Flag Set to 0 This section describes the Digital Control Register which is used to program the 8255A ports in any one of the three modes discussed earli...

Page 181: ...mode is for simple I O operations for each of the ports No handshaking is required data is simply written to or read from a specified port Mode 0 has the following features Two 8 bit ports A and B and two 4 bit ports upper and lower nibble of Port C Any port can be input or output Outputs are latched but inputs are not latched Control Words Mode 0 provides simple I O functions for each of the thre...

Page 182: ... Input Input 10011000 Input Input Output Output 10011001 Input Input Output Input 10011010 Input Input Input Output 10011011 Input Input Input Input 1 Upper nibble of Port C 2 Lower nibble of Port C Programming Examples Example 1 Configure all three ports A B and C as output ports in Mode 0 Write 80 hex to the Digital Control Register Write 8 bit data to the Port A Port B or Port C Register as app...

Page 183: ... contains one 8 bit port and one 4 bit control data port The 8 bit port can be either an input port or an output port and the 4 bit port is used for control and status information for the 8 bit port The transfer of data is synchronized by handshaking signals in the 4 bit port The control word written to the Digital Control Register to configure Port A for input in Mode 1 is shown here Bits PC6 and...

Page 184: ...status for Port A When INTEA is high and IBFA is high this bit is high indicating that an interrupt request is asserted 2 INTEB Interrupt enable bit for Port B Enables interrupts from the 8255A for Port B Controlled by bit set reset of PC2 1 IBFB Input buffer full for Port B High indicates that data has been loaded into the input latch for Port B 0 INTRB Interrupt request status for Port B When IN...

Page 185: ...Port B Output The control word written to the Digital Control Register to configure Port A for output in Mode 1 is shown here Bits PC4 and PC5 of Port C can be used as extra input or output lines when Port A uses Mode 1 output Port C bits PC4 and PC5 1 input 0 output 1 0 X X X 0 1 0 1 7 6 5 4 3 2 1 0 The control word written to the Digital Control Register to configure Port B for output in Mode 1 ...

Page 186: ...st status for Port A When INTEA is high and OBFA is high this bit is high indicating that an interrupt request is asserted 2 INTEB Interrupt enable bit for Port B If this bit is high interrupts are enabled from the 8255A for Port B Controlled by bit set reset of PC2 1 OBFB Output buffer full for Port B Low indicates that the CPU has written data out to Port B 0 INTRB Interrupt request status for P...

Page 187: ...pt generation and enable disable functions are also available Other features of this mode include the following Used in Group A only Port A and upper nibble of Port C One 8 bit bidirectional port Port A and a 5 bit control status port Port C Both inputs and outputs are latched Control Words In Mode 2 an 8 bit bus can be used for both input and output transfers without changing the configuration Th...

Page 188: ... buffer full Low indicates that the CPU has written data out to Port A 6 INTE1 Interrupt enable bit for output If this bit is set interrupts are enabled from the 8255A for OBF Controlled by bit set reset of PC6 5 IBFA Input buffer full High indicates that data has been loaded into the input latch of Port A 4 INTE2 Interrupt enable bit for input If this bit is set interrupts are enabled from the 82...

Page 189: ...to Port A Wait for bit 5 of Port C IBFA to be set indicating that data is available in Port A to be read Read data from Port A Single Bit Set Reset Control Words Table E 6 shows the control words for setting or resetting each bit in Port C Notice that bit 7 of the control word is cleared for programming the set reset option for the bits of Port C Table E 6 Port C Set Reset Control Words Bit Set Bi...

Page 190: ...rcuitry Interrupts can be enabled on PC0 PC3 or both PC0 and PC3 by setting the DIOINTEN bit in Command Register 3 See the Command Register 3 description earlier in this chapter for corresponding bit positions An external signal can be used to generate an interrupt when Port A or B is in Mode 0 Program PC0 or PC3 for input and connect the external signal that should trigger an interrupt to PC0 or ...

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Page 192: ...Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax Phone Computer brand Model Processor Operating system include version number Clock Speed MHz RAM MB Display adapter Mouse yes no Other adapters installed Hard disk capacity MB Brand Instruments used National Instrum...

Page 193: ... Output Channel 1 Configuration _____________________________________________ Factory Setting Bipolar W2 A B Analog Input Configuration _____________________________________________ Factory Setting Bipolar W3 A B NI DAQ LabVIEW or LabWindows CVI Version _____________________________________________ Other Products Microprocessor _____________________________________________ Clock Frequency ________...

Page 194: ...6 Part Number 320502B 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address Phone Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway MS ...

Page 195: ...Gauge BCD binary coded decimal C Celsius CMOS complementary metallic oxide semiconductor D A digital to analog DAC D A converter dB decibels DC direct current DIFF differential DIP dual inline package DMA direct memory access EISA Extended Industry Standard Architecture F farads FIFO first in first out ft feet hex hexadecimal Hz hertz I O input output in inches ksamples 1 000 samples LED light emi...

Page 196: ...e RSE referenced single ended RTSI Real Time System Integration s seconds SCXI Signal Conditioning eXtensions for Instrumentation bus SDK System Development Kit STC system timing controller TTL transistor to transistor logic V volts VDC volts direct current VEXT external volts VIH volts input high VIL volts input low Vin volts in VOH volts output high VOL volts output low Vout output voltage Vref ...

Page 197: ...scanning E 18 single channel interval acquisition mode E 19 Counter B2 Data Register D 31 overview D 23 register map D 2 Timer Interrupt Clear Register D 28 8255A Digital I O Register Group D 33 to D 37 Digital Control Register D 37 overview D 33 Port A Register D 34 Port B Register D 35 Port C Register D 36 programming E 23 to E 34 control word format control word flag set to 0 figure E 24 contro...

Page 198: ...gnal table 3 3 Analog Configuration Register E 18 analog input calibration 5 3 to 5 6 bipolar input procedure 5 4 to 5 5 board configuration 5 4 unipolar input procedure 5 5 to 5 6 voltage values of ADC input figure 5 4 analog input circuitry block diagram 4 4 theory of operation 4 5 analog input circuitry programming A D FIFO output binary modes E 4 clearing analog input circuitry E 5 programming...

Page 199: ...ications A 4 to A 5 dynamic characteristics A 4 explanation A 4 to A 5 output characteristics A 4 stability A 4 transfer characteristics A 4 voltage output A 4 B base I O address selection 2 3 to 2 5 example switch settings figure 2 4 factory settings table 2 3 possible settings with corresponding base I O address and base address I O space table 2 5 bipolar input mode bipolar input signal range v...

Page 200: ...channel scanning cycle E 17 circuitry See theory of operation circular buffer E 11 CLK signal See GATE CLK and OUT signals CLKB2 signal table 3 3 CNTINT bit data acquisition timing 3 24 description D 7 interrupt programming for analog output circuitry E 23 CNTINTEN bit data acquisition timing 3 23 description D 11 interrupt programming for analog output circuitry E 23 Command Register 1 channel sc...

Page 201: ...trolled acquisition mode multiple A D conversions external timing E 12 to E 16 posttrigger mode E 12 to E 14 pretrigger mode E 14 to E 16 overview E 5 programming steps E 6 to E 8 single input channel E 6 to E 8 CONVERT signal posttrigger data acquisition timing figure 3 22 Counter A Mode Register description D 27 interrupt programming for analog output circuitry E 22 to E 23 Counter A0 Data Regis...

Page 202: ...le 4 8 unipolar analog input signal range versus gain table 4 8 multiple channel scanned data acquisition 4 6 to 4 7 single channel data acquisition 4 6 data acquisition timing connections EXTCONV signal timing figure 3 21 EXTUPDATE signal timing generating interrupts figure 3 24 updating DAC output figure 3 24 posttrigger timing figure 3 22 pretrigger timing figure 3 23 DATA signal description 3 ...

Page 203: ... D 7 DMA request generation E 20 DMATC Interrupt Clear Register description D 20 DMA request generation E 20 documentation conventions used in manual xii National Instruments documentation xiii organization of manual xi xii E ECKDRV bit D 14 ECLKRCV bit D 13 environment specifications A 6 EOIRCV bit description D 14 multiple A D conversions interval scanning E 17 to E 18 single channel interval ac...

Page 204: ... block diagram 4 14 event counting application figure 3 25 frequency measurement application figure 3 26 general purpose timing 3 24 to 3 27 timing requirements figure 3 27 general purpose timing connections event counting 3 25 application with external switch gating figure 3 25 frequency measurement 3 26 application figure 3 26 pretrigger timing figure 3 23 pulse and square wave generation 3 25 p...

Page 205: ... 2 8 factory setting of IRQ5 figure 2 7 interrupts control circuitry 4 3 generating with EXTUPDATE signal figure 3 24 types of interrupts 4 3 to 4 4 Interval Counter Register Group D 38 to D 40 Interval Counter Data Register description D 39 single channel interval acquisition mode E 19 Interval Counter Strobe Register D 40 overview D 38 register map table D 2 interval scanning for multiple A D co...

Page 206: ... status word bit definitions E 28 programming example E 29 timing 3 18 Mode 1 output E 29 to E 31 control words E 29 Port C pin assignments E 30 Port C status word bit definitions E 30 programming example E 31 timing 3 19 Mode 2 bidirectional timing 3 20 Mode 2 operation E 31 to E 34 control words E 31 to E 32 Port C pin assignments E 33 Port C status word bit definitions E 32 programming example ...

Page 207: ... interrupt programming E 20 description D 7 OVERRUN bit A D FIFO overrun condition clearing the analog input circuitry E 5 controlled acquisition programming E 8 posttrigger mode E 14 pretrigger mode E 16 freerun acquisition programming E 10 A D interrupt programming E 20 description D 8 P PAO 0 7 signal table 3 3 PBO 0 7 signal table 3 3 PC bus interface 2 1 factory settings table 2 3 PC I O chan...

Page 208: ...gnments E 30 Port C status word bit definitions E 30 programming example E 31 Mode 2 operation E 31 to E 34 control words E 31 to E 32 Port C pin assignments E 33 Port C status word bit definitions E 32 programming example E 33 single bit set reset control words E 33 single bit set reset feature E 34 DMA operation E 20 initializing Lab PC E 1 to E 2 interrupt programming for analog output circuitr...

Page 209: ... 15 Mode 1 input timing 3 18 Mode 1 output timing 3 19 Mode 2 bidirectional timing 3 20 Port C pin connections 3 15 to 3 16 timing specifications 3 16 to 3 17 input configurations 3 6 to 3 28 common mode signal rejection considerations 3 12 differential connection considerations 3 6 to 3 9 floating signal sources 3 8 to 3 9 ground referenced signal sources 3 7 to 3 8 recommended configurations for...

Page 210: ...mper and switch settings SWTRIG bit controlled acquisition mode E 7 posttrigger mode E 12 pretrigger mode E 16 description D 10 freerun acquisition mode E 10 multiple A D conversions using EXTTRIG signal E 11 system noise A 3 T TBSEL bit controlled acquisition mode E 6 description D 9 TCINTEN bit D 11 technical support F 1 theory of operation analog input circuitry 4 5 block diagram 4 4 analog out...

Page 211: ...nnel interval timing figure 4 14 two channel interval scanning timing figure 4 13 timing I O specifications A 5 to A 6 trigger specifications A 6 two channel interval scanning timing figure 4 13 TWOSCMP bit description D 6 returning A D conversion result E 4 U unipolar input mode configuration 2 14 unipolar input signal range versus gain table 4 8 voltage versus A D conversion values table E 4 uni...

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