©
National Instruments Corporation
I-1
Index
A
acquisition, scaling, and region-of-interest (ROI)
circuitry, 3-4
acquisition start conditions, 3-5
acquisition window control, 3-5 to 3-6
active pixel region (acquisition
window), 3-5
interlaced video, 3-6
region of interest, 3-5
scaling down circuitry, 3-6
advanced clock generation circuitry, 3-3
B
block diagram of IMAQ PCI/PXI-1422
(figure), 3-2
bus master PCI interface, 3-4
C
clock signals
Master Clock<0..1>
±
signal (table), 4-3
Pixel Clock
±
signal (table), 4-3
clocks
advanced clock generation circuitry, 3-3
specifications, A-1
configuration
flowchart (figure), 2-3
setting up IMAQ PCI/PXI-1422, 2-2
Control<0..3>
±
signal (table), 4-3
CTS signal (table), 4-3
D
DAQ, integration with, 1-6
data formatter, multiple-tap, 3-3
Data<0..15>
±
signal (table), 4-3
DCD signal (table), 4-3
delayed acquisition start conditions, 3-5
differential-level/TTL level converters, 3-2
DMA controllers, 3-4
DSR signal (table), 4-3
DTR signal (table), 4-3
E
Enable<A..D>
±
signal (table), 4-3
environment specifications, A-3
equipment, optional, 2-2
external connection specifications, A-1
External Trigger<0..3> signal (table), 4-3
F
frame/field selection, 3-5
G
GND signal (table), 4-3
H
hardware overview, 3-1 to 3-6
acquisition, scaling, ROI, 3-4
acquisition window control, 3-5 to 3-6
advanced clock generation, 3-3
block diagram (figure), 3-2
board configuration NVRAM, 3-4
bus master PCI interface, 3-4
differential/TTL level converters, 3-2
high-speed timing, 3-4
LUTs, 3-2
multiple-tap data formatter, 3-3
RS-232 serial interface, 3-3
scatter-gather DMA controllers, 3-4
