Index
©
National Instruments Corporation
I-5
counter/timer, programming. See
general-purpose counter/timer.
customer communication, xv, A-1 to A-2
D
D<15..0> bits, 3-8
DAC FIFO Data Register, 3-18
DAC0 Direct Data Register, 3-19
DAC1 Direct Data Register, 3-20
DAC FIFO Clear Register
description, 3-24
register map, 3-3
DAC FIFO Data Register
description, 3-18
register map, 3-2
DAC0 Direct Data Register, 3-19
description, 3-19
register map, 3-2
DAC1 Direct Data Register
description, 3-20
register map, 3-2
DACs
analog output circuitry, 2-21 to 2-22
analog triggering, 4-53
DACSel bit, 3-16
DAQ-STC programming examples. See
programming examples.
DAQ-STC Register Group
overview, 3-24
register map, 3-2
DAQ-STC system timing controller, xiii
counter diagram, 2-24
programming. See programming
examples.
data acquisition timing circuitry, 2-11 to 2-18
ADC timing (figure), 2-12
block diagram, 2-8
data acquisition sequence timing,
2-12 to 2-18
multirate scanning with ghost,
2-16 to 2-18
advantages (figure), 2-17
analog input configuration memory
(table), 2-18
occurrences of conversion on channel
1 (figure), 2-17
successive scans (figure), 2-17
multirate scanning without ghost,
2-14 to 2-16
scanning three channels with 4:2:1
sampling rate (figure), 2-16
scanning two channels (figure), 2-15
1:x sampling rate, 2-15
3:1:1 sampling rate, 2-16
single-read timing, 2-11 to 2-12
timing of scan (figure), 2-14
differential channel assignments (table), 3-13
digital I/O circuitry, 2-24
digital I/O programming examples
performing digital I/O, 4-7 to 4-8
windowed registers, 4-7
dither circuitry, 2-10
DitherEn bit, 3-9 to 3-10
DIV counter, 2-12
DMA Control Register Group
AI AO Select Register, 3-22
G0 G1 Select Register, 3-23
overview, 3-21
register map, 3-2
DMA programming, 4-57 to 4-59
analog input examples, 4-17 to 4-20
STC scanning with DMA,
4-17 to 4-20
generating DMA requests, 4-57 to 4-58
Link Chaining Mode for DMA transfer,
4-58 to 4-59
programming MITE for different DMA
transfers, 4-20 to 4-21
structure (figure), 4-57
