National Instruments E Series Programmer'S Manual Download Page 129

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Chapter 5

Calibration

National Instruments Corporation

5-7

PCI E Series RLPM

Table 5-3.

PCI-MIO-16XE-10, PCI-6031E, PCI-6032E, and PCI-6033E EEPROM Map

EEPROM

Address

Data Stored at EEPROM

Address

Data Type

CALDAC

Type

CALDAC

Address

Ser

DacLd

Line

511

NI-DAQ Board Code

—

510

Revision

—

509

Sub-revision

—

508

Year of last factory
fabrication

—

507

Month of last factory
fabrication

—

506

Day of last factory
fabrication

—

431

Factory reference MSB

—

430

Factory reference LSB

—

429

CALDAC factory constant
MSB

Bipolar AI

DAC8043

(12-bit)

—

428

CALDAC factory constant
LSB

Bipolar AI

DAC8043

(12-bit)

—

427

CALDAC factory constant

Bipolar AI

8800

(8-bit)

426

CALDAC factory constant

Bipolar AI

8800

(8-bit)

425

CALDAC factory constant

Bipolar AI

8800

(8-bit)

424

CALDAC factory constant

Bipolar AI

8800

(8-bit)

423

CALDAC factory constant
MSB

Unipolar AI

DAC8043

(12-bit)

—

422

CALDAC factory constant
LSB

Unipolar AI

DAC8043

(12-bit)

—

421

CALDAC factory constant

Unipolar AI

8800

(8-bit)

Summary of Contents for E Series

Page 1: ...DAQ PCI E Series Register Level Programmer Manual Multifunction I O Boards for PCI Bus Computers PCI E Series RLPM November 1998 Edition Part Number 341079B 01...

Page 2: ...3336 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 6120092 Italy 02 413091...

Page 3: ...R INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contrac...

Page 4: ...og Input Circuitry 2 8 Data Acquisition Timing Circuitry 2 11 Single Read Timing 2 11 Data Acquisition Sequence Timing 2 12 Posttrigger and Pretrigger Acquisition 2 18 Analog Triggering 2 19 Analog Ou...

Page 5: ...0 G1 Select Register 3 23 DAQ STC Register Group 3 24 FIFO Strobe Register Group 3 24 Configuration Memory Clear Register 3 24 ADC FIFO Clear Register 3 24 DAC FIFO Clear Register 3 24 Chapter 4 Progr...

Page 6: ...pose Counter Timer 4 45 Example 1 4 45 Example 2 4 47 Example 3 4 49 RTSI Trigger Lines Programming Considerations 4 52 Analog Triggering 4 52 Interrupt Programming 4 56 Interrupt Sharing 4 56 DMA Pro...

Page 7: ...Rate 2 16 Figure 2 14 Multirate Scanning without Ghost 2 17 Figure 2 15 Occurrences of Conversion on Channel 1 in Example 3 2 17 Figure 2 16 Successive Scans Using Ghost 2 17 Figure 2 17 Analog Outpu...

Page 8: ...I 6071E EEPROM Map 5 3 Table 5 2 PCI MIO 16XE 50 EEPROM Map 5 5 Table 5 3 PCI MIO 16XE 10 PCI 6031E PCI 6032E and PCI 6033E EEPROM Map 5 7 Table 5 4 PCI 6023E EEPROM Map 5 9 Table 5 5 PCI 6024E and PC...

Page 9: ...DAQ STC Technical Reference Manual You must use your register level programmer manual along with the DAQ STC Technical Reference Manual for a complete understanding of PCI E Series board programming U...

Page 10: ...w to calibrate the analog input and output sections of the PCI E Series boards by reading calibration constants from the EEPROM and writing them to the calibration DACs Appendix A Customer Communicati...

Page 11: ...s also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions and for statements and comments...

Page 12: ...ote Revision C and earlier versions of the PCI MIO 16XE 50 use the MITE as the interface chip and do not support the DMA feature The PCI E Series boards use the National Instruments DAQ STC system tim...

Page 13: ...tion generate digital signals for communication and control SCXI is the instrumentation front end for plug in DAQ boards Your PCI E Series board is completely software configurable Refer to your PCI E...

Page 14: ...ter Configuration Memory REF Buffer Programmable Gain Amplifier Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs 4 Calibration DACs DAC0 DAC1 DAQ STC Analog Input...

Page 15: ...alibration DACs DAC0 DAC1 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 8 8 AI Control...

Page 16: ...EF Calibration DACs Dither Generator Calibration DACs 82C55A DAC0 DAC1 NOT ON 6023E Analog Output DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Interface Counter...

Page 17: ...nterface PCI Bus Interface Address 5 Timing PFI Trigger I O Connector 3 RTSI Bus Digital I O 8 16 Bit Sampling A D Converter Configuration Memory NI PGIA Gain Amplifier Calibration Mux Mux Mode Select...

Page 18: ...anual is skeletal in nature and is sufficient in most cases For register level programming information refer to the DAQ STC Technical Reference Manual Timing PFI Trigger I O Connector 2 2 RTSI Bus PCI...

Page 19: ...s use only 8 bit or 16 bit transfers The bus mastering capabilities of the MITE provides high speed data transfer between the board and system memory The MITE contains three DMA channels that can be u...

Page 20: ...uitry The PCI E Series boards have 16 and 64 analog input channels and a timing core within the DAQ STC that is dedicated to analog input operation Figure 2 7 shows a general block diagram for the ana...

Page 21: ...to use for each conversion Each entry in the configuration memory includes channel type channel number bank gain polarity dither general trigger and last channel The configuration memory is a 512 ent...

Page 22: ...on while the bank field indicates which bank of 16 channels is active This bank field is used on boards that have more than 16 channels These bits control the input multiplexers The programmable gain...

Page 23: ...E Series boards use sampling successive approximation ADCs with 12 or 16 bits of resolution with maximum conversion rates between 50 s and 800 ns The converter can resolve its input range into 4 096 d...

Page 24: ...ust input offset output offset and gain errors associated with the analog input section When the board leaves the factory the upper one fourth of the EEPROM is protected and cannot be overwritten The...

Page 25: ...gating you must program the boards to automatically generate timed signals that initiate and gate conversions This is known as a data acquisition DAQ sequence Data Acquisition Sequence Timing The foll...

Page 26: ...configuration memory advances by one and selects the next set of analog input conditions channel number gain polarity etc A STOP pulse ends the SCAN sequence This STOP could be generated in two ways...

Page 27: ...ends the scan Example 1 allows you to sample all three channels at a rate of 10 kS s per channel 100 s sample interval period To achieve different rates for different channels you must do multirate sc...

Page 28: ...of sampling rates The effective scan interval of the slower channel will be at the rate of the faster channel This implementation requires x scan sequences in the configuration memory Also you can imp...

Page 29: ...but the data is not stored in the analog input FIFO In other words a conversion is performed and the data is thrown away By using this option multirate scanning with ratios such as x y are possible w...

Page 30: ...ve occurrences of convert pulses in Figure 2 14 Figure 2 15 Occurrences of Conversion on Channel 1 in Example 3 To rectify the problem use ghost as illustrated in Figure 2 16 Figure 2 16 Successive Sc...

Page 31: ...sed as a trigger line in the posttrigger mode Since the START1 pulse can be generated through software by strobing a bit all of the examples discussed so far can be generally categorized as posttrigge...

Page 32: ...lows continuous software initiated acquisition to continue indefinitely In this mode the SC gets reloaded each time it counts down to zero The acquisition can be stopped by disarming the SC When the S...

Page 33: ...ed here refer to the DAQ STC Technical Reference Manual Analog Output and Timing Circuitry The PCI E Series boards except the PCI 6023E PCI 6032E and PCI 6033E have two analog output channels and a ti...

Page 34: ...C signal If you apply an AC reference the analog output channel acts as a signal attenuator and the AC signal appears at the output attenuated by the digital code For unipolar output the voltage is si...

Page 35: ...put repetitively without any further data transfer to the FIFO The PCI MIO 16XE 50 PCI 6024E and PCI 6025E has a zero depth virtual FIFO Analog Output Timing Circuitry This section describes the diffe...

Page 36: ...ulse This data transfer will be from the analog output FIFO Some of the boards have large 2 kword FIFOs and some have 512 word FIFOs others are zero deep virtual FIFOs The large FIFOs are true FIFOs w...

Page 37: ...s used as the serial data in pin and DIO0 is used as the serial data out pin You can use handshaking with the EXTSTROBE pin to do either parallel or serial data transfer Refer to the DAQ STC Technical...

Page 38: ...tri state the corresponding DIO line The SOURCE of these counters can be selected to be one of the 10 PFI lines the seven RTSI lines the internal 20 MHz or 100 kHz timebases or the TC of the other co...

Page 39: ...us signals can be driven by eight internally generated timing signals and the four RTSI board signals Similarly the four RTSI board signals can be driven by any of the RTSI trigger bus signals Of the...

Page 40: ...ess of the PCI E Series board Registers are grouped in the table by function Each register group is introduced in the order shown in Table 3 1 then described in detail including a bit by bit descripti...

Page 41: ...n DAC FIFO Data DAC0 Direct Data DAC1 Direct Data 16 1E 18 1A 22 30 24 26 Write only Write only Write only Write only 16 bit 16 bit 16 bit 16 bit DMA Control Register Group AI AO Select G0 G1 Select 0...

Page 42: ...and bit map of the register followed by a description of each bit The register bit map shows a diagram of the register with the MSB shown on the left bit 15 for a 16 bit register bit 7 for an 8 bit r...

Page 43: ...data previously shifted into the DACs 3 SerDacLd0 Serial DAC Load0 This bit is used to load the first set of serial DACs with the serial data previously shifted into the DACs 2 EEPromCS EEPROM Chip Se...

Page 44: ...Address Base address 0F hex Type Write only Word Size 8 bit Bit Map Bit Name Description 7 Int Ext Trig Internal External Analog Trigger This bit controls the analog trigger source If this bit is set...

Page 45: ...he status of the calibration EEPROM output Address Base address 01 hex Type Read only Word Size 8 bit Bit Map Bit Name Description 7 1 Reserved Reserved Ignore returned bits 0 PROMOUT EEPROM Output Da...

Page 46: ...used to read the ADC FIFO contents Reading the ADC FIFO Data Register location transfers data from the PCI E Series ADC data FIFO to the computer Writing to the Configuration Memory Low and Configura...

Page 47: ...le in two different binary formats straight binary which generates only positive numbers or two s complement binary which generates both positive and negative numbers The binary format used is determi...

Page 48: ...than one occurrence of the LastChan bit is possible in the configuration memory list for the interval scanning mode For example there can be multiple scan sequences in one memory list 14 13 Reserved...

Page 49: ...e in straight binary format When Unip Bip is clear the ADC is configured for bipolar operation and values The data values are two s complement and automatically sign extended 2 0 Gain 2 0 Channel Gain...

Page 50: ...Address Base address 12 hex Type Write only Word Size 16 bit Bit Map Bit Name Description 15 Reserved Reserved Always write 0 to these bits 11 6 14 12 ChanType 2 0 Channel Type 2 through 0 These bits...

Page 51: ...hannel Select 3 through 0 These bits indicate which channel is active for the current resource in the scan list Not every resource uses all 16 channels in a bank Channel assignments for all PCI E Seri...

Page 52: ...h10 0011 ACh3 ACh11 0100 ACh4 ACh12 0001 ACh5 ACh13 0110 ACh6 ACh14 0111 ACh7 ACh15 1xxx Reserved Reserved Table 3 6 Nonreferenced Single Ended Channel Assignments Chan Type 2 0 NRSE Chan 3 0 PGIA PGI...

Page 53: ...RSE Chan 3 0 PGIA PGIA 0000 ACh0 AIGround 0001 ACh1 AIGround 0010 ACh2 AIGround 0011 ACh3 AIGround 0100 ACh4 AIGround 0101 ACh5 AIGround 0110 ACh6 AIGround 0111 ACh7 AIGround 1000 ACh8 AIGround 1001...

Page 54: ...sferred to the DACs in one of two ways Data can be directly sent to the DACs from the host computer or buffered from the host by the DAC data FIFO Table 3 8 Auxiliary Channel Assignments Chan Type 2 0...

Page 55: ...connects the reference for both DACs to ground when this bit is set This is useful for calibration of the DAC linearity This bit is not currently implemented as a separate selection for the two DACs...

Page 56: ...6032E and PCI 6031E It should be set to 0 0 BipDac Bipolar DAC This bit configures the voltage range of the selected DAC If this bit is set then the DAC is configured for bipolar operation of Vref to...

Page 57: ...full flag is available on the boards with the 0 word deep DAC data virtual FIFO Whenever the FIFO is not full the host is free to write additional data Address Base address 1E hex Type Write only Wor...

Page 58: ...15 through 0 The data to be written directly to DAC0 This data is interpreted in straight binary form when DAC0 is configured for unipolar operation In unipolar mode the valid range is 0 to 65 536 for...

Page 59: ...15 through 0 The data to be written directly to DAC1 This data is interpreted in straight binary form when DAC1 is configured for unipolar operation In unipolar mode the valid range is 0 to 65 536 for...

Page 60: ...the PCI E Series boards DMA interface The AI AO Select and G0 G1 Select Registers select the DMA channels for the analog input analog output and general purpose counter timer resources The PCI E Serie...

Page 61: ...iption 7 4 Reserved Reserved Always write 0 to these bits for PCI 6032E and PCI 6033E only 7 4 Output D A Analog Output Logical Channel D through A These four bits select the logical channels of the M...

Page 62: ...ss Base address 0B hex Type Write only Word Size 8 bit Bit Map Bit Name Description 7 4 GPCT1 D A General Purpose Counter Timer 1 Logical Channel C through A These four bits select the MITE logical ch...

Page 63: ...ion Memory Clear Register clears all information in the channel configuration memory and resets the write pointer to the first location in the memory Window Address 52 hex Type Write only Word Size 16...

Page 64: ...rogramming style becomes very modular and a functional description of every programming step is easily understood Because the DAQ STC Technical Reference Manual has detailed step by step programming i...

Page 65: ...d to operate properly this chip must be configured Ordinarily NI DAQ performs this function but if you are not using NI DAQ then you must configure the MITE ASIC chip The following sections explain ho...

Page 66: ...e The pseudo code shown below demonstrates how to re map the board below 1 MB If you do not want to re map the board you must still perform steps 4 and 5 to enable the device window of the MITE All va...

Page 67: ...re not using NI DAQ then you must configure the MITE ASIC chip The following sections explain how to accomplish this The initialization is done by the Setup_Mite function Setup_Mite consists of two pa...

Page 68: ...ndowed mode write the address offset to the Window_Address_Register read from the Window_Data_Read_Register Programming Examples The programs presented in this chapter are broken into three sections D...

Page 69: ...Board_Write Board_Write_8bit and Board_Read In addition Macintosh users should include the NI DAQ library since the NI DAQ library has the low level routines for reading the configuration Before begin...

Page 70: ...7 of the DAQ STC Technical Reference Manual 1 Set up the PCI board resources Use the function Setup_Mite provided on the Companion Disk 2 Configure all the digital lines as outputs DIO_Control_Registe...

Page 71: ...board registers and DAQ STC registers The following functions configure the board by calling the Board_Read and Board_Write functions Setup_Mite Configure_Board Analog input DAQ STC programming consis...

Page 72: ...ue to the input voltage The first two steps set up the E Series board and the subsequent steps configure the DAQ STC 1 Set up the PCI board resources Use the function Setup_Mite provided on the Compan...

Page 73: ...tart 1 Interrupt_A_Ack_Register 0x3F80 AI_Mode_1_Register Reserved one 1 AI start stop 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 6 AI_Board_Personalize sets the DAQ STC fo...

Page 74: ...1 AI_Mode_1_Register Trigger once 1 AI_Trigger_Select_Register Start edge 1 Start sync 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 10 The function AI_Scan_Start selects the...

Page 75: ...can interval of 1 ms The scan list contains channels 5 4 1 and 0 respectively The channels are configured as RSE at a gain of 1 Within each scan the sample interval should be 100 s Dithering should re...

Page 76: ...y ticks 1 19999 Joint_Reset_Register AI configuration start 0 AI configuration end 1 6 Perform Analog Input Example 1 Step 11 7 Convert_Signal selects the convert signal for the acquisition Joint_Rese...

Page 77: ...of 1 Within each scan the sample interval should be 100 s Dithering should remain off during the operation No external multiplexers are used Use interrupts to acquire the data Only minor modifications...

Page 78: ...he number of scans Joint_Reset_Register AI configuration start 1 AI_SC_Load_A_Registers 24 bits Number of posttrigger scans 1 4 AI_Command_1_Register AI SC Load 1 Joint_Reset_Register AI configuration...

Page 79: ...tial load source 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 8 Perform Analog Input Example 1 Step 4 9 The function AI_Interrupt_Enable enables interrupts for the acquisitio...

Page 80: ...example constructs a linked list to contain the information about the buffers such as their physical address logical address and total transfer bytes You need to pass the linked list head node to MITE...

Page 81: ...r AI configuration start 1 AI_Start_Stop_Select_Register Start edge 1 Start sync 1 AI_SI_Load_A_Registers 24 bits AI SI special ticks 1 1 AI_Command_1_Register AI SI load 1 AI_SI_Load_A_Registers 24 b...

Page 82: ...al address and logical address and total transfer bytes for that buffer 11 Set up the DRQ channel AI_AO_Select_Register DMA Channel A enable 1 12 Call the function MITE_DMAProgram to set up the MITE f...

Page 83: ...nstruct the output buffer information linked list Then perform all the steps above but pass OUTPUT for the direction parameter to the function MITE_DMAProgram To perform two or more DMA transfers at t...

Page 84: ...Analog Input Example 1 Step 1 2 Perform Analog Input Example 1 Step 2 for each channel in the scan list Only channel 0 has Last channel set to 1 3 Perform Analog Input Example 1 Steps 3 through 8 4 Ca...

Page 85: ...I_SI2_Load_B_Register AI SI2 ordinary ticks 1 1999 AI_Mode_2_Register AI SI2 reload mode 1 AI_Command_1_Register AI SI2 load 1 AI_Mode_2_Register AI SI2 initial load source 1 Joint_Reset_Register AI c...

Page 86: ...le 1 Step 1 2 Perform Analog Input Example 1 Step 2 for each channel in the scan list Only channel 0 has Last channel set to 1 3 Perform Analog Input Example 1 Steps 3 through 8 4 Call AI_Trigger_Sign...

Page 87: ...ers 24 bits AI SI ordinary ticks 1 19999 Joint_Reset_Register AI configuration start 0 AI configuration end 1 7 Perform Analog Input Example 1 Step 11 8 Convert_Signal selects the convert signal for t...

Page 88: ...as Example 2 but as a single wire acquisition Acquire 5 scans The scan list contains channels 5 4 1 and 0 respectively each at a gain of 1 and in RSE mode The START and CONVERT signals should be appli...

Page 89: ...enable 1 AI START STOP gate enable 1 AI_Mode_1_Register AI CONVERT source select 1 AI CONVERT source polarity 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 8 Perform Analog In...

Page 90: ...rough 6 4 Call the function AI_Initialize_Configuration_Memory_Output to output one pulse and access the first value in the configuration FIFO This function also configures the DIO circuitry for the A...

Page 91: ...Joint_Reset_Register AI configuration start 1 AI_SI2_Load_A_Register AI SI2 special ticks 1 1 AI_SI2_Load_B_Register AI SI2 ordinary ticks 1 1 AI_Mode_2_Register AI SI2 reload mode 1 AI_Command_1_Reg...

Page 92: ...7 Compare the unscaled results to the applied voltage Read the samples using polled input 1 Perform Analog Input Example 1 Step 1 2 Perform Analog Input Example 1 Step 2 for channels 0 and 1 Only cha...

Page 93: ...mber of scans Joint_Reset_Register AI configuration start 1 AI_SC_Load_A_Registers 24 bits Number of posttrigger scans 1 99 AI_Command_1_Register AI SC Load 1 Joint_Reset_Register AI configuration sta...

Page 94: ...0 AI configuration end 1 11 Perform Analog Input Example 1 Step 4 12 Call AI_Arming to arm the analog input counter AI_Command_1_Register AI SC arm 1 AI SI arm 1 AI SI2 arm 1 AI DIV arm 1 13 Now star...

Page 95: ...in complexity more of these functions will be necessary The functions will be presented in the applicable examples subsequent examples address only the specific differences from Example 1 This manual...

Page 96: ...98 Joint_Reset_Register AO configuration start 0 AO configuration end 1 4 Call AO_Board_Personalize to configure the DAQ STC Joint_Reset_Register AO_Configuration_Start 1 If Board Type PCI MIO 16E 1 P...

Page 97: ...ialize the buffer with 3000 points Use polled writes to write each point to the data FIFO Updates occur every 2 ms Output the buffer five times Confirm operation with an oscilloscope 1 Perform Analog...

Page 98: ...onfiguration end 1 8 Call AO_Board_Personalize to configure the DAQ STC for the MIO board Use the following bitfield settings Joint_Reset_Register AO_Configuration_Start 1 If Board Type PCI MIO 16E 1...

Page 99: ...he first buffer contains 3000 points Write 2999 to UC Load Register A each subsequent buffer contains 3000 points Joint_Reset_Register AO configuration start 1 AO_Mode_1_Register AO continuous 0 AO_Mo...

Page 100: ...I source select 0 AO UI source polarity 0 AO_Mode_2_Register AO UI initial load source 0 AO UI reload mode 0 AO_UI_Load_A_Registers 24 bits AO UI special ticks 1 1 AO_Command_1_Register AO UI load 1 A...

Page 101: ...analog output to stop on overrun error Joint_Reset_Register AO configuration start 1 AO_Mode_3_Register 0x0020 Joint_Reset_Register AO configuration start 0 AO configuration end 1 15 Call AO_FIFO to...

Page 102: ...6XE 50 boards because it has virtual analog output FIFOs Initialize the data FIFO with a 100 point buffer Output the buffer 50 times The update interval is 100 s Confirm operation with an oscilloscope...

Page 103: ...ce to AO_IN_TIMEBASE1 Load the UI counter with 1 minimum delay from the START1 to the first UPDATE Write 1999 to UI Load Register A 100 s update interval Joint_Reset_Register AO configuration start 1...

Page 104: ...ll AO_Start_The_Acquisition to pulse the software START1 trigger AO_Command_2_Register AO START1 pulse 1 Example 4 This example generates a waveform using local buffer mode with an external UPDATE and...

Page 105: ...oad the BC counter with 49 output the buffer 50 times Load the UC counter with 100 the first buffer contains 100 points Write 99 to UC Load Register A each subsequent buffer contains 100 points Joint_...

Page 106: ...us register indicates an interrupt the main loop transfers control to the ISR To use the example ISR as an actual interrupt you need to learn how to install software interrupts on your system Generall...

Page 107: ...r 0x554 5 Program the DAQ STC to generate interrupts on the FIFO condition Interrupt_B_Enable_Register AO FIFO interrupt enable 1 Interrupt_Control_Register Interrupt B output select IRQ number Interr...

Page 108: ...ual contains all the information on the DAQ STC general purpose counter and timer module with specific programming steps in the Programming Information section Example 1 shows simple gated event count...

Page 109: ...er G0_Load_Source 0 G0_Load_A_Registers 24 bits G0_Load_A 0x0000 initial counter value G0_Command_Register G0_Load 1 G0_Input_Select_Register G0_Source_Select 4 PFI3 G0_Source_Polarity 0 rising edges...

Page 110: ...le 2 This is the example for buffered pulsewidth measurement The counter uses G_In_TimeBase as G_Source to measure the signal s pulsewidth on PFI4 G_Gate counting the number of edges that occur on G_S...

Page 111: ..._Mode 1 one clock cycle output G0_Gate_Polarity 1 enable inversion G0_Loading_On_Gate 1 G0_Loading_On_TC 0 GO_Gating_Mode 1 G0_Gate_On_Both_Edges 0 GO_Trigger_Mode_For_Edge_Gate 3 G0_Stop_Mode 0 G0_Co...

Page 112: ...dware saves are too fast if G0_Gate_Error_St 1 Interrupt_A_Ack_Register G0_Gate_Error_Confirm 1 if G0_TC_St 1 rollover error counter value is not correct confirm user rollover has occurred Interrupt_A...

Page 113: ...Board_Divide_By_2 1 3 Call Cont_Pulse_Train_Generation to set up the DAQ STC for continuous pulse train generation Go_Mode_Register G0_Load_Source 0 G0_Load_A_Registers 24 bits G0_Load_A 0x0002 delay...

Page 114: ...lse_Train_Change G0_Bank_Switch_Mode 0 Interrupt_A_Enable_Register G0_TC_Interrupt_Enable 0 G0_Gate_Interrupt_Enable 0 4 Call G0_Out_Enable to enable GPCTR0_Out pin Analog_Trigger_Etc_Register GPFO_0_...

Page 115: ...e four RTSI board signals with any of the seven RTSI trigger signals and the AISTART or AISTOP signal See the DAQ STC manual for information on programming the RTSI interface The function MSC_RTSI_Pin...

Page 116: ...g bit in the Misc Command Register controls which input is used The PGIA output is selected when this bit is set and the PFI0 TRIG1 input is selected when this bit is cleared When the PFI0 TRIG1 input...

Page 117: ...rogramming Analog Trigger section of Chapter 10 in the DAQ STC Technical Reference Manual The following example is written for the PCI MIO 16E 1 PCI MIO 16E 4 and PCI 6071 boards which use 8 bit CALDA...

Page 118: ...robe 1 1 Configuration_Memory_High_Register Channel Number 0 Channel type 3 Configuration_Memory_Low_Register Last Channel 1 Gain 1 Polarity 0 Dither enable 0 3 Perform Steps 3 through 9 of Analog Inp...

Page 119: ...log input interrupts general purpose Counter 0 interrupts and one pass through interrupt The Group A pass through interrupt is not used Group B handles the analog output interrupts general purpose cou...

Page 120: ...our PCI E Series board so that the analog input analog output or general purpose counter timers can generate DMA requests under appropriate circumstances There are four logical DMA channels A B C and...

Page 121: ...full Assert on FIFO half full and deassert on FIFO full For general purpose counter timers an interrupt is produced in buffered modes such as the buffered event counting the buffered period measuremen...

Page 122: ...an entry point to access the link chain After arming the DMA transfer the MITE goes through the link chain and loads the buffer s physical address into MAR Then the MITE transfers data from the FIFO t...

Page 123: ...enerating new constants results in a more accurate calibration for the actual environment in which the board is used About the EEPROM The EEPROM is used to store all non volatile information about the...

Page 124: ...to the CalDACs could result in accidental writes to the EEPROM However this is not true A write cycle to the EEPROM needs the chip select bit asserted While writing to the CalDACs make sure that this...

Page 125: ...ast factory fabrication 426 Factory reference MSB 425 Factory reference LSB 424 CALDAC factory constant AI MB88341 8 bit 4 0 423 CALDAC factory constant AI MB88341 8 bit 1 0 422 CALDAC factory constan...

Page 126: ...ory constant Unipolar AO MB88341 8 bit 8 0 410 CALDAC factory constant Unipolar AO MB88341 8 bit 10 0 409 CALDAC factory constant Unipolar AO MB88341 8 bit 9 0 408 Factory calibration temperature 371...

Page 127: ...ation 438 Factory reference MSB 437 Factory reference LSB 436 CALDAC factory constant MSB Bipolar AI DAC8043 12 bit 1 435 CALDAC factory constant LSB Bipolar AI DAC8043 12 bit 1 434 CALDAC factory con...

Page 128: ...t 6 0 425 CALDAC factory constant AO 8800 8 bit 4 0 424 CALDAC factory constant AO 8800 8 bit 7 0 423 CALDAC factory constant AO 8800 8 bit 5 0 422 Factory calibration temperature 371 Start of the fiv...

Page 129: ...t factory fabrication 431 Factory reference MSB 430 Factory reference LSB 429 CALDAC factory constant MSB Bipolar AI DAC8043 12 bit 1 428 CALDAC factory constant LSB Bipolar AI DAC8043 12 bit 1 427 CA...

Page 130: ...CALDAC factory constant Bipolar AO 8800 8 bit 5 0 413 CALDAC factory constant Unipolar AO 8800 8 bit 6 0 412 CALDAC factory constant Unipolar AO 8800 8 bit 4 0 411 CALDAC factory constant Unipolar AO...

Page 131: ...508 Year of last factory fabrication 507 Month of last factory fabrication 506 Day of last factory fabrication 444 Factory reference MSB 443 Factory reference LSB 442 CALDAC factory constant AI MB883...

Page 132: ...tory fabrication 506 Day of last factory fabrication 432 Factory reference MSB 431 Factory reference LSB 430 CALDAC factory constant Bipolar AI MB88341 8 bit 4 0 429 CALDAC factory constant Bipolar AI...

Page 133: ...8 bit 9 0 420 Factory calibration temperature 371 Start of the five user calibration sections 1Board Codes LSB MSB 256 LSB Board Code 13 PCI 6024E 1 256 13 269 15 PCI 6025E 1 256 15 271 2 Board Codes...

Page 134: ...of last factory calibration 416 Factory reference MSB 415 Factory reference LSB 414 CALDAC factory constant AI pregain offset coarse MB88341 0 0 413 CALDAC factory constant AI pregain offset fine MB88...

Page 135: ...1 2 1 401 CALDAC factory constant AO1bipolar gain coarse MB88341 10 1 400 CALDAC factory constant AO1bipolar gain fine MB88341 6 1 399 CALDAC factory constant AO1bipolar offset MB88341 14 1 398 CALDAC...

Page 136: ...oarse MB88341 10 1 392 CALDAC factory constant AO 1 unipolar gain fine MB88341 6 1 391 CALDAC factory constant AO 1 unipolar offset MB88341 14 1 390 Factory calibration temp 1 371 Start of the four us...

Page 137: ...ial DACs is similar to the EEPROM The basic write cycle consists of shifting an address data pair into the DAC then pulsing the appropriate SerDacLd pin The timing diagram for the write cycle for each...

Page 138: ...ard for use with Figure 5 2 SerClk a MB 88341 SerDacLd SerData A0 A1 A2 A3 D7 D6 D5 D4 D3 D2 D1 D0 SerClk b DAC 8800 SerDacLd SerData A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SerClk c DAC 8043 SerDacLd SerDat...

Page 139: ...ue to the complexity of the actual calibration algorithm use Calibrate_E_Series to calibrate each section and store the results in the EEPROM You can write a separate application using Calibrate_E_Ser...

Page 140: ...not answer your questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services Bulletin Board Support National Inst...

Page 141: ...fice in your country contact the source from which you purchased your software to obtain support Country Telephone Fax Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0662 45 79 90 19 Belg...

Page 142: ...___ Instruments used _________________________________________________________________ _______________________________________________________________________________ National Instruments hardware pro...

Page 143: ...__________ Base memory address of other National Instruments boards _______________________________ Interrupt level of other National Instruments boards _____________________________________ Other Pro...

Page 144: ...____________________ _______________________________________________________________________________ _______________________________________________________________________________ ___________________...

Page 145: ...0 9 micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 109 Symbols inverted bit negative logic if after a bit name ohms A A amperes A D analog to digital AC alternating current ADC A D converter AIG...

Page 146: ...t bit ChanEnable DMA channel enable bit Channel physical channel select bit ChanType channel type bit CONVERT convert signal D D data bit D A digital to analog DAC D A converter DAC0OUT analog channel...

Page 147: ...count C bit DmaTcCClr DMA terminal count C clear bit E EEPROM electrically erasable programmable read only memory EEPromCS EEPROM chip select bit EXTREF external reference signal ExtRef external refe...

Page 148: ...adecimal Hz hertz I I O input output Input analog input bit Int Ext Trig internal external analog trigger IRQ interrupt request signal ISA Industry Standard Architecture ISR interrupt service routine...

Page 149: ...fiers OS operating system Output analog output bit P PFI0 Trig1 PFI 0 Trigger 1 signal PFI1 Trig2 PFI 1 Trigger 2 signal PGIA Programmable Gain Instrumentation Amplifier ppm parts per million PRETRIG...

Page 150: ...serial DAC load bit SerData serial data bit SHIFTIN shift in signal SI scan interval counter SI2 sample interval START start signal STOP stop signal T TC terminal count TCIntEnable DMATC interrupt ena...

Page 151: ...Glossary National Instruments Corporation G 7 PCI E Series RLPM UI2 update interval 2 Unip Bip channel unipolar bipolar bit V V volts Vref input voltage reference X X don t care bits...

Page 152: ...le from channel 0 4 10 AMUX 64T examples sampling one channel 4 27 scanning eight channels 4 29 AI_Interrupt_Enable function 4 16 AI_Reset_All function 4 10 AI_Scan_Start function AMUX 64T examples sa...

Page 153: ...ing local buffer mode 4 41 to 4 43 Analog Output Register Group AO Configuration Register 3 16 to 3 17 DAC FIFO Data Register 3 18 DAC0 Direct Data Register 3 19 DAC1 Direct Data Register 3 20 overvie...

Page 154: ...bits AI_FIFO_Empty_St 2 12 Analog_Trigger_Drive 4 53 Bank 1 0 3 12 BipDac 3 17 Chan 3 0 3 12 to 3 15 ChanType 2 0 3 11 D 15 0 3 8 3 18 3 19 3 20 DACSel 3 16 DitherEn 3 9 to 3 10 DOTRIG0 4 52 EEPromCS...

Page 155: ...onreferenced single ended channel assignments table 3 13 to 3 14 referenced single ended channel assignments table 3 14 valid channel types table 3 11 ChanType 2 0 bit 3 11 Clear_FIFO function 4 10 4...

Page 156: ...acquisition sequence timing 2 12 to 2 18 multirate scanning with ghost 2 16 to 2 18 advantages figure 2 17 analog input configuration memory table 2 18 occurrences of conversion on channel 1 figure 2...

Page 157: ...ory 2 8 overflow 2 11 theory of operation 2 10 to 2 11 waveform generation 2 23 to 2 24 FIFO Strobe Register Group ADC FIFO Clear Register 3 24 Configuration Memory Clear Register 3 24 DAC FIFO Clear...

Page 158: ...atus Register 3 6 MITE ASIC initializing PCI 4 2 Link Chaining Mode for DMA transfer 4 58 to 4 59 programming for different DMA transfers 4 20 to 4 21 re mapping PCI E Series board 4 3 MITE_DMAarm fun...

Page 159: ...local bus programming considerations 4 1 to 4 4 PCI initialization for IBM compatible systems 4 2 for Macintosh computers 4 4 re mapping PCI E Series board 4 3 to 4 4 PFIO TRIG1 signal 4 53 PGIA prog...

Page 160: ...n generation 4 49 to 4 52 gated event counting 4 45 to 4 47 PROMOUT bit 3 6 5 1 pulse train generation example 4 49 to 4 52 pulsewidth measurement example 4 47 to 4 49 Pulse_Width_Measurement_ISR func...

Page 161: ...p_Mite function analog input examples acquiring one sample from channel 0 4 9 digital I O examples 4 7 general purpose counter timer examples gated event counting 4 45 initializing PCI IBM compatible...

Page 162: ...data acquisition 2 11 to 2 18 ADC timing figure 2 12 block diagram 2 8 data acquisition sequence timing 2 12 to 2 18 multirate scanning with ghost 2 16 to 2 18 multirate scanning without ghost 2 14 to...

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National Instruments E Series, Programmer'S Manual

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