Chapter 3
Hardware Overview
©
National Instruments Corporation
3-3
DAQCard-DIO-24 User Manual
high signal on the PC3 line generates an interrupt request. When
interrupts are enabled for group B, an active high signal on the PC0 line
generates an interrupt request.
In addition to selecting interrupt levels, the system examines
information stored in the DAQCard-DIO-24 card information structure.
The software uses this data to configure the card appropriately for the
system in which it is used. When the system has assigned the card to a
section of memory, it updates the PC Card control registers and
initializes the card.
The rest of the circuitry consists of address decoders, data buffers, I/O
channel interface timing control circuitry, and interrupt control
circuitry. The decode circuitry uses the PCMCIA bus signal CE1*,
which the PCMCIA Card and Socket Services software controls, as the
board-enable signal and uses lines A0 through A4 plus timing signals to
generate the onboard register-select signals and read/write signals. The
data buffers control the direction of data transfer on the bidirectional
data lines based on whether the transfer is a read or write. The
DAQCard-DIO-24 uses only 8-bit transfers. The interrupt control
circuitry routes any enabled interrupts to the IREQ* line, which the
system motherboard routes to an available interrupt request line.
Digital I/O Connector
All digital I/O is transmitted through a 25-pin PC Card I/O connector.
The optional PSH27-50F-D1 cable can connect the DAQCard-DIO-24
to a standard 50-pin male connector. The pin assignments for the 50-pin
I/O connector are compatible with standard 24-channel digital I/O
applications. All even-numbered pins on this 50-pin connector are
attached to the card’s ground. Pin 49 is connected to +5 V, which is
often required to operate I/O module mounting racks. See Chapter 4,
Signal Connections, for additional information on pin assignments.
