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Chapter 4

Signal Connections

PCI-6110E/6111E User Manual

4-24

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National Instruments Corporation

Refer to Figures 4-8 and 4-9 for the relationship of STARTSCAN to the
DAQ sequence.

As an input, the CONVERT* signal is configured in the edge-detection
mode. You can select any PFI pin as the source for CONVERT* and
configure the polarity selection for either rising or falling edge. The
selected edge of the CONVERT* signal initiates an A/D conversion.

As an output, the CONVERT* signal reflects the actual convert pulse
that is connected to the ADC. This is true even if the conversions are
being externally generated by another PFI. The output is an active low
pulse with a pulse width of 50 to 100 ns. This output is set to tri-state at
startup.

Figures 4-18 and 4-19 show the input and output timing requirements
for the CONVERT* signal.

Figure 4-18.

CONVERT* Input Signal Timing

Figure 4-19.

CONVERT* Output Signal Timing

The ADC switches to hold mode within 20 ns of the selected edge. This
hold-mode delay time is a function of temperature and does not vary
from one conversion to the next.

Rising-edge

polarity

Falling-edge

polarity

t

w

t

w

= 10 ns minimum

t

w

t

w

= 50-100 ns

PCI_E.book Page 24 Thursday, June 25, 1998 12:55 PM

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Summary of Contents for DAQ PCI-6110E

Page 1: ...User Manual Multifunction I O Boards for PCI Bus Computers April 1998 Edition Part Number 321759B 01 Copyright 1998 National Instruments Corporation All rights reserved PCI_E book Page 1 Thursday June 25 1998 12 55 PM ...

Page 2: ...il 011 288 3336 Canada Ontario 905 785 0085 Canada Québec 514 694 8521 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 5 520 2635 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 200 51 51 Taiwan 02...

Page 3: ...S EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reas...

Page 4: ...ted 1 2 Software Programming Choices 1 2 National Instruments Application Software 1 2 NI DAQ Driver Software 1 3 Register Level Programming 1 4 Optional Equipment 1 5 Custom Cabling 1 5 Unpacking 1 6 Chapter 2 Installation and Configuration Software Installation 2 1 Hardware Installation 2 1 Board Configuration 2 2 Chapter 3 Hardware Overview Analog Input 3 2 Input Mode 3 2 Input Polarity and Inp...

Page 5: ...nsiderations 4 10 Differential Connections for Ground Referenced Signal Sources 4 11 Differential Connections for Nonreferenced or Floating Signal Sources 4 11 Common Mode Signal Rejection Considerations 4 12 Analog Output Signal Connections 4 13 Digital I O Signal Connections 4 13 Power Connections 4 15 Timing Connections 4 15 Programmable Function Input Connections 4 16 DAQ Timing Connections 4 ...

Page 6: ...URCE Signal 4 32 GPCTR1_GATE Signal 4 32 GPCTR1_OUT Signal 4 33 GPCTR1_UP_DOWN Signal 4 34 FREQ_OUT Signal 4 35 Field Wiring Considerations 4 35 Chapter 5 Calibration Loading Calibration Constants 5 1 Self Calibration 5 2 External Calibration 5 2 Appendix A Specifications Appendix B Cable Connector Descriptions Appendix C Common Questions Appendix D Customer Communication Glossary Index PCI_E book...

Page 7: ...ctions for Ground Referenced Signals 4 11 Figure 4 4 Differential Input Connections for Nonreferenced Signals 4 12 Figure 4 5 Analog Output Connections 4 13 Figure 4 6 Digital I O Connections 4 14 Figure 4 7 Timing I O Connections 4 16 Figure 4 8 Typical Posttriggered Acquisition 4 17 Figure 4 9 Typical Pretriggered Acquisition 4 18 Figure 4 10 SCANCLK Signal Timing 4 18 Figure 4 11 EXTSTROBE Sign...

Page 8: ...0 GPCTR1_GATE Signal Timing in Edge Detection Mode 4 33 Figure 4 31 GPCTR1_OUT Signal Timing 4 33 Figure 4 32 GPCTR Timing Summary 4 34 Figure B 1 68 Pin 611X E Series Connector Pin Assignments B 2 Tables Table 3 1 Actual Range and Measurement Precision 3 3 Table 4 1 Signal Descriptions for I O Connector Pins 4 3 Table 4 2 I O Signal Summary for the 611X E 4 6 Table 4 3 Signal Source Types 4 10 PC...

Page 9: ...duction describes your 611X E board lists what you need to get started describes the optional software and optional equipment and explains how to unpack your 611X E board Chapter 2 Installation and Configuration explains how to install and configure your 611X E board Chapter 3 Hardware Overview presents an overview of the hardware functions on your 611X E board Chapter 4 Signal Connections describ...

Page 10: ...ion Angle brackets containing numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example DIO 3 0 611X E This refers to either the PCI 6110E or PCI 6111E board This icon to the left of bold italicized text denotes a note which alerts you to important information This icon to the left of bold italicized text denotes a caution which advises you of pr...

Page 11: ...ny of several types of documentation depending on the hardware and software in your system Use the documentation you have as follows Getting Started with SCXI If you are using SCXI this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software Your SCXI hardware user manuals If you are using SC...

Page 12: ...d these manuals for maintenance information on the chassis and installation instructions Related Documentation The following documents contain information you may find helpful DAQ STC Technical Reference Manual National Instruments Application Note 025 Field Wiring and Noise Considerations for Analog Signals PCI Local Bus Specification Revision 2 0 Customer Communication National Instruments wants...

Page 13: ...ta acquisition DAQ board for the PCI bus This feature is made possible by the National Instruments MITE bus interface chip that connects the board to the PCI I O bus The MITE implements the PCI Local Bus Specification so that the interrupts and base memory addresses are all software configured The 611X E board uses the National Instruments DAQ STC system timing controller for time related function...

Page 14: ...h Your computer Software Programming Choices You have several options to choose from when programming your National Instruments DAQ and SCXI hardware You can use National Instruments application software NI DAQ or register level programming National Instruments Application Software ComponentWorks contains tools for data acquisition and instrument control built on NI DAQ driver software ComponentWo...

Page 15: ...g ComponentWorks LabVIEW LabWindows CVI or VirtualBench software will greatly reduce the development time for your data acquisition and control application NI DAQ Driver Software The NI DAQ driver software is included at no charge with all National Instruments DAQ hardware NI DAQ is not packaged with SCXI or accessory products except for the SCXI 1200 NI DAQ has an extensive library of functions t...

Page 16: ...lationship between the Programming Environment NI DAQ and Your Hardware Register Level Programming The final option for programming any National Instruments DAQ hardware is to write register level software Writing register level programming software can be very time consuming and inefficient and is not recommended for most users Even if you are an experienced register level programmer using NI DAQ...

Page 17: ...truments offers cables and accessories for you to prototype your application or to use if you frequently change board interconnections If you want to develop your own cable however the following guidelines may be useful For the analog input signals shielded twisted pair wires for each analog input pair yield the best results assuming that you use differential inputs Tie the shield for each signal ...

Page 18: ...tatic discharge can damage several components on the board To avoid such damage in handling the board take the following precautions Ground yourself via a grounding strap or by holding a grounded object Touch the antistatic package to a metal part of your computer chassis before removing the board from the package Remove the board from the package and inspect the board for loose components or any ...

Page 19: ...are using NI DAQ refer to your NI DAQ release notes Find the installation section for your operating system and follow the instructions given there Hardware Installation You can install the 611X E board in any available expansion slot in your computer However to achieve best noise performance leave as much room as possible between the 611X E board and other boards and hardware The following are ge...

Page 20: ...for data acquisition and the PCI bus specification the 611X E board is completely software configurable You must perform two types of configuration on the 611X E board bus related and data acquisition related configuration The 611X E board is fully compatible with the industry standard PCI Local Bus Specification Revision 2 0 This allows the PCI system to automatically perform all bus related conf...

Page 21: ...Bit ADC DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA IRQ Bus Interface DAC FIFO Data 32 Address Data Control Data 32 Analog Input Control EEPROM Control DMA Interface FPGA DAQ STC Bus Interface Analog Output Control I O Bus Interface Mini MITE Generic Bus Interface PCI Bus Interface IRQ DMA AO Control CH0 CH0 CH1 Amp...

Page 22: ...itive input of the board programmable gain instrumentation amplifier PGIA and the other connects to the negative input of the PGIA For more information about DIFF input Timing PFI Trigger I O Connector RTSI Bus PCI Bus Digital I O 8 EEPROM CH0 Amplifier Calibration Mux AI CH0 Mux CH0 Latch Analog Trigger Circuitry 2 Trigger Level DACs Trigger 12 4 Calibration DACs DAC0 DAC1 CH0 12 Bit ADC DAQ STC ...

Page 23: ... measure the input signal Table 3 1 shows the overall input range and precision according to the gain used Table 3 1 Actual Range and Measurement Precision Range Configuration Gain Actual Input Range1 Precision2 10 to 10 V 0 2 0 5 1 0 2 0 5 0 10 0 20 0 50 0 50 to 50 V 20 to 20 V 10 to 10 V 5 to 5 V 2 to 2 V 1 to 1V 500 to 500 mV 200 to 200 mV 24 41 mV 9 77 mV 4 88 mV 2 44 mV 976 56 µV 488 28 µV 24...

Page 24: ...r applications involving averaging to increase the resolution of the 611X E board as in calibration or spectral analysis In such applications noise modulation is decreased and differential linearity is improved by the addition of the dither When taking DC measurements such as when checking the board calibration you should average about 1 000 points to take a single reading This process removes the...

Page 25: ...r The range is fixed at bipolar 10 V a Dither disabled no averaging b Dither disabled average of 50 acquisitions c Dither enabled no averaging d Dither enabled average of 50 acquisitions LSBs 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 LSBs 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 LSBs 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 LSBs 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6...

Page 26: ...e 611X E board The range for the post PGIA trigger selection is simply the full scale range of the selected channel and the resolution is that range divided by 256 Note The PFI0 TRIG1 pin is an analog input when configured as an analog trigger Therefore it is susceptible to crosstalk from adjacent pins which can result in false triggering when the pin is left unconnected To avoid false triggering ...

Page 27: ...0 You can set lowValue and highValue independently in software In below low level analog triggering mode the trigger is generated when the signal value is less than lowValue as shown in Figure 3 6 HighValue is unused Figure 3 6 Below Low Level Analog Triggering Mode PGIA Analog Input CH0 ADC DAQ STC Analog Trigger Circuit Mux PGIA Analog Input CH1 ADC PFI0 TRIG1 lowValue Trigger PCI_E book Page 7 ...

Page 28: ...n highValue as shown in Figure 3 7 LowValue is unused Figure 3 7 Above High Level Analog Triggering Mode In inside region analog triggering mode the trigger is generated when the signal value is between the lowValue and the highValue as shown in Figure 3 8 Figure 3 8 Inside Region Analog Triggering Mode highValue Trigger highValue Trigger lowValue PCI_E book Page 8 Thursday June 25 1998 12 55 PM ...

Page 29: ...ow Hysteresis Analog Triggering Mode The analog trigger circuit generates an internal digital trigger based on the analog input signal and the user defined trigger levels This digital trigger can be used by any of the timing sections of the DAQ STC including the analog input analog output and general purpose counter timer sections For example the analog input section can be configured to acquire n...

Page 30: ...e for either input or output At system startup and reset the digital I O ports are all high impedance The hardware up down control for general purpose counters 0 and 1 are connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals are input only and do not affect the operation of the DIO lines PCI_E book Page 1...

Page 31: ...e connections are designed to enable the 611X E board to both control and be controlled by other boards and circuits There are a total of 13 timing signals internal to the DAQ STC that can be controlled by an external source These timing signals can also be controlled by signals generated internally to the DAQ STC and these selections are fully software configurable For example the signal routing ...

Page 32: ...e I O connector for different applications You can also individually enable each of the PFI pins to output a specific internal timing signal For example if you need the UPDATE signal as an output on the I O connector software can turn on the output driver for the PFI5 UPDATE pin Board and RTSI Clocks Many functions performed by the 611X E board require a frequency timebase to generate the necessar...

Page 33: ...s and can receive any of these timing signals This signal connection scheme is shown in Figure 3 12 Figure 3 12 RTSI Bus Signal Connection Refer to the Timing Connections section of Chapter 4 Signal Connections for a description of the signals shown in Figure 3 12 RTSI Bus Connector switch RTSI Switch Clock Trigger 7 DAQ STC TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT ST...

Page 34: ...ed cable I O Connector Figure 4 1 shows the pin assignments for the 68 pin I O connector on the 611X E board A signal description follows the connector pinouts Caution Connections that exceed any of the maximum ratings of input or output signals on the 611X E board can damage the 611X E board and the computer Maximum input ratings for each signal are given in the Protection column of Table 4 2 Nat...

Page 35: ...GND1 ACH3 1 ACH2 1 ACH1GND ACH1 ACH0 DGND 1 NC on PCI 6111E PFI8 GPCTR0_SOURCE PFI7 STARTSCAN GPCTR1_OUT PFI4 GPCTR1_GATE PFI3 GPCTR1_SOURCE PFI2 CONVERT DGND DGND DGND EXTSTROBE SCANCLK DIO3 DIO7 DIO2 DGND DIO5 DIO0 DGND AOGND AOGND NC NC NC NC NC NC NC ACH3 1 ACH2GND1 ACH2 1 ACH1 ACH0GND ACH0 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53...

Page 36: ...t This pin supplies the voltage output of analog output channel 0 DAC1OUT AOGND Output Analog Channel 1 Output This pin supplies the voltage output of analog output channel 1 AOGND Analog Output Ground The analog output voltages are referenced to this node DGND Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply DIO 0 7 DGND Input...

Page 37: ... not used in posttrigger applications PFI2 CONVERT DGND Input Output PFI2 Convert As an input this is one of the PFIs As an output this is the CONVERT signal A high to low edge on CONVERT indicates that an A D conversion is occurring PFI3 GPCTR1_SOURCE DGND Input Output PFI3 Counter 1 Source As an input this is one of the PFIs As an output this is the GPCTR1_SOURCE signal This signal reflects the ...

Page 38: ...e scan PFI8 GPCTR0_SOURCE DGND Input Output PFI8 Counter 0 Source As an input this is one of the PFIs As an output this is the GPCTR0_SOURCE signal This signal reflects the actual source connected to the general purpose counter 0 PFI9 GPCTR0_GATE DGND Input Output PFI9 Counter 0 Gate As an input this is one of the PFIs As an output this is the GPCTR0_GATE signal This signal reflects the actual gat...

Page 39: ...50 Ω Short circuit to ground 5 at 10 5 at 10 300 V µs DAC1OUT AO 50 Ω Short circuit to ground 5 at 10 5 at 10 300 V µs AOGND AO DGND DO VCC DO 0 1 Ω Short circuit to ground 1 A DIO 0 7 DIO Vcc 0 5 13 at Vcc 0 4 24 at 0 4 1 1 50 kΩ pu SCANCLK DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu EXTSTROBE DO 3 5 at V cc 0 4 5 at 0 4 1 5 50 kΩ pu PFI0 TRIG1 AI DIO 10 kΩ 35 V cc 0 5 3 5 at V cc 0 4 5 at 0 4 1 5 9 ...

Page 40: ...t V cc 0 4 5 at 0 4 1 5 50 kΩ pu GPCTR0_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu FREQ_OUT DO 3 5 at V cc 0 4 5 at 0 4 1 5 50 kΩ pu 1 Applies to gain 1 impedance refers to ACH 0 3 2 Applies to gain 1 impedance refers to ACH 0 3 AI Analog Input DIO Digital Input Output pu pull up AO Analog Output DO Digital Output AI DIO Analog Input Digital Input Output The tolerance on the 50 kΩ pull up and pul...

Page 41: ...ted in the Protection column of Table 4 2 With the different configurations you can use the PGIA in different ways Figure 4 2 shows a diagram of your 611X E board PGIA Figure 4 2 611X E Board PGIA The PGIA applies gain and common mode voltage rejection and presents high input impedance to the analog input signals connected to the 611X E board Signals are routed to the positive and negative inputs ...

Page 42: ... common mode input range Ground Referenced Signal Sources A ground referenced signal source is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the 611X E board assuming that the computer is plugged into the same power system Nonisolated outputs of instruments and devices that plug into the building power system fall in...

Page 43: ...egative input of the PGIA Each differential signal uses two inputs one for the signal and one for its reference signal Differential signal connections reduce picked up noise and increase common mode noise rejection Differential signal connections also allow input signals to float within the common mode limits of the PGIA Table 4 3 Signal Source Types DIFF Input Examples and Signal Source Floating ...

Page 44: ...GIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the 611X E board ground shown as Vcm in Figure 4 3 Differential Connections for Nonreferenced or Floating Signal Sources Figure 4 4 shows how to connect a floating signal source to a channel on the 611X E board Ground Referenced Signal Source Common Mode Noise and Ground Potential...

Page 45: ... that are already referenced to some ground point with respect to the 611X E board In this case the PGIA can reject any voltage caused by ground potential differences between the signal source and the board In addition with differential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the board The PGIA can reject common mode signals as l...

Page 46: ... signal for the analog output channels Figure 4 5 shows how to make analog output connections to the 611X E board Figure 4 5 Analog Output Connections Digital I O Signal Connections The digital I O signals are DIO 0 7 and DGND DIO 0 7 are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually to be inputs or outputs Channe...

Page 47: ...hree typical digital I O applications Figure 4 6 Digital I O Connections Figure 4 6 shows DIO 0 3 configured for digital input and DIO 4 7 configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the switch state shown in Figure 4 6 Digital output applications include sending TTL signals and driving external devices such as t...

Page 48: ...e computer National Instruments is NOT liable for any damages resulting from such signal connections All external control over the timing of the 611X E board is routed through the 10 programmable function inputs labeled PFI0 through PFI9 These signals are explained in detail in the next section Programmable Function Input Connections These PFIs are bidirectional as outputs they are not programmabl...

Page 49: ...rnally control from the PFI pins The source for each of these signals is software selectable from any of the PFIs when you want external control This flexible routing scheme reduces the need to change the physical wiring to the board I O connector for different applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For...

Page 50: ...dge detect mode In level detection mode there are no minimum or maximum pulse width requirements imposed by the PFIs themselves but there may be limits imposed by the particular timing signal being controlled These requirements are listed later in this chapter DAQ Timing Connections The DAQ timing signals are SCANCLK EXTSTROBE TRIG1 TRIG2 STARTSCAN CONVERT AIGATE and SISOURCE Posttriggered data ac...

Page 51: ... This signal has a 450 ns pulse width and is software enabled Figure 4 10 shows the timing for the SCANCLK signal Figure 4 10 SCANCLK Signal Timing EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse or a sequence of eight pulses in the hardware strobe mode An external device can use this signal to latch signals or to trigger events In the single pulse mode sof...

Page 52: ...ource for TRIG1 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG1 signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions The 611X E supports analog triggering on the PFI0 TRIG1 pin See Chapter 3 Hardware Overview for more information on analog triggering As an output the TRIG1 signal reflects the action t...

Page 53: ...peration TRIG2 Signal Any PFI pin can externally input the TRIG2 signal which is available as an output on the PFI1 TRIG2 pin Refer to Figure 4 9 for the relationship of TRIG2 to the DAQ sequence As an input the TRIG2 signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge The selected...

Page 54: ...e acquires data both before and after receiving TRIG2 As an output the TRIG2 signal reflects the posttrigger in a pretriggered acquisition sequence This is true even if the acquisition is being externally triggered by another PFI The TRIG2 signal is not used in posttriggered data acquisition The output is an active high pulse with a pulse width of 25 to 50 ns This output is set to tri state at sta...

Page 55: ...gered CONVERT As an output the STARTSCAN signal reflects the actual start pulse that initiates a scan This is true even if the starts are being externally triggered by another PFI You have two output options The first is an active high pulse with a pulse width of 25 to 50 ns which indicates the start of the scan The second action is an active high pulse that terminates at the start of the last con...

Page 56: ...oard internally generates the STARTSCAN signal unless you select some external source This counter is started by the TRIG1 signal and is stopped either by software or by the sample counter Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence may be gated by either the hardware AIGATE signal or...

Page 57: ... pulse that is connected to the ADC This is true even if the conversions are being externally generated by another PFI The output is an active low pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 18 and 4 19 show the input and output timing requirements for the CONVERT signal Figure 4 18 CONVERT Input Signal Timing Figure 4 19 CONVERT Output Signal Timi...

Page 58: ...tion mode You can configure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal is masked off and no scans can occur In the edge detection mode the first active edge disables the STARTSCAN signal and the second active edge enables STARTSCAN The AIGATE signal can neither stop a scan in progress nor continue...

Page 59: ...he WFTRIG signal which is available as an output on the PFI6 WFTRIG pin As an input the WFTRIG signal is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge The selected edge of the WFTRIG signal starts the waveform generation for the DACs The update interval UI counter is started if you se...

Page 60: ...elect any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode As an output the UPDATE signal reflects the actual update pulse that is connected to the DACs This is true even if the updates are being externally ...

Page 61: ...he UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate UISOURCE Signal Any PFI pin can externally input the UISOURCE signal which is not available as an output on the I O connector The UI counter uses the UISOUR...

Page 62: ...ignals are GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT GPCTR0_UP_DOWN GPCTR1_SOURCE GPCTR1_GATE GPCTR1_OUT GPCTR1_UP_DOWN and FREQ_OUT GPCTR0_SOURCE Signal Any PFI pin can externally input the GPCTR0_SOURCE signal which is available as an output on the PFI8 GPCTR0_SOURCE pin As an input the GPCTR0_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR0_S...

Page 63: ... output on the PFI9 GPCTR0_GATE pin As an input the GPCTR0_GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR0_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform actions such as starting and stopping the counter generating interrupts saving the...

Page 64: ...lectable for both options This output is set to tri state at startup Figure 4 28 shows the timing of the GPCTR0_OUT signal Figure 4 28 GPCTR0_OUT Signal Timing GPCTR0_UP_DOWN Signal This signal can be externally input on the DIO6 pin and is not available as an output on the I O connector The general purpose counter 0 will count down when this pin is at a logic low and count up when it is at a logi...

Page 65: ...up Figure 4 29 shows the timing requirements for the GPCTR1_SOURCE signal Figure 4 29 GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTR1_SOURCE unless you select some external source GPCTR1_GATE Signal Any PFI pin can externally inpu...

Page 66: ...gure 4 30 GPCTR1_GATE Signal Timing in Edge Detection Mode GPCTR1_OUT Signal This signal is available only as an output on the GPCTR1_OUT pin The GPCTR1_OUT signal monitors the TC board general purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at ...

Page 67: ... rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram but with the source signal inverted and referenced to the falling edge of the source signal would apply when the counter is programmed to count falling edges The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the in...

Page 68: ...ble only as an output on the FREQ_OUT pin The frequency generator for the 611X E board outputs the FREQ_OUT pin The frequency generator is a 4 bit counter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases The output polarity is software selectable This output is set to tri sta...

Page 69: ...e the 611X E board signal lines from high current or high voltage lines These lines can induce currents in or voltages on the 611X E board signal lines if they run in parallel paths at a close distance To reduce the magnetic coupling between lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other Do not run signal lines through conduits t...

Page 70: ...ereas the last level is the slowest most difficult and most accurate Loading Calibration Constants The 611X E board is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM ...

Page 71: ...e reference This error is addressed by external calibration which is discussed in the following section If you are interested primarily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration The 611X E board has an onboard calibration reference to ensure the accuracy of self calibration Its specifications are listed in Ap...

Page 72: ...ly calibrate your board be sure to use a very accurate external reference The reference should be several times more accurate than the board itself For example to calibrate a 16 bit board the external reference should be at least 0 001 10 ppm accurate PCI_E book Page 3 Thursday June 25 1998 12 55 PM ...

Page 73: ...ling rate 5 MS s Min sampling rate 1 kS s Analog input characteristics Input Range Gain Error1 Offset Error SFDR2 CMRR3 System Noise4 50 V 0 50 10 mV 70 dB 32 dB 0 5 20 V 0 50 10 mV 70 dB 35 dB 0 5 10 V 0 10 0 8 mV 75 dB 50 dB 0 5 5 V 0 05 0 5 mV 75 dB 56 dB 0 5 2 V 0 05 0 28 mV 75 dB 62 dB 0 5 1 V 0 05 0 20 mV 75 dB 67 dB 0 5 500 mV 0 05 0 15 mV 75 dB 70 dB 0 6 200 mV 0 05 0 10 mV 75 dB 72 dB 1 0...

Page 74: ...ain within 11 V for ranges 10 V should remain within 42 V for ranges 10 V input Should remain within 11 V Overvoltage protection 42 V Inputs protected input all channels input all channels FIFO buffer size 8 192 samples Data transfers DMA interrupts programmed I O DMA modes Scatter gather Accuracy Information See following table PCI_E book Page 2 Thursday June 25 1998 12 55 PM ...

Page 75: ...5 1 mV 0 44 mV 0 0005 2 4 mV 0 58 mV 2 0 057 0 058 0 059 1 3 mV 2 mV 0 18 mV 0 0005 0 98 mV 0 23 mV 1 0 057 0 058 0 059 0 7 mV 1 mV 0 088 mV 0 0005 0 49 mV 0 12 mV 0 5 0 057 0 058 0 059 0 4 mV 0 67 mV 0 059 mV 0 0005 0 24 mV 0 077 mV 0 2 0 057 0 058 0 059 0 2 mV 0 39 mV 0 035 mV 0 0005 0 098 mV 0 046 mV Note Accuracies are valid for measurements following an internal E Series calibration Averaged ...

Page 76: ...istics Amplifier Characteristics Input impedance 1 MΩ in parallel with 100 pF Input bias current 200 pA Input offset current 100 pA CMRR See table analog input characteristics Dynamic Characteristics Interchannel skew 1 ns typ fin 100 kHz input range 10 V Bandwidth 0 5 to 3 dB Input range 0 2 V 5 MHz Input range 0 2 V 4 MHz System noise See table analog input characteristics Crosstalk 80 dB DC to ...

Page 77: ...Number of channels 2 voltage Resolution 16 bits 1 in 65 536 Max update rate 1 channel 4 MS s system dependent 2 channel 2 5 MS s system dependent FIFO buffer size 2 048 samples Data transfers DMA interrupts programmed I O DMA modes Scatter gather Transfer Characteristics Relative accuracy INL 4 LSB typ 8 LSB max DNL 2 LSB typ 8 LSB max Offset error 5 0 mV max Gain error relative to internal refere...

Page 78: ...e 1 mVrms DC to 5 MHz Spurious free dynamic range 75 dB DC to 10 kHz Stability Offset temperature coefficient 500 µV C Gain temperature coefficient Internal reference 50 ppm C External reference 25 ppm C Onboard calibration reference Level 5 000 V 2 5 mV actual value stored in EEPROM Temperature coefficient 0 6 ppm C max Long term stability 6 ppm Digital I O Number of channels 8 input output Compa...

Page 79: ...lity TTL CMOS Base clocks available Counter timers 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns edge detect mode Min gate pulse duration 10 ns edge detect mode Level Min Max Input low voltage Input high voltage Input low current V in 0 V Input high current V in 5 V 0 0 V 2 0 V 0 8 V 5 0 V 320 µA 10 µA Output low...

Page 80: ...IG1 Level full scale internal 10 V external Slope Positive or negative software selectable Resolution 8 bits 1 in 256 Hysteresis Programmable Bandwidth 3 dB 5 MHz internal external External input PFI0 TRIG1 Impedance 10 kΩ Coupling AC DC Protection 0 5 V to Vcc 0 5 V when configured as a digital signal 35 V when configured as an analog trigger signal or disabled 35 V powered off Digital Trigger Co...

Page 81: ...5 PCI 6110E 2 5 A PCI 6111E 2 0 A Power available at I O connector 4 65 to 5 25 VDC at 1 A Physical Dimensions not including connectors 31 2 by 10 6 cm 12 3 by 4 2 in I O connector 68 pin male SCSI II type Environment Operating temperature 0 to 45 C Storage temperature 20 to 70 C Relative humidity 5 to 90 noncondensing PCI_E book Page 9 Thursday June 25 1998 12 55 PM ...

Page 82: ...or Descriptions This appendix describes the cable connectors on your 611X E board Figure B 1 shows the pin assignments for the 68 pin 611X E connector This connector is available when you use the SH6868EP cable assemblies with the 611X E board PCI_E book Page 1 Thursday June 25 1998 12 55 PM ...

Page 83: ...ACH3GND1 ACH3 1 ACH2 1 ACH1GND ACH1 ACH0 DGND 1 NC on PCI 6111E PFI8 GPCTR0_SOURCE PFI7 STARTSCAN GPCTR1_OUT PFI4 GPCTR1_GATE PFI3 GPCTR1_SOURCE PFI2 CONVERT DGND DGND DGND EXTSTROBE SCANCLK DIO3 DIO7 DIO2 DGND DIO5 DIO0 DGND AOGND AOGND NC NC NC NC NC NC NC ACH3 1 ACH2GND1 ACH2 1 ACH1 ACH0GND ACH0 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 1...

Page 84: ...roups Analog input two 24 bit two 16 bit counters Analog output three 24 bit one 16 bit counters General purpose counter timer functions two 24 bit counters The groups can be configured independently with timing resolutions of 50 ns or 10 µs With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and comp...

Page 85: ...gnal but my readings are random and drift rapidly What s wrong Check your ground reference connections Your signal may be referenced to a level that is considered floating with reference to the board ground reference Even if you are in differential mode the signal must still be referenced to the same ground level as the board reference There are various methods of achieving this while maintaining ...

Page 86: ...PFI5 as follows If you are using NI DAQ call Select_Signal deviceNumber ND_IN_CONVERT ND_PFI_5 ND_HIGH_TO_LOW If you are using LabVIEW invoke AI Clock Config VI with clock source code set to PFI pin high to low and clock source string set to 5 3 Initiate analog input data acquisition which will start only when the analog output waveform generation starts 4 Initiate analog output waveform generatio...

Page 87: ... the answer is no the counter timer applications that you wrote previously will not work with the DAQ STC You must use the GPCTR functions ICTR and CTR functions will not work with the DAQ STC The GPCTR functions have the same capabilities as the ICTR and CTR functions plus more but you must rewrite the application with the GPCTR function calls I m using one of the general purpose counter timers o...

Page 88: ...any external signal source to it if you do you can damage the board the computer and the connected equipment What are the power on states of the PFI and DIO lines on the I O connector At system power on and reset both the PFI and DIO lines are set to high impedance by the hardware This means that the board circuitry is not actively driving the output either high or low However these lines may have...

Page 89: ...ur questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrument drivers upd...

Page 90: ...you purchased your software to obtain support Country Telephone Fax Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0662 45 79 90 19 Belgium 02 757 00 20 02 757 03 11 Brazil 011 288 3336 011 288 8528 Canada Ontario 905 785 0085 905 785 0086 Canada Québec 514 694 8521 514 694 4399 Denmark 45 76 26 00 45 76 26 02 Finland 09 725 725 11 09 725 725 55 France 01 48 14 24 24 01 48 14 24 14 Ge...

Page 91: ...________________________ _______________________________________________________________________________ National Instruments hardware product model __________ Revision ______________________ Configuration ___________________________________________________________________ National Instruments software product ____________________________Version ____________ Configuration _________________________...

Page 92: ... version __________________________________________________________________ Other Products Computer make and model _________________________________________________________ Microprocessor ___________________________________________________________________ Clock frequency or speed ___________________________________________________________ Type of video board installed _____________________________...

Page 93: ...___________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ ____________________________________________________...

Page 94: ...Numbers degrees greater than greater than or equal to less than less than or equal to per percent plus or minus positive of or plus Prefix Meaning Value p pico 10 12 n nano 10 9 µ micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 109 PCI_E book Page 1 Thursday June 25 1998 12 55 PM ...

Page 95: ...ntegrated circuit that converts an analog voltage to a digital number AI analog input AIGATE analog input gate signal AIGND analog input ground signal ANSI American National Standards Institute AO analog output AOGND analog output ground signal ASIC Application Specific Integrated Circuit a proprietary semiconductor component designed and manufactured to perform a set of specific functions B bipol...

Page 96: ...nce from a common mode signal usually expressed in decibels dB CONVERT convert signal counter timer a circuit that counts external pulses or clock pulses timing CTR counter D D A digital to analog DAC digital to analog converter an electronic device often an integrated circuit that converts a digital number into a corresponding analog voltage or current DAC0OUT analog channel 0 output signal DAC1O...

Page 97: ...emory from to a device or memory on the bus while the processor does something else DMA is the fastest method of transferring data to from computer memory DNL differential nonlinearity a measure in least significant bit of the worst case deviation of code widths from their ideal value of 1 LSB DO digital output E EEPROM electrically erasable programmable read only memory ROM that can be erased wit...

Page 98: ...associated with getting the data from system memory to the DAQ device FREQ_OUT frequency output signal ft feet G GATE gate signal GPCTR general purpose counter signal GPCTR0_GATE general purpose counter 0 gate signal GPCTR0_OUT general purpose counter 0 output signal GPCTR0_SOURCE general purpose counter 0 clock source signal GPCTR0_UP_DOWN general purpose counter 0 up down signal GPCTR1_GATE gene...

Page 99: ...tion and control interfaces IOH current output high IOL current output low K kHz kilohertz L LED light emitting diode LSB least significant bit M m meter MB megabytes of memory MHz megahertz MIO multifunction I O MITE MXI Interface to Everything MSB most significant bit mux multiplexer a switching device with multiple inputs that sequentially connects each of its inputs to its output typically at ...

Page 100: ...de all measurements are made with respect to a common NRSE measurement system reference but the voltage at this reference can vary with respect to the measurement system ground O OUT output pin a counter output pin where the counter can generate various TTL pulse waveforms P PCI Peripheral Component Interconnect a high performance expansion bus architecture originally developed by Intel to replace...

Page 101: ...digital input and or output ppm parts per million pu pull up R RAM random access memory rms root mean square RSE referenced single ended mode all measurements are made with respect to a common reference measurement system or a ground Also called a grounded measurement system RTD resistive temperature detector a metallic probe that measures temperature based upon its coefficient of resistivity RTSI...

Page 102: ...mon ground settling time the amount of time required for a voltage to reach its final value within specified limits signal conditioning the manipulation of signals to prepare them for digitizing SISOURCE SI counter clock signal SOURCE source signal S s samples per second used to express the rate at which a DAQ board samples an analog signal STARTSCAN start scan signal system noise a measure of the...

Page 103: ...e width TTL transistor transistor logic U UI update interval UISOURCE update interval counter clock signal unipolar a signal range that is always positive for example 0 to 10 V UPDATE update signal V V volts VDC volts direct current VI virtual instrument 1 a combination of hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 a ...

Page 104: ...Corporation G 11 PCI 6110E 6111E User Manual VOH volts output high VOL volts output low Vref reference voltage Vrms volts root mean square W WFTRIG waveform generation trigger signal PCI_E book Page 11 Thursday June 25 1998 12 55 PM ...

Page 105: ...rces figure 4 11 nonreferenced or floating signal sources figure 4 12 signal summary table 4 6 AIGATE signal 4 25 amplifier characteristic specifications A 3 to A 4 analog input 3 2 to 3 5 dither 3 4 to 3 5 input coupling 3 4 input mode 3 2 to 3 3 input polarity and range 3 3 to 3 4 questions about C 2 to C 3 selection considerations 3 4 signal connections 4 8 specifications A 1 to A 5 amplifier c...

Page 106: ... questions and answers common mode signal rejection 4 12 ComponentWorks software 1 3 configuration PCI 6110E 6111E 2 2 questions about C 2 connectors See I O connectors CONVERT signal input timing figure 4 24 multiplexer for controlling figure 3 11 output timing figure 4 24 signal routing 3 11 to 12 timing connections 4 23 to 4 25 counter timer applications C 4 to C 5 customer communication xiv D ...

Page 107: ...ation xiii xiv organization of manual xi xii related documentation xiv dynamic characteristic specifications analog input A 4 analog output A 6 E EEPROM storage of calibration constants 5 1 electronic support services D 1 to D 2 e mail support D 2 environment specifications A 9 environmental noise avoiding 4 35 to 4 36 equipment optional 1 5 EXTSTROBE signal description table 4 3 signal summary ta...

Page 108: ...dither 3 4 to 3 5 input mode 3 2 to 3 3 input polarity and range 3 3 to 3 4 selection considerations 3 4 analog output 3 5 analog trigger 3 6 to 3 9 block diagrams PCI 6110E 3 1 PCI 6111E 3 2 digital I O 3 10 timing signal routing 3 11 to 13 board and RTSI clocks 3 12 CONVERT signal routing figure 3 11 programmable function inputs 3 12 RTSI triggers 3 13 I input characteristic specifications A 1 t...

Page 109: ...RIG2 signal description table 4 4 signal summary table 4 6 PFI2 CONVERT signal description table 4 4 signal summary table 4 6 PFI3 GPCTR1_SOURCE signal description table 4 4 signal summary table 4 6 PFI4 GPCTR1_GATE signal description table 4 4 signal summary table 4 7 PFI5 UPDATE signal description table 4 4 signal summary table 4 7 PFI6 WFTRIG signal description table 4 5 signal summary table 4 ...

Page 110: ... summary table 4 6 timing connections 4 18 signal connections analog input 4 8 analog output 4 13 differential measurements 4 9 to 4 12 common mode signal rejection 4 12 connection considerations 4 10 floating signal sources 4 9 4 11 to 4 12 ground referenced signal sources 4 9 4 11 nonreferenced signal sources 4 11 to 4 12 recommended configuration table 4 10 digital I O 4 13 to 4 14 field wiring...

Page 111: ...irtualBench 1 3 specifications analog input A 1 to A 5 amplifier characteristics A 3 to A 4 dynamic characteristics A 4 input characteristics A 1 to A 2 stability A 4 to A 5 transfer characteristics A 2 to A 3 analog output A 5 to A 6 dynamic characteristics A 6 output characteristics A 5 stability A 6 transfer characteristics A 5 voltage output A 5 to A 6 analog trigger A 8 bus interface A 9 digi...

Page 112: ... function inputs 3 12 RTSI triggers 3 13 transfer characteristic specifications analog input A 2 to A 3 analog output A 5 TRIG1 signal input timing figure 4 20 output timing figure 4 20 timing connections 4 19 to 4 20 TRIG2 signal input timing figure 4 21 output timing figure 4 21 timing connections 4 20 to 4 21 trigger analog above high level analog triggering mode figure 3 8 avoiding false trigg...

Page 113: ...m generation timing connections 4 26 to 4 29 UISOURCE signal 4 28 to 4 29 UPDATE signal 4 27 to 4 28 WFTRIG signal 4 26 to 4 27 WFTRIG signal input signal timing figure 4 27 output signal timing figure 4 27 timing connections 4 26 to 4 27 wiring considerations 4 35 to 4 36 PCI_E book Page 9 Thursday June 25 1998 12 55 PM ...

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