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Chapter 5
Counters
Figure 5-25.
Sample Clocked Buffered Two-Signal Separation Measurement
Note
If an active edge on the Gate and an active edge on the Aux does not occur
between sample clocks, an overrun error occurs.
For information about connecting counter signals, refer to the
section.
Counter Output Applications
The following sections list the various counter output applications available on the cDAQ
controller:
•
•
•
•
•
Simple Pulse Generation
Refer to the following sections for more information about the cDAQ controller simple pulse
generation options:
•
•
Single Pulse Generation with Start Trigger
Single Pulse Generation
The counter can output a single pulse. The pulse appears on the Counter
n
Internal Output signal
of the counter.
You can specify a delay from when the counter is armed to the beginning of the pulse. The delay
is measured in terms of a number of active edges of the Source input.
S
OURCE
Co
u
nter V
a
l
u
e
B
u
ffer
AUX
GATE
1
2
3
1
2
3
1
2
3
3
3
3
Sa
mple
Clock
