NI 5782R User Manual and Specifications
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© National Instruments
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The NI 5782 ships with socketed CLIP items that add module I/O to the LabVIEW project. The
NI 5782 ships with the following CLIP items:
1.
NI 5782 Multiple Sample CLIP
—The analog input channels generate two samples per
clock cycle at a clock rate that is half the sample rate. The analog output channels generate
four samples per clock cycle at a clock rate that is one quarter of the sample rate. The AI
default sample rate is 250 MHz, and the AO default sample rate is 500 MHz. The default
clock rate for this CLIP is 125 MHz. You can set a lower sample rate by using an external
Sample Clock.
This CLIP presents the data to the diagram in a decelerated format. The ADC data lands at
half the rate as the ADC clock. The DAC data must be presented in four time samples per
clock on each channel.
This CLIP provides access to two AI channels, two AO channels, eight bidirectional DIO
channels, four bidirectional PFI channels
, and an input clock selector that can be configured
to use one of the following settings:
–
Internal Sample Clock
–
Internal Sample Clock locked to an external Reference Clock through the CLK IN
connector
–
External Sample Clock through the CLK IN connector
–
Internal Sample Clock locked to an external Reference Clock through
IoModSyncClock
–
External Sample Clock through IoModSyncClock
This CLIP also contains an engine to program the CLK chip, ADCs, and DACs, either
through predetermined settings for an easier instrument setup, or through a raw SPI address
and data signals for a more advanced setup. The NI 5782 Multiple Sample CLIP is the
default CLIP.
2.
NI 5782 Single Sample CLIP
—The analog input channels generate one sample per clock
cycle and the analog output channels generate two samples per clock cycle. The default
clock rate for the Multiple Sample CLIP is 250 MHz. The Sample Clock rates of
AI (250 MHz) and AO (500 MHz) are the same as Multiple Sample CLIP. You can set
lower sample rates with the external Sample Clock.
This CLIP presents the data to the diagram at a clock rate such that the ADC data lands at
the same rate as the ADC clock. However, the DAC data must be presented in two time
samples per clock on each channel.
This CLIP provides access to two AI channels, two AO channels, eight bidirectional DIO
channels, four bidirectional PFI channels, and an input clock selector that can be configured
to use one of the following settings:
–
Internal Sample Clock
–
Internal Sample Clock locked to an external Reference Clock through the CLK IN
connector
–
External Sample Clock through the CLK IN connector
