36
Pin No.
Port Name
I/O
FUNCTION
1
AVSS
---
Ground pin for DSL, PLL circuit.
2
IREF
I
Reference current input pin.
3
ARF
I
RF signal input pin.
4
DRF
---
Bias pin for DSL.
5
DSLF
O
Loop filter pin for DSL.
6
PLLF
l/O
Loop filter pin for PLL.
7
AVDD
---
+5 V power supply pin for DSL, PLL.
8
RSEL
---
RF signal polarity setting pin. (Brightness level : H--> RSEL: H)
9-16
TBUS0-7
O
Test pins. Normally, these pins are open circuit.
17
FLAG
O
Flag output pin.
18
IPFLAG
O
Interpolation flag pin. (H: interpolate)
19
FCLK
O
Frame clock output (from crystal OSC). (fCLK=7.35 kHz,14.7 kHz when dubble speed)
20
BYTCK
O
Byte clock out.
21
WDCK
O
Word clock out.
22
/RST
I
Reset input pin (L: reset).
23
TX
O
Digital audio interface output.
24
LDG
O
L-CH deglitch signal output.
25
RDG
O
R-CH deglitch signal output.
26
SRDATA
O
Serial data output.
27
SCK
O
Bit clock output for SRDATA.
28
LRCK
O
Left-right discrimination clock output.
29
XCK
O
Crystal OSC clock output (fXCK=16.9344 MHz).
30
PMCK
O
1/192 counted down clock signal from the crystal OSC. (fPMCK=88.2 kHz)
31
CSEL
I
Crystal OSC frequency select pin. (L: 16.9344 MHz, H: 33.8688 MHz)
32
PSEL
---
Test pin (normally, open circuit).
33
X1
I
Crystal connecting pin. (f=16.9344 MHz or 33.8688 MHz)
34
X2
O
Crystal connecting pin. (f=16.9344 MHz or 33.8688 MHz)
35
VSS
---
Ground pin.
36
SUBQ
O
Subcode Q output.
37
SQCK
I
External clock input for Subcode Q register.
38
/CLDCK
O
Subcode frame clock signal output. (fCLDCK=7.35 kHz in normal palyback)
39
BLKCK
O
Subcord block clock signal. (fBLOCK= 75 Hz in normal playback)
40
DEMPH
O
De-emphasis control output. (H: de-emphasis on)
41
MEMP
I
Emphasis signal input for digital audio interface.
42
MLD
I
MI-COM command LOAD signal input. (L: LOAD)
43
MCLK
l
MI-COM command CLOCK signal input. (Data will be latched with rising edge of the pulse)
44
MDATA
l
MI-COM command DATA input.
45
DMUTE
I
Muting input.
46
SMCK
O
1/2 counted down crystal OSC signal output when MSEL=H.
1/4 counted down crystal OSC signal output when MSEL=L.
47
STAT
O
Status signal output (CRC, CUE, CLVS, TTSTOP, FCLV, SQOK).
48
CRC
O
Subcode CRC check output. (H: OK, L: no good)
49
SUBC
O
Subcode serial output data.
50
SBCK
I
Clock input for subcode serial output.
51
/TRON
I
Tracking servo on signal. (L: tracking on)
52
CLVS
O
Spindle servo phase synchronization judge output. (H: CLV, L: rough cervo)
53
PC
O
Spindle motor on signal (L= on).
54
ECM
O
Spindle motor drive signal output (forced mode, 3-state).
55
ECS
O
Spindle motor drive signal output (servo error signal, 3-state).
56
VDD
---
+5V power supply.
7.10 MN66261 (CD signal processor) - IC490 on DVD Main P.C.B. Ass’y
(to be continued)
IC BLOCK DIAGRAMS
Summary of Contents for DVD-15
Page 14: ...14 MECHANICAL ASS Y AND PARTS LIST 4 2 Mechanism Ass y DVD 15 A01 Fig 4 2...
Page 17: ...17 MECHANICAL ASS Y AND PARTS LIST 4 4 Loading EX Ass y ADJ 3 B02 Fig 4 4...
Page 51: ...To Digital PCB P550 DVD 15 MECHANISM C3M1 SCHEMATIC DIAGRAM...
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