Nakamichi DVD-15, Service Manual

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7.16 CYC13D000 (DVD Sync /ECC / Formatter) - IC500 on DVD Main P.C.B. Ass’y
Pin No. Port Name l/ O FUNCTION
1,12,26,35,46
52,63,73,81
95,105,118
VSS1-18 --- Grounded.
131,142,156
170,182,195
2 SEL0 --- Grounded.
3 SEL1 --- Test mode select pins.
4-6,8,10,11
14-22,28,29
116,117,119
125,126,132
TEST 9-46 --- Test mode output pins. (Leave them open)
171-174,194
197-206
7 AVRTM O End of output stream of 2060 byies data to CSS.
9 XSRTM O End of block signal.
13,25,33,45,
VDD-5
53, 62,72,140,
1-12 --- +5 V power supply.
157,169,196,208
23 MLD O Microprocessor command load signal for CD-DA section. (L: Ioad).
24 MCLK O Microprocessor command clock signal for CD-DA section.
(data is atched on rising edge)
27 MDATA O Microprocessor command data for CD-DA section.
30 DEMPH I De-emphasis control input (H: on).
31 DMUTE O Muting output for CD-DA section.
32 STAT l Status signal (CRC, CUE, CLVS, TTSTOP, FCLV, SQOK) from CD-DA, STAT also
goes to CPU.
34 PLLCLK l 27 MHz clock input pin.
36 CHNDATA l Inverted bit data, which is changed on the falling edge of PLLCLK.
37 SDTIO I/O Serial bit data l/O.
38 ASPSCK O 296ns clock (27 MHz/8) output.
39 SEN O High enable CPU to write data to 8 read-channel registers.
40 PLLOK O DVD frame sync (H: O.K)
41 LDON O Turn on the Laser diode.
42 XDVD O DVD mode control output.
43 XCD2 O 2X CD mode control output.
44 XCD4 O 4X CD mode control output.
47-51,54-56 SRMDT0-7 I/O SRAM data bus.
57-61 ,64-71
74-77 SRMADR0-16 O SRAM address bus.
78 XSRMCE O Chip enable signal to SRAM.
79 XSRMOE O Output enable signal to SRAM.
80 XSRMWE O Write enable signal to SRAM.
82,84,104 VDD-3 --- +3.3 V power supply.
114,175,184 1-6
83-90 SDMDT0-7 l/O SDRAM data bus.
91-93
96-103,106 SDMADR0-11 O SDRAM address bus.
107 SDMRAS O SDRAM row address strobe output.
108 SDMCAS O SDRAM column address strobe output.
109 SDMWE O SDRAM write enable output.
110 SDMDQML O SDRAM Iower byte input/output mask.
111 SDMCLK O Clock signal output to SDRAM.
112 SDMCS O SDRAM chip select control.
113 SDMDQMU O SDRAM upper byte input/output mask.
115 SDMCKE O SDRAM clock enable.
120 XDSCO O Chip select signal to the SERVO Ml-COM.
121 CRCOK O Sector IDs are O.K.
IC BLOCK DIAGRAMS
(to be continued)