N.A.T. NAT-MCH, Technical Reference Manual

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NAT-MCH BASE-Module– Technical Reference Manual
Version 2.10 © N.A.T. GmbH 6
List of Tables
Table 1:
List of used Abbreviations ...................................................................... 7
Table 2: NAT-MCH BASE-Module – Coax-IO signal mapping ...................................15
Table 3: NAT-MCH BASE-Module – Coax-IO Electrical characteristics ......................15
Table 4: CON1: MCH Connector – Pin-Assignment ................................................19
Table 5: CON2: Extension Module Connector – Pin Assignment ..............................21
Table 6: JP1: Altera FPGA Programming Port – Pin Assignment ..............................21
Table 7: JP2: LED-Module Connector – Pin Assignment .........................................21
Table 8: JP3: Development Connector – Pin Assignment .......................................22
Table 9: P3: External Clock Transceiver Module Connector – Pin Assignment ..........22
Table 10: S1: Micro USB Connector – Pin Assignment .............................................23
Table 11: S100: RJ45 Connector – Pin-Assignment ................................................23
Table 12: S101: RJ45 Connector – Pin-Assignment – GbE-Interface ........................23
Table 13: S101: RJ45 Connector – Pin-Assignment – RJ45-Clock-Interface ..............23
Table 14: NAT-MCH BASE-Module – Features ........................................................25
List of Figures
Figure 1:
NAT-MCH BASE-Module – Block Diagram incl. LED Module ........................10
Figure 2: NAT-MCH BASE-Module – Location Diagram – top-view ............................11
Figure 3: NAT-MCH BASE-Module – Front Panel .....................................................17
Figure 4: NAT-MCH BASE-Module – Connectors – Overview ....................................18