NAT-MCH BASE-Module– Technical Reference Manual
Version 2.10
© N.A.T. GmbH
12
3
Board Features
The
NAT-MCH BASE-Module
can be divided into a number of functional blocks, which
are described in the following paragraphs.
3.1
CPU
The
NAT-MCH BASE-Module
features a 32-bit CPU ColdFire MCF54452 (Freescale)
which is based on the V4e ColdFire core. The MCF54452 includes a memory management
unit (MMU), a dual precision floating-point unit (FPU) and an enhanced multiply-
accumulate unit (EMAC), delivering 308 (Drystone 2.1) MIPS at 266 MHz.
The processor has integrated a 32 KB I-Cache, a 32 KB D-Cache and 32 KB on-chip
system SRAM. The MCF54452 is equipped with a 32-bit DDR2 266 controller at 133 MHz
clock rate.
The MFC5470 ColdFire integrates the following interfaces:
two 10/100 Ethernet Controllers (FECs)
DSPI – SPI with DMA capability
a I²C interface
a 16-channel DMA controller
USB Interface
3.2
Memory
3.2.1
DDR2SDRAM
The onboard DDR2SDRAM memory is 16 bit wide; its size is 32 or 64 MB
(assembly option). The interface to the SDRAM is implemented in the ColdFire
MCF54452. By programming several registers, the SDRAM controller can be
adapted to different RAM architectures.
3.2.2
FLASH
FLASH memory is connected to the demultiplexed upper 16 data bits D0 – 15 of
the local bus and to the latched address lines. Its size is 16, 32 or 64 MB
(assembly option).The FLASH on the
NAT-MCH BASE-MODULE
can be
programmed by the CPU (by appropriate software) or through the BDM port.
