CHAPTER 4
AWARD
®
BIOS SETUP
4-15
EDO DRAM Write Burst
This sets the timing for burst mode writes from DRAM (EDO).
Burst read and write requests are generated by the CPU in four separate
parts. The lower the timing numbers, the faster the system will address
memory.
x222
Write DRAM timings are 2-2-2-2
x333
Write DRAM timings are 3-3-3-3
CPU-To-PCI IDE Posting
Select Enabled to post write cycles from the CPU to the PCI IDE
interface. IDE accesses are posted in the CPU to PCI buffers, cycle
optimization. The settings are Enabled or Disabled.
System BIOS Cacheable
Select Enabled allows caching of the system BIOS ROM at F000h-
FFFFFh, resulting in better system performance. However, if any program
writes to this memory area, a system error may result.
Enabled
BIOS access cached
Disabled
BIOS access not cached
Video BIOS Cacheable
Select Enabled allows caching of the system BIOS ROM at C0000h-
F7FFFh, resulting in better video performance. However, if any program
writes to this memory area, a system error may result.
Enabled
Video BIOS access cached
Disabled
Video BIOS access not cached
Video RAM Cacheable
Select Enabled allows caching of the video RAM, resulting in better
system performance. However, if any program writes to this memory area, a
system error may result.
