MSI 790XT-G35 series, Manual

Page: 56 / 103

3-22
BIOS Setup
▍
MS-7388
BIOS Setup
▍
MS-7388
ths field to [DCT 0], [DCT 1] or [Both], some fields wll appear and selectable. DCT
0 controls channel A and DCT1 controls channel B.
CAS Latency (CL)
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. Ths controls the CAS latency, whch determnes the tmng delay (n clock
cycles) before SDRAM starts a read command after recevng t.
tRCD
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. When DRAM s refreshed, both rows and columns are addressed separately.
Ths setup tem allows you to determne the tmng of the transton from RAS (row
address strobe) to CAS (column address strobe). The less the clock cycles, the
faster the DRAM performance.
tRP
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. Ths settng controls the number of cycles for Row Address Strobe (RAS) to
be allowed to precharge. If nsufficent tme s allowed for the RAS to accumulate ts
charge before DRAM refresh may be ncomplete and DRAM may fal to retan data.
Ths tem apples only when synchronous DRAM s nstalled n the system.
tRAS
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. Ths settng determnes the tme RAS takes to read from and wrte to a memory
cell.
tRTP
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. Ths settng controls the tme nterval between a read and a precharge com-
mand.
tRC
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. The row cycle tme determnes the mnmum number of clock cycles a memory
row takes to complete a full cycle, from row actvaton up to the prechargng of the
actve row.
tWR
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. It specfies the amount of delay (n clock cycles) that must elapse after the
completon of a vald wrte operaton, before an actve bank can be precharged. Ths
delay s requred to guarantee that data n the wrte buffers can be wrtten to the
memory cells before precharge occurs.
tRRD
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. Specfies the actve-to-actve delay of dfferent banks.
tWTR
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. Ths tem controls the Wrte Data In to Read Command Delay memory tmng.
Ths consttutes the mnmum number of clock cycles that must occur between the
last vald wrte operaton and the next read command to the same nternal bank of
▶
▶
▶
▶
▶
▶
▶
▶
▶