Motorola Timeport P8190, Service Manual

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Theory of Operation Service Manual
85
limiting the output swing. The comparators
are realized in software.
The post-limiter splatter filter is realized
using a 17-tap FIR digital filter. This stage
includes a down-shelf filter realized using one
pole and one zero of IIR digital filtering. The
up- and down-shelf filters work together with
the splatter filter to limit the maximum de-
viation of the transmitter. The TX Mic. Au-
dio mute is realized in software.
Data/Signaling Tone (ST) is generated as a
sinusoidal signal using a look-up table. This
method produces less harmonic energy than
pure “Manchester” encoding would generate,
easing the requirements for filtering of this
signal.
DTMF is generated using look-up tables and
SAT processing is also performed in the
Transmit Audio Circuitry.
The summing of all Analog Transmit Modu-
lation signals (Mic. Audio, Data/ST, DTMF
and SAT) is performed in software.
The D/A converts the audio samples to an
analog signal. The resultant analog wave-
form is filtered by a 5th-order low-pass
switched-capacitor filter and a two-pole, two-
zero continuous-time filter to remove aliases.
The Master Deviation Adjust is realized by
a digitally controlled amplifier. The result-
ant signal is then applied to the Analog Mod.
input of the synthesizer circuit.
Digital TX Audio Processing
The analog voice signal is taken from the
microphone and digitized by the CODEC
using an A/D converter. The codec also con-
tains filtering to remove aliases before sam-
pling. The audio samples are then transmit-
ted to the DSP.
In the DSP, microphone compensation and
echo cancellation is applied to the Tx audio.
Following these processes, the DSP uses
VSELP (Vector-Sum Excited Linear Predic-
tion) to compress the 160 samples of voice
data into 159 bits of voice data. After the data
has been compressed, the DSP separates the
voice data into class I and class II bits. A
cyclic redundancy check (CRC) is performed
on the most significant class I bits. The CRC
is used during the decoding process to deter-
mine the validity of the class I bits. Redun-
dancy is then added to the class I bits by per-
forming a rate-1/2 convolutional encoding
operation on the class I bits and the CRC.
The redundancy is used during the decoding
process to correct class I errors. The class II
bits are not encoded. The rate-1/2
convolutionally encoded class I bits and the
class II bits are then interleaved with speech
data from adjacent speech frames. Interleav-
ing is used during the decoding process to
reduce the effects of burst errors. The DSP
then combines system messages with the
interleaved rate-1/2 convolutionally encoded
class I bits and class II bits. The resultant
bits are sent to a data converter to be modu-
lated.
The data converter modulates the data us-
ing differential quadrature phase shift key-
ing (DQPSK) to generate in-phase and
quadrature-phase data. The in-phase and
Digital TX Audio Processing