Part
Designator
Part
Description
Part
Number
Part
Designator
Part
Description
Part
Number
AL800
Alert
5009473S01
Q501
Transistor TX_EN
4809607E05
CR605
Diode Charger Line
4809653F03
Q601
Power Transistor Chrg Line
4809579E17
CR910
Diode VSwitch Line
4809653F02
Q602
Transistor BATT_FDBACK
LINE
4809939C04
J101
Display Connector
2809454C02
R602
Resistor for ISENSE
0680195M64
J600
EXT/Butt Plug Connector
0909449B04
T902
Choke / Switched Supply
2503788S08
J601
Flexprint Connector
0909059E01
U500
SMOC IC
5199332C04
J802
MIC Connector
0909195E01
U703
BIC IC
51097463E13
MIC
Microphone
5009135L07
U900
GCap IC
5109632D75
FREQUENCIES
GSM KRUNCH AUDIO LOGIC BLOCK DIAGRAM
LOGIC BOARD SIGNALS
Chip
Select
External
Bus
Interface
U
7
0
1
C
a
ll
P
ro
ce
ss
o
r
to U702
to U710
to U710
to BIC
to U705
Audio
Filter
Audio
Filter
Buffer
Ampl.
SRAM
U704
EEPROM
U705
FLASH
U702
ADDRESSS / DATA BUS
Tone
Generator
A/D
D/A
CODEC
BIC
U703
37
31
32
1
3
M
H
z
C
L
O
C
K
48
20
B
C
E
A
D
D
R
E
S
S
S
/
D
A
T
A
B
U
S
S
ig
n
a
l
P
ro
c
e
s
s
in
g
CPU
Interface
CPU
SPI
GMSK
to GIFSYN
to GIFSYN
to PAC / SMOC
AFC
D / A
to SMOC
to SMOC
17
13 MHz Clock
CLK_13IN
from GIFSYN
2
46
J600
Q500
PLL
Transmit
Power
Control
D / A
3
T
im
e
P
ro
c
es
si
n
g
U
n
it
Queued
Serial
Module
Multiplexer
Q501
U500
SMOC IC
Europe Middle East & Africa Customer Services
11.08.98
LEVEL 3 COLOUR DIAGRAMS
Rev. 1.0
GSM KRUNCH Block Diagram
Colin Jack, Michael Hansen, Billy Jenkins, Ralf Lorenzen
Page 1 of 2
# press 2 sec.
Enter Manual Test Mode
01 #
Exit Manual Test Mode
07 #
Mute Rx Audio Path
08 #
Unmute Rx Audio Path
09 #
Mute Tx Audio Path
10 #
Unmute Tx Audio Path
11 #
Program Main Local Osc. to Channelbb
12 #
Set Tx Power level to fixed valure
19 #
Display SW Version Number of Call Processor
20 #
Display SW Version Number of Modem
22 #
Display SW Version Number of Speech Coder
25 #
Set Continuous AGC
26xxxx #
Set Continuous AFC
31x #
Initiate Pseudo-Random Sequence with Midamble
33xxx #
Synchronize to BCH Carrier
36 #
Initiate Acoustic Loopback
37 #
Stop Test
45xxx #
Serving Cell Power Level
46 #
Display Current Valure od AFC DAC
47x #
Set Audio Volume
58 / xxxxxx #
Display / Modify Security Code
59 / xxx #
Display / Modify Lock Code
60 #
Display IMEI
7100 #
Display Error Code
TEST COMMANDS
REVISIONS
AL LAYER - ORDERABLE SPARES
RX SIGNAL PATH
TX SIGNAL PATH
MAIN VCO SIGNAL PATH
TUNING VOLTAGES
REFERENCE CLOCK
Orderable Part
Non - Orderable Part
35
2.8Vpp
DUAL_CS
RESET
2,8Vrms
TX_EN
RX_EN
2.8mVpp
RAM1_CS
RAM2_CS
Measured in standby mode
DP_EN
10ms / cm
7Vpp
10ms / cm
200ms / cm
100ns / cm
2.8Vpp
100ns / cm
2.8Vpp
100ns / cm
2.8Vpp
100ns / cm
start up or
press key
start up or
press key
2.8Vpp
2ns / cm
SC_INT
MF_INT
BIC_INT
2.8Vpp
1ms / cm
2.8Vpp
50us / cm
press a key
UPLINK
DOWNLINK
5Vpp
10us / cm
2.8Vpp
10us / cm
AUDIO IN
2.7Vpp
5us / cm
test mode
08#, 10#, 36#
434#, 477#
AUDIO OUT
2.8Vpp
5us / cm
test mode
08#, 10#, 36#
434#, 477#
CLK_AUD
FS_AUD
2.8Vpp
5us / cm
2.8Vpp
5us / cm
CLK_13_IN
1.6Vpp
50ns / cm
power on
From the CPU (U701). When high, Rx path enabled and low muted.
From CPU (U701), but inverted by Q501. High when
1. Enable the Rf switch for transmit mode & also the GIFSYN for transmit mode.
2. Supply Voltage for the PAC IC.
3. Isolates RF, by switching the PA Bias Circuitry ( Not shown).
1. Enables the Rf switch (U401) for receive mode.
2. Biases the mixer Q420, and low noise amp (Q418).
Controlled at power up by FCAP (U900) & CPU (U701).
1. Connected to CPU (U701), BIC (U703), SMOC (U500)
After power up sequence, any chip can hold RESET low to power phone off if there is a problem.
From CPU (U701) to Eprom.
1. Chip Enable controlling read/write access to and from Eprom (U702).
From CPU (U701) to SRAM.
1. Chip Enable controlling read/write access to and from 1st half of SRAM (U704).
From CPU (U701) to SRAM.
1. Chip Enable controlling read/write access to and from 2nd half of SRAM (U704).
From CPU (U701) to Eprom.
1. Chip Enable controlling read/write access to and from Eprom (U702).
ROM1_CS
2.8Vpp
100ns / cm
Measured in test mode
From CPU (U701) to display, via connector J101.
1. Processor selects to enable display. When high, the display is enabled and low disabled.
SMOC Interface. This is a signal from uP (U701) to SMOC (U500).
1) This is a 20ms timing signal from U701 which times the decoding and encoding function of the SMOC
U500.
From BIC chip (U703) to butt plug (J600). . This is a comms link from an external peripherale and the phone,
and could be either data information or speech information. It is also used to sense the presence of a DHFA and
the ignition status of the DHFA with DC levels
. This is a comms link from an external peripherale and the phone,
and could be either data information or speech information. It is also used to sense the presence of a DHFA and
the ignition status of the DHFA with DC levels
From butt plug (J600) to BIC chip (U703).
From GIF Syn to BIC IC - 13MHz clock..
Motorola Confidential Proprietary
From BIC to uP.
This is the master clock reference required for the radio
This signal periodically interrupts the uP at 217Hz. During Power Saving mode this signal is set
to DC.
From BIC to uP. This signal interrupts the uP for a number of reasons.
1. Keypad detection
2. Power Sense
3. SIM Functions
4. DSC Bus Status Indicators
External audio from butt plug, directly to SMOC IC
External audio from SMOC via FCAP to butt plug
This signal is from the BIC to the SMOC
It is a timing signal and runs at 512KHz, and times the transfer of speech information on the DSC
Bus between BIC and SMOC.
This signal is from the BIC to the SMOC
It is a timing signal at 8KHz and provides for frame synchronisation during speech transfer on
the DSC bus.
A
D
D
R
E
S
S
S
/
D
A
T
A
B
U
S
DISPLAY
J101
DISPLAY
CONNECTOR
21
38
40
34
33
COMMON PROBLEMS
D
C
A
uBGA
CHANNEL
Tx
Rx
MAIN
VCO
Rx I.F
Rx I.F
L.O
Tx I.F
Tx I.F
L.O
1-Low
890.2
935.2
720.2
215
430
170
340
62-Middle
902.4
947.4
732.4
215
430
170
340
124-High
914.8
959.8
744.8
215
430
170
340
A/D
D/A
CHARGER
15
20
5
6
21
J802
19
10
J601
1
2
-1
-
-
+
+
-
A
L
E
R
T
E
A
R
P
IE
C
E
16
7
8
+
-
VSWITCH
28
22
40
B+ DC/DC
37
VSWITCH
3
32, 41
5.6V
AL
RF
AL
SW
RF
CR910
39
Boost Mode Circuitry
Vswitch DC/DC
11
VSWITCH
T
9
0
2
R275
L275
R475
L500
VREF
B+
RX_AUDIO
EXT_AUD
MIC_AUD_IN
TXQ_P
TXQ_M
TXI_P
TXI_M
RXI
IQ_REF
RXQ
(O
n
ly
a
v
a
il
a
b
le
w
it
h
a
c
o
m
p
le
te
f
li
p
a
ss
em
b
ly
)
from
BATT_SER_DATA
BATT_GND
THERM
Battery
Select Circuit
A
U
X
_
B
A
T
T
+
EXT_B+
MIC
E
X
T
_
B
+
MAIN Battery
1-5
12-16
11
6
Charge
Select Circuit
B+
Q601
Q602
R
6
0
2
CR605
ISENSE
BATT_FDBAK
CHG
MAN_TEST
6
4
5
10, 15
GND
14
11
12
DCS_EN_B
13
9
AUDIO_OUT
13
50
12
8
EXT_MIC
47
7
1, 3
16, 17
18, 19
2
SW_RF ( EXT ANT )
AUDIO_IN
RS232_RX
RS232_TX
UPLINK
DWNLINK
23
BLK_CNTL
DP_EN
D
W
N
L
IN
K
_
A
U
D
U
P
L
IN
K
_
A
U
D
uBGA
C
L
K
_
A
U
D
F
S
_
A
U
D
D
W
N
L
IN
K
_
A
U
D
U
P
L
IN
K
_
A
U
D
C
L
K
_
A
U
D
F
S
_
A
U
D
Flexprint Conn.
EXT / Butt Plug Conn.
MIC Conn.
RTC_BATT
10
VIB_DRIVE
9
DWNLINK
UPLINK
MAN_TEST
L275
*RESET
*RESET
30
*
R
E
S
E
T
*RESET
T
H
E
R
M
D
A
C
_
O
U
T
17
1
58
14
47
B
A
T
T
_
S
E
N
S
E
B+_SENSE
4
RS232
SWITCH MATRIX
SCI_RX
SCI_TX
RS232_RX
RS232_TX
BATT_SER_DATA
45
49
U900
GCAP
26
27
29
28
23
22
21
98
63
64
65
62
14
15
39
40
38
10
9
1
3
99
11
2
100
4
16
12
20
RX_ACQ
MDM_INT
TX_KEY
MDM_RD
MDM_WR
DM_CS
SPI_RFCS
SPI_MISO
SPI_MOSI
SPI_SCK
SPI_DATA
SPI_CLK
AFC
AOC
DET_SW
SAT_DET
CLK13_IN
ROM1_CS
ROM2_CS
RAM1_CS
RAM2_CS
MDM_RD
MDM_WR
SPI_CLK
SPI_MISO
SPI_MOSI
SPI_RFCS
MDM_INT
BIC_INT
SP_INT
RF_START
RX_ACQ
*DM_CS
TX_KEY
to SMOC
TX_EN
RX_EN
TX_ON_OFF
M
F
_
IN
T
2
1
7
H
z
B
IC
_
IN
T
L275
R275
POWER UP DEBUG
Tie watchdog as shown in Signal Flow diagram, and supply power to radio:
- Check that there is B+ present at input to FCAP on pin 40. If not, could be problem with Battery Charger Circuitry (Q901)
- FCAP should then drive R275, L275 and VRef. If these are not present, could be a problem with FCAP itself.
- Verify collectors of regulators Q221 and Q222 are both around 2.75V.
- If ok, then check that the SMOC drives he Xtal Varactor Diode CR201 on the AFC line with a DC Voltage.
- If ok, then follow 13MHz path through GIF SYN & BIC and then to uP and SMOC.
- If ok, then check chip enables on Eprom, and SRams.
- If ok, then verify Reset Line.
Follows soon
Summary of Contents for StarTAC130
Page 1: ...StarTAC130 GSM The World s Leading Cellular Telephone Manufacturer Service Manual ...
Page 2: ...GSM StarTAC130 PERSONAL CELLULAR TELEPHONE Service Manual Ver 1 0 ...
Page 9: ...Service Manual 2 2 3 99 StarTAC130 CELLULAR TELEPHONE PAGE INTENTIONALLY BLANK ...
Page 11: ...Service Manual 4 2 3 99 StarTAC130 CELLULAR TELEPHONE PAGE INTENTIONALLY BLANK ...
Page 13: ...Service Manual 6 2 3 99 StarTAC130 CELLULAR TELEPHONE PAGE INTENTIONALLY BLANK ...
Page 25: ...Service Manual 18 2 3 99 StarTAC130 CELLULAR TELEPHONE 2 1 3 4 5 6 7 8 9 10 11 ...
Page 27: ...Service Manual 20 2 3 99 StarTAC130 CELLULAR TELEPHONE PAGE INTENTIONALLY BLANK ...
Page 60: ...Page 31 MOTOROLA CONFIDENTIAL PROPRIETARY GSM Krunch Level 3 Procedure vers 1 1 03 05 1999 ...
Page 69: ...Page 40 MOTOROLA CONFIDENTIAL PROPRIETARY GSM Krunch Level 3 Procedure vers 1 1 03 05 1999 ...
Page 70: ...Page 41 MOTOROLA CONFIDENTIAL PROPRIETARY GSM Krunch Level 3 Procedure vers 1 1 03 05 1999 ...
Page 71: ...Page 42 MOTOROLA CONFIDENTIAL PROPRIETARY GSM Krunch Level 3 Procedure vers 1 1 03 05 1999 ...
Page 83: ......