Motorola StarTAC130, Service Manual

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- MOTOROLA CONFIDENTIAL PROPRIETARY -
GSM Krunch - Level 3 Procedure vers.1.1
03/05/1999
RESET SEQUENCE AT POWER ON
The power up RESET sequence is described in the following diagram. Following the activation of the
+2.75V Regulator, the GCAP LITE IC and the 68338 begin a seven state power sequence involving the
*RESET line and the GCAP Lite’s Watchdog input. The figure below depicts the sequence of the states.
The figure is not drawn to scale.
State 1
When the GCAP LITE IC detects a power on request (ON/OFF Line ”LOW”), the GCAP LITE will drive
the system *RESET line low. The 68338 Clock line will take approximately 100mS to stabilize after power
is applied.
State 2
The 68338, SMoC, and BIC in the radio are connected to the *RESET line. The nominal time *RESET is
held low by the GCAP LITE is 250 millis/- 50 ms.
State 3
When the GCAP LITE releases *RESET, it is pulled high by an internal resistor. There isa period of
approximately 500 nanoseconds when neither the GCAP LITE or 68338 is asserting *RESET.
State 4
When the 68338 reset control logic detects that the system *RESET line is no longer being driven, it drives
it low for an additional 512 cycles (39.6 microseconds). This assertion of *RESET by the 68338 is a feature
of the IC and cannot be modified.
State 5
When the 68338 releases *RESET, it is pulled high by the internal resistor. The 68338 be-gins executing its
Boot Code. If valid code is present, the RESET vector in the radio code is then executed. The Boot Code
runs for about 512 cycles (39.6usec) before this new vector is executed.
State 6
The 68338 holds *RESET low for 50usec during this state (an internally generated RE-SET).
State 7
When the 68338 releases *RESET, it is again pulled high by the internal resistor. All the processors in the
system, including the 68338, then begin execution. During this state, the 68338 must drive the GCAP Lite’s