VMEbus Interface
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VMEbus Interface
The VMEbus interface is provided by the Tsi148 ASIC. Refer to the
Tsi148 User’s Manual available from Tundra Semiconductor for
additional information as listed in
Appendix C, Related Documentation
.
2eSST operations are not supported on 3-row backplanes. You must use
VME64x (VITA 1.5) compatible backplanes, such as 5-row backplanes, to
achieve maximum VMEbus performance.
PMCspan Interface
The MVME6100 provides a PCI expansion connector to add more PMC
interfaces than the two on the MVME6100 board. The PMCspan interface
is provided through the PCI6520 PCIx/PCIx bridge.
Flash Memory
The MVME6100 contains two banks of flash memory accessed via the
device controller bus contained within the MV64360 device. Both banks
are soldered on board and have different write-protection schemes.
System Memory
MVME6100 system memory consists of double-data-rate SDRAMs. The
DDR SDRAMs support two data transfers per clock cycle. The memory
device is a standard monolithic (32M x 8 or 64M x 8) DDR, 8-bit wide, 66-
pin, TSSOPII package. Both banks are provided on board the MVME6100
and operate at 133 MHz clock frequency with both banks populated.
Asynchronous Serial Ports
The MVME6100 board contains one EXAR ST16C554D quad UART
(QUART) device connected to the MV64360 device controller bus to
provide asynchronous debug ports. The QUART supports up to four
asynchronous serial ports, two of which are used on the MVME6100.
