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Functional Description

4

IDSEL Routing

PCI device configuration registers are accessed by using the IDSEL signal 
of each PCI agent to an A/D signal as defined in version 2.2 of the PCI 
specification. IDSEL assignments to on-board resources are specified in 
the MVME6100 Programmer’s Guide.

Reset Control Logic

The sources of reset on the MVME6100 are the following:

❏

Powerup

❏

Reset Switch

❏

NVRAM Watchdog Timer

❏

MV64360 Watchdog Timer

❏

VMEbus controller – Tsi148 ASIC

❏

System Control register bit

❏

PCI Bus 0 reset via System Control register

❏

PCI Bus 1 reset via System Control register

Debug Support

The MVME6100 provides JTAG/COP headers for debug capability for 
Processor as well as PCI0 bus use. These connectors are not populated as 
factory build configuration.

Processor JTAG/COP Headers

The MVME6100 provides JTAG/COP connectors for JTAG/COP 
emulator support (RISCWatch COP J42), as well as supporting board 
boundary scan capabilities (Boundary Scan header J8).

Summary of Contents for MVME6100

Page 1: ...MVME6100 Single Board Computer Installation and Use V6100A IH1 June 2004 Edition ...

Page 2: ...ted in the United States of America Motorola and the stylized M logo are trademarks of Motorola Inc registered in the U S Patent and Trademark Office All other product or service names mentioned in this document are the property of their respective owners ...

Page 3: ...the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power ...

Page 4: ...losion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Attention Caution Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du même type ou d un type équivalent recommandé par le constr...

Page 5: ...nd Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment this product tested to Equipment Class A EN55024 Information technology equipment Immunity characteristics Limits and methods of measurement Board products are tested in a representative system to show compliance with the above mentioned requirements A proper installation in a CE marked system will ...

Page 6: ...ola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Limited and Restricted Rights Legend If the docu...

Page 7: ...lection Headers J10 J15 J18 J25 J28 1 8 Front Rear Ethernet and Transition Module Options Header J30 1 9 SROM Configuration Switch S3 1 10 Flash Boot Bank Select Configuration Switch S4 1 11 Hardware Installation 1 12 Installing the MVME6100 into a Chassis 1 12 Connection to Peripherals 1 13 Completing the Installation 1 14 CHAPTER 2 Startup and Operation Introduction 2 1 Applying Power 2 1 Switch...

Page 8: ...nd Safe Start 3 20 Firmware Startup Sequence Following Reset 3 20 Firmware Scan for Boot Image 3 21 Valid Boot Images 3 23 Checksum Algorithm 3 24 MOTLoad Image Flags 3 24 USER Images 3 25 Alternate Boot Data Structure 3 26 CHAPTER 4 Functional Description Features 4 1 Block Diagram 4 3 Processor 4 3 L3 Cache 4 4 System Controller 4 4 CPU Bus Interface 4 5 Memory Controller Interface 4 5 Device Co...

Page 9: ...5 1 Connectors 5 1 PMC Expansion Connector J4 5 1 Gigabit Ethernet Connectors J9 J93 5 5 PCI Mezzanine Card PMC Connectors J11 J14 J21 J24 5 6 COM1 Connector J19 5 18 VMEbus P1 Connector 5 18 VMEBus P2 Connector PMC Mode 5 20 VMEbus P2 Connector IPMC Mode 5 23 Headers 5 26 SCON Header J7 5 26 Boundary Scan Header J8 5 27 PMC IPMC Selection Headers J10 J15 J18 J25 J28 5 27 COM2 Header J29 5 28 Fron...

Page 10: ...nent Temperature Measurement B 5 Preparation B 5 Measuring Junction Temperature B 5 Measuring Case Temperature B 5 Measuring Local Air Temperature B 8 APPENDIX C Related Documentation Motorola Computer Group Documents C 1 Manufacturers Documents C 2 Related Specifications C 5 ...

Page 11: ...ock Diagram 4 3 Figure B 1 Thermally Significant Components Primary Side B 3 Figure B 2 Thermally Significant Components Secondary Side B 4 Figure B 3 Mounting a Thermocouple Under a Heatsink B 7 Figure B 4 Measuring Local Air Temperature B 8 List of Figures ...

Page 12: ... 10 Table 5 7 PMC Slot 2 Connector J21 Pin Assignments 5 12 Table 5 8 PMC Slot 2 Connector J22 Pin Assignments 5 13 Table 5 9 PMC Slot 2 Connector J23 Pin Assignments 5 15 Table 5 10 PMC Slot 2 Connector J24 Pin Assignments 5 16 Table 5 11 COM1 Connector J19 Pin Assignments 5 18 Table 5 12 VMEbus P1 Connector Pin Assignments 5 18 Table 5 13 VMEbus P2 Connector Pin Assignments PMC Mode 5 20 Table 5...

Page 13: ...able A 2 MVME6100 Specifications A 2 Table B 1 Thermally Significant Components B 2 Table C 1 Motorola Computer Group Documents C 1 Table C 2 Manufacturers Documents C 2 Table C 3 Related Specifications C 5 ...

Page 14: ...able to the board As of the printing date of this manual the MVME6100 supports the models listed below Model Number Description MVME6100 0161 1 267 GHz MPC7457 processor 512MB DDR memory 128MB Flash Scanbe handles MVME6100 0163 1 267 GHz MPC7457 processor 512MB DDR memory 128MB Flash IEEE handles MVME6100 0171 1 267 GHz MPC7457 processor 1GB DDR memory 128MB Flash Scanbe handles MVME6100 0173 1 26...

Page 15: ...TLoad firmware product Chapter 4 Functional Description describes the MVME6100 on a block diagram level Chapter 5 Pin Assignments provides pin assignments for various headers and connectors on the MMVE6100 single board computer Appendix A Specifications provides power requirements and environmental specifications Appendix B Thermal Validation provides information to conduct thermal evaluations and...

Page 16: ... tell how you used it Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements Conventions Used in This Manual The following typographical conventions are used in this document bold is used for user input that you type just as it appears it is also used for commands options and arguments to commands and names of programs directories and files italic is...

Page 17: ...xviii Enter Return or CR represents the carriage return or Enter key Ctrl represents the Control key Execute control characters by pressing the Ctrl key and the letter simultaneously for example Ctrl d ...

Page 18: ...s shipped with one additional asynchronous serial port routed to an on board header The MVME6100 contains two IEEE1386 1 PCI PCI X capable mezzanine card slots The PMC slots are 64 bit capable and support both front and rear I O All I O pins of PMC slot 1 and 46 I O pins of PMC slot 2 are routed to the 5 row DIN P2 connector I O pins 1 through 64 from J14 of PMC slot 1 are routed to row C and row ...

Page 19: ...figured for Ethernet port 2 to the front panel non specific transition module and PMC slot 1 in IPMC mode The board can be configured to route Ethernet port 2 to P2 and support MVME712M or MVME761 transition modules The front rear Ethernet and transition module options are configured by jumper block J30 Selection of PMC slot 1 in PMC or IPMC mode is done by the jumper blocks J10 J15 J18 and J25 J2...

Page 20: ... Overview of Startup Procedures The following table lists the things you will need to do before you can use this board and tells where to find the information you need to perform each step Be sure to read this entire chapter including all Caution and Warning notes before you begin Table 1 1 Startup Overview What you need to do Refer to Unpack the hardware Unpacking Guidelines on page 1 4 Configure...

Page 21: ...a system Electronic components such as disk drives computer boards and memory modules can be extremely sensitive to electrostatic discharge ESD After removing the component from its protective wrapper or from the system place the component flat on a grounded static free surface and in the case of a board component side up Do not slide the component over any surface If an ESD station is not availab...

Page 22: ... registers after the board is installed in a system Jumpers switches are used to control those options that are not software configurable These jumper settings are described further on in this section If you are resetting the board jumpers from their default settings it is important to verify that all settings are reset properly MVME6100 Preparation Figure 1 1 illustrates the placement of the jump...

Page 23: ...J10 J15 J18 J25 J28 PMC IPMC Selection Headers Jumper installed 1 2 2 3 PMC I O IPMC I O for IPMC7xx support default J30 Front Rear Ethernet and Transition Module Options Header Refer to Front Rear Ethernet and Transition Module Options Header J30 on page 1 9 for details S3 SROM Configuration Switch sets board Geographical Address Refer to SROM Configuration Switch S3 on page 1 10 for details S4 F...

Page 24: ...1 Figure 1 1 MVME6100 Layout 4296 0604 10 100 1000 DEBUG ABT RST LAN 1 LAN 2 J42 J8 J30 J3 J19 J13 J14 J11 J12 J23 J24 J21 J22 P1 P2 PCI MEZZANINE CARD PCI MEZZANINE CARD J4 U12 10 100 1000 J93 J9 J29 J7 PMC IPMC U32 S2 1 2 3 4 5 6 7 8 1 2 3 4 1 2 3 4 5 6 7 8 S4 S1 S3 ...

Page 25: ...abled No jumper installed configures for auto SCON PMC IPMC Selection Headers J10 J15 J18 J25 J28 Nine 3 pin planar headers are for PMC IPMC mode I O selection for PMC slot 1 These nine headers can also be combined into one single header block where a block shunt can be used as a jumper A jumper installed across pins 1 and 2 on all nine headers selects PMC1 for PMC I O mode A jumper across pins 2 ...

Page 26: ...pins 3 10 enable P2 rear Gigabit Ethernet Only when front Ethernet is enabled can the jumpers be installed across Row C and Row D on pins 1 10 to enable P2 rear PMC I O Note that all jumpers must be installed across the same two rows all between Row A and Row B and or Row C and Row D or all between Row B and Row C J10 1 2 3 PMC1 P2 I O for PMC Mode J16 1 2 3 J15 1 2 3 J17 1 2 3 J18 1 2 3 J25 1 2 3...

Page 27: ...ROM Init switch is OFF to disable the MV64360 device initialization via the I2C SROM The switch is ON to enable this sequence The SROM WP switch is OFF to enable write protection on all I2C The switch is ON to disable the I2 C EEPROM write protection 4294 0604 1 11 21 31 10 20 30 40 Front Ethernet Default 1 11 21 31 10 20 30 40 Rear Ethernet 1 11 21 31 10 20 30 40 Non Specific Transition Module De...

Page 28: ...d on the board to control Flash Bank B Boot block write protect and Flash Bank A write protect Select the Flash Boot bank and the programmed safe start ENV settings Note It is recommended that Bank B Write Protect always be enabled The Bank B Boot WP switch is OFF to indicate that the Flash Bank B Boot block is write protected The switch is ON to indicate no write protection of Bank B Boot block T...

Page 29: ... default settings Hardware Installation Installing the MVME6100 into a Chassis Use the following steps to install the MVME6100 into your computer chassis 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to an electrical ground refer to Unpacking Guidelines The ESD Table 1 4 Configuration Switch S4 POSITION 4 3 2 1 FUNCTION BANK B BOOT WP BANK A WP BOOT BANK SEL SAFE START ...

Page 30: ... board malfunction 4 Ensure that the levers of the two injector ejectors are in the outward position 5 Slide the MVME6100 into the chassis until resistance is felt 6 Simultaneously move the injector ejector levers in an inward direction 7 Verify that the MVME6100 is properly seated and secure it to the chassis using the two screws located adjacent to the injector ejector levers 8 Connect the appro...

Page 31: ...talled and the power peripheral cables connected are appropriate for your system configuration Replace the chassis or system cover reconnect the system to the AC or DC power source and turn the equipment power on Table 1 5 MVME6100 Connectors Connector Function J3 IPMC761 712 connector J4 PMC expansion connector J9 J93 Gigabit Ethernet connectors J11 J12 J13 J14 PCI mezzanine card PMC slot 1 conne...

Page 32: ...ing up the MVME6100 brings up the MOTLoad prompt MVME6100 Switches and Indicators The MVME6100 board provides a single pushbutton switch that provides both abort and reset ABT RST functions When the switch is depressed for less than three seconds an abort interrupt is generated to the processor If the switch is held for more than three seconds a board hard reset is generated The board hard reset w...

Page 33: ...ware or other software to indicate a configuration problem or other failure CPU connected to a CPU bus control signal to indicate bus transfer activity The following table describes these indicators Table 2 1 Front Panel LED Status Indicators Function Label Color Description CPU Bus Activity CPU Green CPU bus is busy Board Fail BDFAIL Yellow Board has a failure ...

Page 34: ...a vehicle from which user applications can be booted A secondary function of the MOTLoad firmware is to serve in some respects as a test suite providing individual tests for certain devices MOTLoad is controlled through an easy to use UNIX like command line interface The MOTLoad software package is similar to many end user applications designed for the embedded market such as the real time operati...

Page 35: ...in some way that is they do something useful From the perspective of MOTLoad examples of utility applications are configuration data status displays data manipulation help routines data status monitors etc Operationally MOTLoad utility applications differ from MOTLoad test applications in several ways Only one utility application operates at any given time that is multiple utility applications can...

Page 36: ...vice path string it is not supported by MOTLoad and can not be directly tested There are a few exceptions to the device path string requirement like testing RAM which is not considered a true device and can be directly tested without a device path string Refer to the devShow command description page in the MOTLoad Firmware Package User s Manual Most MOTLoad tests can be organized to execute as a g...

Page 37: ...Load then performs the specified action An example of a MOTLoad command line prompt is shown below The MOTLoad prompt changes according to what product it is used on for example MVME5500 MVME6100 Example MVME6100 If an invalid MOTLoad command is entered at the MOTLoad command line prompt MOTLoad displays a message that the command was not found Example MVME6100 mytest mytest not found MVME6100 If ...

Page 38: ...mand string cannot be resolved to a single unique command MOTLoad will inform the user that the command was ambiguous Example MVME6100 te te ambiguous MVME6100 Command Line Help Each MOTLoad firmware package has an extensive product specific help facility that can be accessed through the help command The user can enter help at the MOTLoad command line to display a complete listing of all available...

Page 39: ...MVME6100 Command Line Rules There are a few things to remember when entering a MOTLoad command Multiple commands are permitted on a single command line provided they are separated by a single semicolon Spaces separate the various fields on the command line command arguments options The argument option identifier character is always preceded by a hyphen character Options are identified by a single ...

Page 40: ...bdTempShow Display Current Board Temperature bfb bfh bfw Block Fill Byte Halfword Word blkCp Block Copy blkFmt Block Format blkRd Block Read blkShow Block Show Device Configuration Data blkVe Block Verify blkWr Block Write bmb bmh bmw Block Move Byte Halfword Word br Assign Delete Display User Program Break Points bsb bsh bsw Block Search Byte Halfword Word bvb bvh bvw Block Verify Byte Halfword W...

Page 41: ...gram Flash Memory Program flashShow Display Flash Memory Device Configuration Data gd Go Execute User Program Direct Ignore Break Points gevDelete Global Environment Variable Delete gevDump Global Environment Variable s Dump NVRAM Header Data gevEdit Global Environment Variable Edit gevInit Global Environment Variable Area Initialize NVRAM Header gevList Global Environment Variable Labels Names Li...

Page 42: ...hutdown Network Interface netStats Display Network Interface Statistics Data noCm Turns off Concurrent Mode pciDataRd Read PCI Device Configuration Header Register pciDataWr Write PCI Device Configuration Header Register pciDump Dump PCI Device Configuration Header Register pciShow Display PCI Device Configuration Header Register pciSpace Display PCI Device Address Space Allocation ping Ping Netwo...

Page 43: ...amRd NVRAM Read testNvramRdWr NVRAM Read Write Destructive testRam RAM Test Directory testRamAddr RAM Addressing testRamAlt RAM Alternating testRamBitToggle RAM Bit Toggle testRamBounce RAM Bounce testRamCodeCopy RAM Code Copy and Execute testRamEccMonitor Monitor for ECC Errors testRamMarch RAM March testRamPatterns RAM Patterns testRamPerm RAM Permutations testRamQuick RAM Quick testRamRandom RA...

Page 44: ...Thermometer Temp Limit Quick Test testThermoRange Tests That Board Thermometer is Within Range testWatchdogTimer Tests the Accuracy of the Watchdog Timer Device tftpGet TFTP Get tftpPut TFTP Put time Display Date and Time transparentMode Transparent Mode Connect to Host tsShow Display Task Status upLoad Up Load Binary Data from Target version Display Version String s vmeCfg Manages user specified ...

Page 45: ...Related Documentation MVME6100 vmeCfg s m Displaying the selected Default VME Setting interpreted as follows VME PCI Master Enable Y N Y MVME6100 The PCI Master is enabled MVME6100 vmeCfg s r234 Displaying the selected Default VME Setting interpreted as follows VMEbus Master Control Register 00000003 MVME6100 The VMEbus Master Control Register is set to the default RESET condition MVME6100 vmeCfg ...

Page 46: ...d to 2eSST 2eVME MBLT and BLT cycles A32 address space respond to Supervisor User Program and Data cycles Image maps from 0x00000000 to 0x1FFF0000 on the VMbus translates 1x1 to the PCI X bus thus 1x1 to local memory To enable this window set bit 31 of ITAT0 to 1 Note For Inbound Translations the Upper Translation Offset Register needs to be set to 0xFFFFFFFF to ensure proper translations to the P...

Page 47: ...0000000 Outbound Image 2 Translation Offset Lower Register 40000000 Outbound Image 2 2eSST Broadcast Select Register 00000000 MVME6100 Outbound window 2 OTAT2 is enabled 2eSST timing at SST320 transfer mode of SCT A24 D32 Supervisory access The window accepts transfers on the PCI X Local Bus from 0xB0000000 0xB0FF0000 and translates them onto the VMEbus using an offset of 0x40000000 thus an access...

Page 48: ...ound Image 7 Starting Address Upper Register 00000000 Outbound Image 7 Starting Address Lower Register B1000000 Outbound Image 7 Ending Address Upper Register 00000000 Outbound Image 7 Ending Address Lower Register B1FF0000 Outbound Image 7 Translation Offset Upper Register 00000000 Outbound Image 7 Translation Offset Lower Register 4F000000 Outbound Image 7 2eSST Broadcast Select Register 0000000...

Page 49: ...e Geographical address that is the VME slot number See the VME64 Specification and the VME64 Extensions for details As a result a 512K byte CR CSR area can be accessed from the VMEbus using the CR CSR AM code Displaying VME Settings To display the changeable VME setting type the following at the firmware prompt vmeCfg s m Displays Master Enable state vmeCfg s i 0 7 Displays selected Inbound Window...

Page 50: ... the following at the firmware prompt vmeCfg e m Edits Master Enable state vmeCfg e i 0 7 Edits selected Inbound Window state vmeCfg e o 0 7 Edits selected Outbound Window state vmeCfg e r184 Edits PCI Miscellaneous Register state vmeCfg e r188 Edits Special PCI Target Image Register state vmeCfg e r400 Edits Master Control Register state vmeCfg e r404 Edits Miscellaneous Control Register state vm...

Page 51: ...Window state vmeCfg d r184 Deletes PCI Miscellaneous Register state vmeCfg d r188 Deletes Special PCI Target Image Register state vmeCfg d r400 Deletes Master Control Register state vmeCfg d r404 Deletes Miscellaneous Control Register state vmeCfg d r40C Deletes User AM Codes Register state vmeCfg d rF70 Deletes VMEbus Register Access Image Control Register state Restoring Default VME Settings To ...

Page 52: ...dress IBCA between the host and the target CR CSR slave addresses configured by MOTLoad are assigned according to the installation slot in the backplane as indicated by the VME64 Specification For reference the following values are provided For further details on CR CSR space please refer to the VME64 Specification listed in Appendix C Related Documentation The MVME6100 uses a Discovery II for its...

Page 53: ...tions The MVME6100 s IBCA needs to be mapped appropriately through the master s VMEbus bridge For example to use remote start using mailbox 0 on an MVME6100 installed in slot 5 the master would need a mapping to support reads and writes of address 0x002ff348 in VME CR CSR space 0x280000 0x7f348 Alternate Boot Images and Safe Start Some later versions of MOTLoad support Alternate Boot Images and a ...

Page 54: ...e Safe Start jumper switch or by sending an ESC to the console serial port within five seconds of the board reset During interactive mode the user has the option to display locations at which valid boot images were discovered specify which discovered image is to be executed or specify that the recovery image in the boot block of the active Flash bank is to be executed Firmware Scan for Boot Image ...

Page 55: ... is an example of an interactive Safe Start ABCDEInteractive Boot Mode Entered boot Interactive boot commands d show directory of alternate boot images c continue with normal startup q quit without executing any alternate boot image r address execute specified or default alternate image p address execute specified or default POST image this help screen h this help screen boot d Addr FFE00000 Size ...

Page 56: ...mage keys and other sanity checks A valid boot image begins with a structure as defined in the following table Name Type Size Notes UserDefined unsigned integer 8 User defined ImageKey 1 unsigned integer 1 0x414c5420 ImageKey 2 unsigned integer 1 0x424f4f54 ImageChecksum unsigned integer 1 Image checksum ImageSize unsigned integer 1 Must be a multiple of 4 ImageName unsigned character 20 User defi...

Page 57: ... implemented using the following code Unsigned int checksum Unsigned int startPtr starting address Unsigned int endPtr ending address unsigned int checksum 0 while startPtr endPtr checksum startPtr startPtr return checksum MOTLoad Image Flags The image flags of the header define various bit options that control how the image will be executed Table 3 2 MOTLoad Image Flags Name Value Interpretation ...

Page 58: ... on self test image This bit flag is used to indicate that the image is a diagnostic and should be run prior to running either USER or MCG boot images POST images are expected but not required to return to the boot block code upon completion DONT_AUTO_RUN If set this flag indicates that the image is not to be selected for automatic execution A user through the interactive command facility may spec...

Page 59: ...ltBootData_t Alternate Boot Data Structure The globalData field of the alternate boot data structure points to an area of RAM which was initialized to zeroes by the boot loader This area of RAM is not cleared by the boot loader after execution of a POST image or other alternate boot image is executed It is intended to provide a user a mechanism to pass POST image results to subsequent boot images ...

Page 60: ...Alternate Boot Data Structure http www motorola com computer literature 3 27 3 state that the board was in at POST entry USER images should not return control to the boot loader ...

Page 61: ...ed by processor Up to 2MB using DDR SRAM Flash Two banks A B of soldered Intel StrataFlash devices 8 to 64MB supported on each bank Boot bank is switch selectable between banks Bank A has combination of software and hardware write protect scheme Bank B top 1MB block can be write protected through software hardware write protect control System Memory Two banks on board for up to 1Gb using 256Mb or ...

Page 62: ...r I O as specified by IEEE P1386 33 66 MHz PCI or 66 100 MHz PCI X VME Interface Tsi148 VME 2eSST ASIC provides Eight programmable VMEbus map decoders A16 A24 A32 and A64 address 8 bit 16 bit and 32 bit single cycle data transfers 8 bit 16 bit 32 bit and 64 bit block transfers Supports SCT BLT MBLT 2eVME and 2eSST protocols 8 entry command and 4KB data write post buffer 4KB read ahead buffer PMCsp...

Page 63: ...the board The MPC7457 has integrated L1 and L2 caches as the factory build configuration and supports an L3 cache interface with on chip tags to support up to 2MB of off chip cache 2 5V signal levels are used on the processor bus 64 bit 33 66 100 MHz PCI X L3 Cache 2MB MPC7457 1 267 GHz 211 MHz DDR 133 MHz Processor Bus 133 MHz Memory Bus RTC NVRAM VME TSI148 Soldered Flash Bank A 64MB 64 bit 133 ...

Page 64: ...the L3CR register Refer to the PowerPC Apollo Microprocessor Implementation Definition Book IV listed in Appendix C Related Documentation System Controller The MV64360 is an integrated system controller for high performance embedded control applications The following features of the MV64360 are supported by the MVME6100 The MV64360 has a five bus architecture comprised of A 72 bit interface to the...

Page 65: ...cessor There are 21 address windows supported in the CPU interface Four for SDRAM chip selects Five for device chip selects Five for the PCI_0 interface four memory one I O Five for the PCI_1 interface four memory one I O One for the MV64360 integrated SRAM One for the MV64360 internal registers space Each window is defined by base and size registers and can decode up to 4GB space except for the i...

Page 66: ...C cache coherency between CPU L1 L2 caches and DRAM Device Controller Interface The device controller supports up to five banks of devices three of which are used for Flash Banks A and B NVRAM RTC Each bank supports up to 512MB of address space resulting in total device space of 1 5GB Serial ports are the fourth and fifth devices on the MVME6100 Each bank has its own parameters register as shown i...

Page 67: ...b s full duplex Ethernet ports connected to the front panel via the MV64360 system controller Ethernet access is provided by front panel RJ 45 connectors with integrated magnetics and LEDs Port 1 is a dedicated Gigabit Ethernet port while a configuration header is provided for port 2 front or rear P2 access Refer to Front Rear Ethernet and Transition Module Options Header J30 for more information ...

Page 68: ...software behavior After the watchdog timer is enabled it becomes a free running counter that must be serviced periodically to keep it from expiring Refer to the MV64360 Data Sheet listed in Appendix C Related Documentation for additional information and programming details I2O Message Unit I2O compliant messaging for the MVME6100 board is provided by an I2O messaging unit integrated into the MV643...

Page 69: ...nal registers In the second function the controller is used by the system software to read the contents of the VPD EEPROM contained on the MVME6100 board along with the SPD EEPROMs for on board memory to further initialize the memory controller and other interfaces The MVME6100 board contains the following I2 C serial devices 8KB EEPROM for user defined MV64360 initialization 8KB EEPROM for VPD 8K...

Page 70: ...s refer to the MVME6100 Programmer s Guide PCI Bus Arbitration PCI arbitration is performed by the MV64360 system controller The MV64360 integrates two PCI arbiters one for each PCI interface PCI bus 0 1 Each arbiter can handle up to six external agents plus one internal agent PCI bus 0 1 master The internal PCI arbiter REQ GNT signals are multiplexed on the MV64360 MPP pins The internal PCI arbit...

Page 71: ...Ix bridge Flash Memory The MVME6100 contains two banks of flash memory accessed via the device controller bus contained within the MV64360 device Both banks are soldered on board and have different write protection schemes System Memory MVME6100 system memory consists of double data rate SDRAMs The DDR SDRAMs support two data transfers per clock cycle The memory device is a standard monolithic 32M...

Page 72: ...MVME6100 board supports two PMC slots Two sets of four EIA E700 AAAB connectors are located on the MVME6100 board to interface to the 32 bit 64 bit IEEE P1386 1 PMC to add any desirable function The PMC slots are PCI PCI X 33 66 100 capable PMC IPMC slot 1 supports PMC slot 2 supports Mezzanine Type PMC IPMC PCI Mezzanine Card Mezzanine Size S1B Single width and standard depth 75mm x 150mm with fr...

Page 73: ... Real Time Clock NVRAM Watchdog Timer The real time clock NVRAM watchdog timer is implemented using an integrated SGS Thompson M48T37V Timekeeper SRAM and Snaphat battery The minimum M48T37V watchdog timer time out resolution is 62 5 msec 1 16s and maximum time out period is 124 seconds The interface for the Timekeeper and SRAM is connected to the MV64360 device controller bus on the MVME6100 boar...

Page 74: ...the following Powerup Reset Switch NVRAM Watchdog Timer MV64360 Watchdog Timer VMEbus controller Tsi148 ASIC System Control register bit PCI Bus 0 reset via System Control register PCI Bus 1 reset via System Control register Debug Support The MVME6100 provides JTAG COP headers for debug capability for Processor as well as PCI0 bus use These connectors are not populated as factory build configurati...

Page 75: ...onnector VMEbus P2 Connector IPMC Mode The following headers are described in this chapter SCON Header J7 Boundary Scan Header J8 PMC IPMC Selection Headers J10 J15 J18 J25 J28 COM2 Header J29 Front Rear Ethernet and Transition Module Options Header J30 Processor JTAG COP Header J42 Connectors PMC Expansion Connector J4 One 114 pin Mictor connector with a center row of power and ground pins is use...

Page 76: ...al Pin 1 3 3V GND 3 3V 2 3 PCICLK PMCINTA 4 5 GND PMCINTB 6 7 PURST PMCINTC 8 9 HRESET PMCINTD 10 11 TDO TDI 12 13 TMS TCK 14 15 TRST PCIXP 16 17 PCIXGNT PCIXREQ 18 19 12V 12V 20 21 PERR SERR 22 23 LOCK SDONE 24 25 DEVSEL SBO 26 27 GND GND 28 29 TRDY IRDY 30 31 STOP FRAME 32 33 GND M66EN 34 35 ACK64 Reserved 36 37 REQ64 Reserved 38 ...

Page 77: ... 45 AD1 AD0 46 47 AD3 AD2 48 49 AD5 AD4 50 51 AD7 AD6 52 53 AD9 AD8 54 55 AD11 AD10 56 57 AD13 AD12 58 59 AD15 AD14 60 61 AD17 AD16 62 63 AD19 AD18 64 65 AD21 AD20 66 67 AD23 AD22 68 69 AD25 AD24 70 71 AD27 AD26 72 73 AD29 AD28 74 75 AD31 AD30 76 Table 5 1 PMC Expansion Connector J4 Pin Assignments continued Pin Signal Signal Pin ...

Page 78: ...80 81 C BE7 C BE6 82 83 AD33 AD32 84 85 AD35 AD34 86 87 AD37 AD36 88 89 AD39 AD38 90 91 AD41 AD40 92 93 AD43 AD42 94 95 AD45 AD44 96 97 AD47 AD46 98 99 AD49 AD48 100 101 AD51 AD50 102 103 AD53 AD52 104 105 AD55 AD54 106 107 AD57 AD56 108 109 AD59 AD58 110 111 AD61 AD60 112 113 AD63 AD62 114 Table 5 1 PMC Expansion Connector J4 Pin Assignments continued Pin Signal Signal Pin ...

Page 79: ...the connector is connected to PHY BCM5421S 2 DS1 and DS2 signals are controlled by the on board Reset PLD Table 5 2 Gigabit Ethernet Connectors J9 J93 Pin Assignment Pin Signal 1000 Mb s 10 100 Mb s 1 CT_BOARD 2 5V 2 5V 2 MDIO0 B1_DA 1 TD 3 MDIO0 B1_DA TD 4 MDIO1 B1_DB RD 5 MDIO1 B1_DC Not Used 6 MDIO2 B1 DC Not Used 7 MDIO2 B1_DB RD 8 MDIO3 B1_DD Not Used 9 MDIO3 B1_DD Not Used 10 CT_CONNECTOR GN...

Page 80: ...24 contain the signals that go to VME P2 I O rows A C D and Z The pin assignments for these connectors are as follows Table 5 3 PMC Slot 1 Connector J11 Pin Assignments Pin Signal Signal Pin 1 TCK 12V 2 3 GND INTA 4 5 INTB INTC 6 7 PMCPRSNT1 5V 8 9 INTD PCI_RSVD 10 11 GND 3 3Vaux 12 13 CLK GND 14 15 GND PMCGNT1 16 17 PMCREQ1 5V 18 19 3 3V VIO AD31 20 21 AD28 AD27 22 23 AD25 GND 24 25 GND C BE3 26 ...

Page 81: ...48 49 AD09 5V 50 51 GND C BE0 52 53 AD06 AD05 54 55 AD04 GND 56 57 3 3V VIO AD03 58 59 AD02 AD01 60 61 AD00 5V 62 63 GND REQ64 64 Table 5 4 PMC Slot 1 Connector J12 Pin Assignments Pin Signal Signal Pin 1 12V TRST 2 3 TMS TDO 4 5 TDI GND 6 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull up 3 3V 12 13 RST Pull down 14 Table 5 3 PMC Slot 1 Connector J11 Pin Assignments continued Pin Signal Signal Pi...

Page 82: ... GND 30 31 AD16 C BE2 32 33 GND IDSEL1B 34 35 TRDY 3 3V 36 37 GND STOP 38 39 PERR GND 40 41 3 3V SERR 42 43 C BE1 GND 44 45 AD14 AD13 46 47 M66EN AD10 48 49 AD08 3 3V 50 51 AD07 REQ1B 52 53 3 3V GNT1B 54 55 Not Used GND 56 57 Not Used EREADY0 58 59 GND Not Used 60 61 ACK64 3 3V 62 63 GND No Connect MONARCH 64 Table 5 4 PMC Slot 1 Connector J12 Pin Assignments continued Pin Signal Signal Pin ...

Page 83: ...ND 2 3 GND C BE7 4 5 C BE6 C BE5 6 7 C BE4 GND 8 9 3 3V VIO PAR64 10 11 AD63 AD62 12 13 AD61 GND 14 15 GND AD60 16 17 AD59 AD58 18 19 AD57 GND 20 21 3 3V VIO AD56 22 23 AD55 AD54 24 25 AD53 GND 26 27 GND AD52 28 29 AD51 AD50 30 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 3 3V VIO AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 ...

Page 84: ...C2 PMC0_4 P2 A2 4 5 PMC0_5 P2 C3 PMC0_6 P2 A3 6 7 PMC0_7 P2 C4 PMC0_8 P2 A4 8 9 PMC1 _9 P2 C5 PMC0_10 P2 A5 10 11 PMC0_11 P2 C6 PMC0_12 P2 A6 12 13 PMC0_13 P2 C7 PMC0_14 P2 A7 14 15 PMC0_15 P2 C8 PMC0_16 P2 A8 16 17 PMC0_17 P2 C9 PMC0_18 P2 A9 18 19 PMC0_19 P2 C10 PMC0_20 P2 A10 20 21 PMC0_21 P2 C11 PMC0_22 P2 A11 22 23 PMC0_23 P2 C12 PMC0_24 P2 A12 24 25 PMC0_25 P2 C13 PMC0_26 P2 A13 26 27 PMC0_2...

Page 85: ... 41 PMC0_41 P2 C21 PMC0_42 P2 A21 42 43 PMC0_43 P2 C22 PMC0_44 P2 A22 44 45 PMC0_45 P2 C23 PMC0_46 P2 A23 46 47 PMC0_47 P2 C24 PMC0_48 P2 A24 48 49 PMC0_49 P2 C25 PMC0_50 P2 A25 50 51 PMC0_51 P2 C26 PMC0_52 P2 A26 52 53 PMC0_53 P2 C27 PMC0_54 P2 A27 54 55 PMC0_55 P2 C28 PMC0_56 P2 A28 56 57 PMC0_57 P2 C29 PMC0_58 P2 A29 58 59 PMC0_59 P2 C30 PMC0_60 P2 A30 60 61 PMC0_61 P2 C31 PMC0_62 P2 A31 62 63 ...

Page 86: ...TA 6 7 PMCPRSNT1 5V 8 9 INTB PCI_RSVD 10 11 GND 3 3Vaux 12 13 CLK GND 14 15 GND PMCGNT1 16 17 PMCREQ1 5V 18 19 3 3V VIO AD31 20 21 AD28 AD27 22 23 AD25 GND 24 25 GND C BE3 26 27 AD22 AD21 28 29 AD19 5V 30 31 3 3V VIO AD17 32 33 FRAME GND 34 35 GND IRDY 36 37 DEVSEL 5V 38 39 GND LOCK 40 41 PCI_RSVD PCI_RSVD 42 43 PAR GND 44 45 3 3V VIO AD15 46 47 AD12 AD11 48 49 AD09 5V 50 ...

Page 87: ...D REQ64 64 Table 5 8 PMC Slot 2 Connector J22 Pin Assignments Pin Signal Signal Pin 1 12V TRST 2 3 TMS TDO 4 5 TDI GND 6 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull up 3 3V 12 13 RST Pull down 14 15 3 3V Pull down 16 17 Not Used GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 3 3V 24 25 IDSEL1 AD23 26 27 3 3V AD20 28 Table 5 7 PMC Slot 2 Connector J21 Pin Assignments continued Pin Signal Signal ...

Page 88: ...7 GND STOP 38 39 PERR GND 40 41 3 3V SERR 42 43 C BE1 GND 44 45 AD14 AD13 46 47 M66EN AD10 48 49 AD08 3 3V 50 51 AD07 REQ1B 52 53 3 3V GNT1B 54 55 Not Used GND 56 57 Not Used EREADY1 58 59 GND Not Used 60 61 ACK64 3 3V 62 63 GND No Connect MONARCH 64 Table 5 8 PMC Slot 2 Connector J22 Pin Assignments continued Pin Signal Signal Pin ...

Page 89: ...ND 2 3 GND C BE7 4 5 C BE6 C BE5 6 7 C BE4 GND 8 9 3 3V VIO PAR64 10 11 AD63 AD62 12 13 AD61 GND 14 15 GND AD60 16 17 AD59 AD58 18 19 AD57 GND 20 21 3 3V VIO AD56 22 23 AD55 AD54 24 25 AD53 GND 26 27 GND AD52 28 29 AD51 AD50 30 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 3 3V VIO AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 ...

Page 90: ...2 PMC1_4 P2 D3 4 5 PMC1_5 P2 Z3 PMC1_6 P2 D4 6 7 PMC1_7 P2 D5 PMC1_8 P2 Z5 8 9 PMC1_9 P2 D6 PMC1_10 P2 D7 10 11 PMC1_11 P2 Z7 PMC1_12 P2 D8 12 13 PMC1_13 P2 D9 PMC1_14 P2 Z9 14 15 PMC1_15 P2 D10 PMC1_16 P2 D11 16 17 PMC1_17 P2 Z11 PMC1_18 P2 D12 18 19 PMC1_19 P2 D13 PMC1_20 P2 Z13 20 21 PMC1_21 P2 D14 PMC1_22 P2 D15 22 23 PMC1_23 P2 Z15 PMC1_24 P2 D16 24 25 PMC1_25 P2 D17 PMC1_26 P2 Z17 26 27 PMC1...

Page 91: ... PMC1_38 P2 Z25 38 39 PMC1_39 P2 D26 PMC1_40 P2 D27 40 41 PMC1_41 P2 Z27 PMC1_42 P2 D28 42 43 PMC1_43 P2 D29 PMC1_44 P2 Z29 44 45 PMC1_45 P2 D30 PMC1_46 P2 Z31 46 47 Not Used Not Used 48 49 Not Used Not Used 50 51 Not Used Not Used 52 53 Not Used Not Used 54 55 Not Used Not Used 56 57 Not Used Not Used 58 59 Not Used Not Used 60 61 Not Used Not Used 62 63 Not Used Not Used 64 Table 5 10 PMC Slot 2...

Page 92: ...r is an 160 pin DIN The P1 connector provides power and VME signals for 24 bit address and 16 bit data The pin assignments for the P1 connector is as follows Table 5 11 COM1 Connector J19 Pin Assignments Pin Signal 1 DCD 2 RTS 3 GNDC 4 TX 5 RX 6 GNDC 7 CTS 8 DTR Table 5 12 VMEbus P1 Connector Pin Assignments ROW Z ROW A ROW B ROW C ROW D 1 Reserved D00 BBSY D08 Reserved 1 2 GND D01 BCLR D09 Reserv...

Page 93: ...eserved 14 15 Reserved GND BR3 A23 Reserved 15 16 GND DTACK AM0 A22 Reserved 16 17 Reserved GND AM1 A21 Reserved 17 18 GND AS AM2 A20 Reserved 18 19 Reserved GND AM3 A19 Reserved 19 20 GND IACK GND A18 Reserved 20 21 Reserved IACKIN SERA A17 Reserved 21 22 GND IACKOUT SERB A16 Reserved 22 23 Reserved AM4 GND A15 Reserved 23 24 GND A07 IRQ7 A14 Reserved 24 25 Reserved A06 IRQ6 A13 Reserved 25 26 GN...

Page 94: ...2 GND 5V 5V 5V Reserved 32 Table 5 12 VMEbus P1 Connector Pin Assignments continued ROW Z ROW A ROW B ROW C ROW D Table 5 13 VMEbus P2 Connector Pin Assignments PMC Mode ROW Z ROW A ROW B ROW C ROW D 1 PMC1_2 J24 2 PMC0_2 J14 2 5V P2_IO_GLAN1_ MDIO_1 PMC1_1 J24 1 1 2 GND PMC0_4 J14 4 GND P2_IO_GLAN1_ MDIO_1 PMC1_3 J24 3 2 3 PMC1_5 J4 5 PMC0_6 J14 6 RETRY P2_IO_GLAN1_ MDIO_0 PMC1_4 J24 4 3 4 GND PM...

Page 95: ...PMC0_28 J14 28 VD16 PMC0_27 J14 27 PMC1_21 J24 21 14 15 PMC1_23 J24 J23 PMC0_30 J14 30 VD17 PMC0_29 J14 29 PMC1_22 J24 22 15 16 GND PMC0_32 J14 32 VD18 PMC0_31 J14 31 PMC1_24 J24 24 16 17 PMC1_26 J24 J26 PMC0_34 J14 34 VD19 PMC0_33 J14 33 PMC1_25 J24 25 17 18 GND PMC0_36 J14 36 VD20 PMC0_35 J14 35 PMC1_27 J24 27 18 19 PMC1_29 J24 29 PMC0_38 J14 38 VD21 PMC0_37 J14 37 PMC1_28 J24 28 19 20 GND PMC0_...

Page 96: ...26 GND PMC0_52 J14 52 VD27 PMC0_51 J14 51 PMC1_39 J24 39 26 27 P2_IO_GLAN1_ MDIO_2 PMC0_54 J14 54 VD28 PMC0_53 J14 53 TXB PMC1_40 J24 40 27 28 GND PMC0_56 J14 56 VD29 PMC0_55 J14 55 RXB PMC1_42 J24 42 28 29 P2_IO_GLAN1_ MDIO_3 PMC0_58 J14 58 VD30 PMC0_57 J14 57 RTSB PMC1_43 J24 43 29 30 GND PMC0_60 J14 60 VD31 PMC0_59 J14 59 CTSB PMC1_45 J24 45 30 31 P2_IO_GLAN1_ MDIO_3 PMC0_62 J14 62 GND PMC0_61 ...

Page 97: ... PMC2_5 DB2 N C TD PMC2_4 J24 4 4 GND DB3 VA24 TD PMC2_6 J24 6 5 PMC2_8 DB4 VA25 NOT USED PMC2_7 J24 7 6 GND DB5 VA26 NOT USED PMC2_9 J24 9 7 PMC2_11 DB6 VA27 12V LAN PMC2_10 J24 10 8 GND DB7 VA28 PRSTB PMC2_12 J24 12 9 PMC2 14 DBP VA29 P DB0 PMC2_13 J24 13 10 GND ATN VA30 P DB1 PMC2_15 J24 15 11 PMC2_17 BSY VA31 P DB2 PMC2_16 J24 16 12 GND ACK GND P DB3 PMC2_18 J24 18 13 PMC2_20 RST 5V P DB4 PMC2...

Page 98: ...43 J24 43 30 GND DTR4 VD31 CTS2 PMC2_45 J24 45 31 PMC2_46 J24 46 DCD4 GND DTR2 GND 32 GND RTXC4 5V DCD2 VPC Table 5 15 VME P2 Connector Pinouts with IPMC761 Pin Row Z Row A Row B Row C Row D 1 DB8 DB0 5V RD 10 100 PMC2_1 J24 1 2 GND DB1 GND RD 10 100 PMC2_3 J24 3 3 DB9 DB2 RETRY TD 10 100 PMC2_4 J24 4 4 GND DB3 VA24 TD 10 100 PMC2_6 J24 6 5 DB10 DB4 VA25 Not Used PMC2_7 J24 7 6 GND DB5 VA26 Not Us...

Page 99: ...C2_27 J24 27 19 PMC2_29 J24 29 AFD VD21 PRPE PMC2_28 J24 28 20 GND SLIN VD22 PRSEL PMC2_30 J24 30 21 PMC2_32 J24 32 TXD3 VD23 INIT PMC2_31 J24 31 22 GND RXD3 GND PRFLT PMC2_33 J24 33 23 PMC2_35 J24 35 RTXC3 VD24 TXD1_232 PMC2_34 J24 34 24 GND TRXC3 VD25 RXD1_232 PMC2_36 J24 36 25 PMC2_38 J24 38 TXD4 VD26 RTS1_232 PMC2_37 J24 37 26 GND RXD4 VD27 CTS1_232 PMC2_39 J24 39 27 PMC2_41 J24 41 RTXC4 VD28 ...

Page 100: ... pins 1 and 2 configures for SCON always enabled A jumper installed across pins 2 and 3 configures for SCON disabled No jumper installed configures for auto SCON The pin assignments for this connector are as follows 29 PMC2_44 J24 44 VD30 RTS2_232 PMC2_43 J24 43 30 GND 12VF VD31 CTS2_232 PMC2_45 J24 45 31 PMC2_46 J24 46 MSYNC GND MDO GND 32 GND MCLK 5V MDI VPC Table 5 15 VME P2 Connector Pinouts w...

Page 101: ...lso be combined into one single header block where a block shunt can be used as a jumper The pin assignments for these connectors are as follows Table 5 17 Boundary Scan Header J8 Pin Assignments Pin Signal Signal Pin 1 TRST_L GND 2 3 TDO GND 4 5 TDI GND 6 7 TMS GND 8 9 TCLK GND 10 11 NC CPU_BSCAN_L 12 13 AW_L GND 14 Table 5 18 PMC IPMC Configuration Jumper Block Pin Row 1 PMC I O Pin Row 2 P2 Pin...

Page 102: ...configuration The pin assignments for this header are as follows J26 PMC1_IO 17 P2_PMC1_IO 17 IPMC DB13_L J17 PMC1_IO 20 P2_PMC1_IO 20 IPMC DB14_L J10 PMC1_IO 23 P2_PMC1_IO 23 IPMC DB15_L J15 PMC1_IO 26 P2_PMC1_IO 26 IPMC DBP1_L Table 5 18 PMC IPMC Configuration Jumper Block Pin Row 1 PMC I O Pin Row 2 P2 Pins Pin Row 3 IPMC Pins Table 5 19 COM2 Planar Serial Port Header J29 Pin Assignments Pin Si...

Page 103: ...2 Controller Row A To Front Panel Ethernet 1 PMC0_IO 13 P21 _C7 Fused 12V No Connect 2 PMC0_IO 60 P2_A30 Fused 12V No Connect 3 PMC0_IO 7 P2_C4 P2_IO_GLAN1_ MDIO_0 magnetic T22 23 MDI_0P J93 2 4 PMC0_IO 5 P2_C3 P2_IO_GLAN1_ MDIO_0 magnetic T2 22 MDI_0N J9 3 5 PMC0_IO 3 P2_C2 P2_IO_GLAN1_ MDIO_1 magnetic T2 20 MDI_1P J9 4 6 PMC0_IO 1 P2_C1 P2_IO_GLAN1_ MDIO_1 magnetic T2 19 MDI_1N J9 5 7 PMC1_IO 38...

Page 104: ...gnments for this header are as follows Note Some signals are actually resistor buffered versions of the named signal Table 5 21 Processor JTAG COP RISCWatch Header J42 Pin Assignments Pin Signal Signal Pin 1 CPU_TDO CPU_QACK_L 2 3 CPU_TDI CPU_TRST_L 4 5 CPU_QREQ_L PU CPU_VIO 6 7 CPU_TCK OPT PU CPU_VIO 8 9 CPU_TMS NC 10 11 CPU_SRST_L OPTPD_GND 12 13 CPU_HRST_L KEY no pin 14 15 CPU_CKSTPO_L GND 16 ...

Page 105: ... 1 provides an estimate of the typical and maximum current required from each of the input supply voltages Note In a 3 row chassis PMC current should be limited to 19 8 watts total of both PMC slots In a 5 row chassis PMC current should be limited to 46 2 watts total of both PMC slots Table A 1 Power Requirements Model Power MVME6100 0163 Typical 42W 5V Maximum 51W 5V MVME6100 0163 with IPMC712 76...

Page 106: ...e of forced air cooling is recommended for operation in the upper temperature range Storage Temperature 40 to 70 C or 40 to 158 F Relative Humidity Operating 5 to 90 non condensing Non operating 5 to 90 non condensing Vibration Non operating 1 G sine sweep 5 100 Hz horizontal and vertical NEBS1 Physical Dimensions 6U 4HP wide 233 mm x 160 mm x 20 mm 9 2 in x 6 3 in x 0 8 in MTBF 328 698 hours calc...

Page 107: ...onfiguration It identifies thermally significant components and lists the corresponding maximum allowable component operating temperatures It also provides example procedures for component level temperature measurements Thermally Significant Components The following table summarizes components that exhibit significant temperature rises These are the components that should be monitored in order to ...

Page 108: ...nt Components Reference Designator Generic Description Max Allowable Component Temperature deg C Measurement Location U3 U11 U64 U72 DDR SDRAM 70 Air U84 U95 Gigabit Ethernet Transceiver 129 Case U82 U83 Cache 115 Case U45 U46 Programmable Logic Device 70 Air U32 PCI Bridge 70 Air U20 Discovery II 110 Case U15 Clock Generator 85 Air U14 U22 Clock Buffer 85 Air U12 MC7457RX 1 267 GHz Processor 103 ...

Page 109: ...ificant Components Primary Side 4248 0504 10 100 1000 DEBUG ABT RST LAN 2 LAN 1 J42 J8 J30 U20 J3 J19 J13 J14 J11 J12 J23 J24 J21 J22 P1 P2 U21 PCI MEZZANINE CARD PCI MEZZANINE CARD J4 U12 10 100 1000 J93 J9 J29 U1 J7 PMC IPMC U32 U7 U6 U5 U3 U4 U11 U10 U9 U8 U13 U18 U14 U15 U22 U30 U19 U17 U16 U23 U27 U25 ...

Page 110: ...B 4 Computer Group Literature Center Web Site Thermal Validation B Figure B 2 Thermally Significant Components Secondary Side 4292 0504 U46 U45 U68 U67 U66 U64 U65 U72 U71 U70 U69 U83 U82 U95 U84 ...

Page 111: ...een reached Measuring Junction Temperature Some components have an on chip thermal measuring device such as a thermal diode For instructions on measuring temperatures using the on board device refer to the component manufacturer s documentation listed in Appendix C Related Documentation Measuring Case Temperature Measure the case temperature at the center of the top of the component Make sure ther...

Page 112: ...ion B Note Machining a heatsink base reduces the contact area between the heatsink and the electrical component You can partially compensate for this effect by filling the machined areas with thermal grease The grease should not contact the thermocouple junction ...

Page 113: ...NK BOTTOM VIEW ISOMETRIC VIEW Machined groove for thermocouple wire routing Thermocouple junction bonded to component Heatsink base Thermal pad Through hole for thermocouple junction clearance may require removal of fin material Also use for alignment guidance during heatsink installation Machined groove for thermocouple wire routing ...

Page 114: ...rature by placing the thermocouple downstream of the component This method is conservative since it includes heating of the air by the component The following figure illustrates one method of mounting the thermocouple Figure B 4 Measuring Local Air Temperature Thermocouple junction PWB Tape thermocouple wire to top of component Air flow ...

Page 115: ... literature site http www motorola com computer literature To obtain the most up to date product information in PDF or HTML format visit http www motorola com computer literature Table C 1 Motorola Computer Group Documents Document Title Motorola Publication Number MVME6100Single BoardComputerProgrammer s Reference Guide V6100A PG MOTLoad Firmware Package User s Manual MOTLODA UM IPMC712 761 I O M...

Page 116: ...47 FAX 602 994 6430 or 303 675 2150 Web Site http e www motorola com webapp sps library prod_lib jsp E mail ldcformotorola hibbertco com MPC7457EC D Rev 1 3 3 2003 Tsi148 PCI X to VME Bus Bridge User Manual Tundra Semiconductor Corporation 603 March Road Ottawa Ontario Canada K2K 2M5 Web Site www tundra com 80A3020_MA001_02 PowerPC Apollo Microprocessor Implementation Definition Book IV Literature...

Page 117: ...11 8141 Web Site http developer intel com design flcomp datashts 290737 htm 290737 PCI6520 HB7 Transparent PCIx PCIx Bridge Preliminary Data Book PLX Technology Inc 870 Maude Avenue Sunnyvale California 94085 Web Site http www hintcorp com products hint default asp PCI6520 Ver 0 992 EXAR ST16C554 554D ST68C554 Quad UART with 16 Byte FIFOs EXAR Corporation 48720 Kato Road Fremont CA 94538 Web Site ...

Page 118: ...M48T37V 2 Wire Serial CMOS EEPROM Atmel Corporation San Jose CA Web Site http www atmel com atmel support AT24C02N AT24C64A Dallas Semiconductor DS1621Digital Thermometer and Thermostat Dallas Semiconductor Web Site http www dalsemi com DS1621 TSOP Type I Shielded Metal Cover SMT Yamaichi Electronics USA Web Site http www yeu com Table C 2 Manufacturers Documents continued Document Title and Sourc...

Page 119: ...rce Publication Number VITA http www vita com VME64 Specification ANSI VITA 1 1994 VME64 Extensions ANSI VITA 1 1 1997 2eSST Source Synchronous Transfer VITA 1 5 199x PCI Special Interest Group PCI SIG http www pcisig com Peripheral Component Interconnect PCI Local Bus Specification Revision 2 0 2 1 2 2 PCI Local Bus Specification PCI X Addendum to the PCI Local Bus Specification Rev 1 0b IEEE htt...

Page 120: ...fault VME settings 3 12 delete 3 18 display 3 16 edit 3 17 restore 3 18 delete VME settings 3 18 dimensions A 2 display VME settings 3 16 documentation related C 1 E edit VME settings 3 17 environmental specifications A 2 ESD precautions 1 4 evaluating thermal performance B 1 F features hardware 4 1 firmware command utility 3 16 Flash memory 4 11 G GT 64260A CPU bus interface 4 5 I2C serial interf...

Page 121: ... operating temperatures maximum B 1 P physical dimensions A 2 power requirements A 1 power apply 2 1 processor 4 3 R related documentation C 1 relative humidity A 2 remote start 3 19 restore VME settings 3 18 S settings VME 3 12 specifications A 2 startup overview 1 3 suggestions submitting xvii switch abort reset 2 1 system controller 4 4 CPU bus interface 4 5 I2C serial interface devices 4 9 int...

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