4-6
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Functional Description
4
supports single-bit and double-bit error detection and single-bit error
correction of all SDRAM reads and writes.
The SDRAM controller supports a wide range of SDRAM timing
parameters. These parameters can be configured through the SDRAM
Mode register and the SDRAM Timing Parameters register. Refer to the
MV64360 Data Sheet, listed in
Appendix C, Related Documentation
, for
additional information and programming details.
The DRAM controller contains four transaction queues—two write buffers
and two read buffers. The DRAM controller does not necessarily issue
DRAM transactions in the same order that it receives the transactions. The
MV64360 is targeted to support full PowerPC cache coherency between
CPU L1/L2 caches and DRAM.
Device Controller Interface
The device controller supports up to five banks of devices, three of which
are used for Flash Banks A and B, NVRAM/RTC. Each bank supports up
to 512MB of address space, resulting in total device space of 1.5GB. Serial
ports are the fourth and fifth devices on the MVME6100. Each bank has its
own parameters register as shown in the following table.
PCI/PCI-X Interfaces
The MVME6100 provides two 32/64-bit PCI/PCI-X buses, operating at a
maximum frequency of 100 MHz when configured to PCI-X mode, and
run at 33 or 66 MHz when running conventional PCI mode. PCI bus 1 is
connected to the PMC slots 1 and 2.
Table 4-2. Device Bus Parameters
Flash Bank A
Device Bus Bank 0
Bank width 32-bit, parity disabled
Flash Bank B
Device Bus Boot Bank
Bank width 32-bit, parity disabled
Real-Time Clock
Serial Ports
Board Specific Registers
Device Bus Bank 1
Bank width 8-bit, parity disabled