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Hardware Preparation

MVME167/D3

2-5

2

SRAM Backup Power Source Select Header J8

Header J8 is an optional header that is used to select the power source used to back up
the SRAM on the MVME167, if the optional battery and circuitry is present.

C

aution

Do not remove all jumpers from J8. This may disable the
SRAM.
If your board contains the optional header J8, but the optional
battery is removed, jumpers must be installed on J8 between
pins 2 and 4, as shown in the Backup Power Disabled drawing
above.

J8

4

1

3

5V STBY

(Factory Configuration, when

Optional Battery Is Present)

Optional Battery

J8

J8

2

4

1

3

2

4

1

3

2

Backup Power Disabled

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Summary of Contents for MVME167 Series

Page 1: ...nderutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Ready to ship TAR certified secure asset solutions Expert team I Trust guarantee I 100 satisfaction All trademarks brand names and brands appearing herein are the property of their respective ow...

Page 2: ...MVME167 Single Board Computer User s Manual Character User Interface ...

Page 3: ......

Page 4: ...uction 2 1 Unpacking Instructions 2 1 Hardware Preparation 2 1 General Purpose Readable Jumpers on Header J1 2 2 System Controller Header J2 2 2 Serial Port 4 Clock Configuration Select Headers J6 and J7 2 4 SRAM Backup Power Source Select Header J8 2 5 Installation Instructions 2 6 MVME167 Module Installation 2 6 System Considerations 2 7 CHAPTER 3 OPERATING INSTRUCTIONS Introduction 3 1 Controls...

Page 5: ...ctional Description 4 1 Data Bus Structure 4 1 MC68040 MPU 4 2 EPROM 4 2 SRAM 4 2 Onboard DRAM 4 3 Battery Backed Up RAM and Clock 4 4 VMEbus Interface 4 4 I O Interfaces 4 5 Serial Port Interface 4 5 Parallel Port Interface 4 6 Ethernet Interface 4 6 SCSI Interface 4 7 SCSI Termination 4 7 Local Resources 4 7 Programmable Tick Timers 4 7 Watchdog Timer 4 8 Software Programmable Hardware Interrupt...

Page 6: ...ix APPENDIX A EIA 232 D INTERCONNECTIONS Introduction A 1 Levels of Implementation A 3 Signal Adaptations A 3 Sample Configurations A 4 Proper Grounding A 6 ...

Page 7: ...x ...

Page 8: ... LEDs 2 3 Figure 4 1 MVME167 Main Module Block Diagram 4 11 Figure 4 2 Parity DRAM Mezzanine Module Block Diagram 4 12 Figure 4 3 ECC DRAM Mezzanine Module Block Diagram 4 13 Figure A 1 Middle of the Road EIA 232 D Configuration A 4 Figure A 2 Minimum EIA 232 D Connection A 5 ...

Page 9: ...xii ...

Page 10: ...Table 3 5 Printer Memory Map 3 16 Table 3 6 MEMC040 Internal Register Memory Map 3 17 Table 3 7 MCECC Internal Register Memory Map 3 17 Table 3 8 Cirrus Logic CD2401 Serial Port Memory Map 3 19 Table 3 9 82596CA Ethernet LAN Memory Map 3 23 Table 3 10 53C710 SCSI Memory Map 3 24 Table 3 11 MK48T08 BBRAM TOD Clock Memory Map 3 25 Table 3 12 BBRAM Configuration Area Memory Map 3 25 Table 3 13 TOD Cl...

Page 11: ...xiv ...

Page 12: ...ons Model Number Speed Major Differences MVME167 001B was MVME167 01or 001A 25MHz 4MBOnboard ParityDRAM MVME167 002B was MVME167 02or 002A 25MHz 8MBOnboard ParityDRAM MVME167 003B was MVME167 03or 003A 25MHz 16MBOnboard Parity DRAM MVME167 004B was MVME167 04or 004A 25MHz 32MBOnboard Parity DRAM MVME167 031B was MVME167 31 or 031A 33MHz 4MBOnboard ECCDRAM MVME167 032B was MVME167 32 or 032A 33MHz ...

Page 13: ...y 8 RAM and time of day clock with battery backup RESET and ABORT switches Four 32 bit tick timers for periodic interrupts Watchdog timer Eight software interrupts I O SCSI Bus interface with DMA Four serial ports with EIA 232 D buffers with DMA Centronics printer port Ethernet transceiver interface with DMA VMEbus interface VMEbus system controller functions VMEbus interface to local bus A24 A32 ...

Page 14: ...incoming air temperature is measured between the fan assembly and the card cage where the incoming airstream first encounters the module under test Test software is executed as the module is subjected to ambient temperature variations Case temperatures of critical high power density integrated circuits are monitored to ensure component vendors specifications are not exceeded While the exact amount...

Page 15: ...s Specifications Power requirements with all four EPROM sockets populated and excluding external LAN transceiver 5 Vdc 5 3 5 A typical 4 5 A max at 25 MHz with 32MB parity DRAM 5 0 A typical 6 5 A max at 33 MHz with 128MB ECC DRAM 12 Vdc 5 100 mA max 1 0 A max with offboard LAN transceiver 12 Vdc 5 100 mA max Operating temperature refer to Cooling Requirements section 0 to 55 C at point of entry o...

Page 16: ...ts the transition boards MVME712 12 MVME712 13 MVME712M MVME712A MVME712AM and MVME712B referred to in this manual as MVME712X unless separately specified The MVME712X transition boards provide configuration headers and provide industry standard connectors for the I O devices The VMEbus interface is provided by an ASIC called the VMEchip2 The VMEchip2 includes two tick timers a watchdog timer prog...

Page 17: ...sembler 167Bug includes a user interface which accepts commands from the system console terminal 167Bug can also operate in a System Mode which includes choices from a service menu Refer to the MVME167Bug Debugging Package User s Manual and the Debugging Package for Motorola 68K CISC CPUs User s Manual for details The MVME712X series of transition modules provide the interface between the MVME167 ...

Page 18: ... bears the same number as a manual but has a suffix such as D2A1 the first supplement to the second edition of the manual Document Title Motorola Publication Number MVME167 Single Board Computer Support Information Refer to Support Information on page 1 8 SIMVME167 MVME167Bug Debugging Package User s Manual MVME167BUG Debugging Package for Motorola 68K CISC CPUs User s Manual 68KBUG Single Board C...

Page 19: ...r 542400 003 Cirrus Logic Inc 3100 West Warren Ave Fremont CA 94538 82596CA Local Area Network Coprocessor Data Sheet order number 290218 and 82596 User s Manual order number 296853 Intel Corporation Literature Sales P O Box 58130 Santa Clara CA 95052 8130 NCR 53C710 SCSI I O Processor Data Manual order number NCR53C710DM and NCR 53C710 SCSI I O Processor Programmer s Guide order number NCR53C710P...

Page 20: ...high to low transition In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation an negate indicate a signal that is inactive or false These terms are used independently of the voltage level high or low that they represent Data and address sizes are defined as follows A byte ...

Page 21: ...General Information 1 10 MVME167 Single Board Computer User s Manual 1 ...

Page 22: ...sure proper operation of the MVME167 certain option modifications may be necessary before installation The MVME167 provides software control for most of these options Some options can not be done in software so are done by jumpers on headers Most other modifications are done by setting bits in control registers after the MVME167 has been installed in a system The MVME167 registers are described in...

Page 23: ...F40088 in the VMEchip2 LCSR The bit values are read as a one when the jumper is off and as a zero when the jumper is on System Controller Header J2 The MVME167 can be VMEbus system controller The system controller function is enabled disabled by jumpers on header J2 When the MVME167 is system controller the SCON LED is turned on The VMEchip2 may be configured as a system controller as follows J1 2...

Page 24: ... P2 A32 B32 C32 A1 B1 C1 19 20 J3 DS1 1 2 HALT FAIL RUN SCON LAN SCSI VME ABORT RESET J2 F2 J8 1 16 2 1 15 12V XU4 SKT 39 40 1 2 29 28 6 7 18 17 XU3 SKT 39 40 1 29 28 6 7 18 17 XU2 39 40 1 29 28 6 7 18 17 XU1 39 40 1 29 28 6 7 18 17 1 1 3 3 J6 J7 COMPONENTS ARE REMOVED FOR CLARITY 60 59 2 1 J4 60 59 2 1 J5 MEZZANINE BOARD DS2 DS3 DS4 2 2 2 1 2 J1 2 3 4 OPTIONAL ...

Page 25: ...l port 4 to drive or receive RTXC4 and TRXC4 respectively Factory configuration is with port 4 set to receive both signals The remaining configuration of the clock lines is accomplished using the Serial Port 4 Clock Configuration Select header on the MVME712M transition module Refer to the MVME712M Transition Module and MVME147P2 Adapter Board User s Manual for configuration of that header Receive...

Page 26: ...d circuitry is present Caution Do not remove all jumpers from J8 This may disable the SRAM If your board contains the optional header J8 but the optional battery is removed jumpers must be installed on J8 between pins 2 and 4 as shown in the Backup Power Disabled drawing above J8 4 1 3 VMEbus 5V STBY Factory Configuration when Optional Battery Is Present Optional Battery J8 J8 2 4 1 3 2 4 1 3 2 Ba...

Page 27: ... s from the appropriate card slot s at the front and rear of the chassis if the chassis has a rear card cage The MVME167 module requires power from both P1 and P2 It may be installed in any double height unused card slot if it is not configured as system controller If the MVME167 is configured as system controller it must be installed in the leftmost card slot slot 1 to correctly initiate the bus ...

Page 28: ...ata for 32 bit transfers and for the upper 8 address lines for extended addressing mode The MVME167 may not operate properly without its main board connected to P1 and P2 of the VMEbus backplane Whether the MVME167 operates as a VMEbus master or as a VMEbus slave it is configured for 32 bits of address and for 32 bits of data A32 D32 However it handles A16 or A24 devices in the address ranges indi...

Page 29: ...rnet LAN transceiver interface through a 1 amp fuse F2 located on the MVME167 module The 12V LED lights when 12 Vdc is available The fuse is socketed and located near diode CR1 If the Ethernet transceiver fails to operate check the fuse When using the MVME712M module the yellow LED DS1 on the MVME712M front panel lights when LAN power is available indicating that the fuse is good The MVME167 provi...

Page 30: ...nd drives SYSRESET if the board is system controller The RESET switch may be disabled by software The VMEchip2 includes both a global and a local reset driver When the chip operates as the VMEbus system controller the reset driver provides a global system reset by asserting the VMEbus signal SYSRESET A SYSRESET may be generated by the RESET switch a power up reset a watchdog timeout or by a contro...

Page 31: ...ng a local bus cycle The green SCON LED part of DS2 lights when the VMEchip2 in the MVME167 is the VMEbus system controller The green LAN LED part of DS3 lights when the LAN chip is local bus master The MVME167 supplies 12V power to the Ethernet transceiver interface through a fuse The green 12V LAN power LED part of DS3 lights when power is available to the transceiver interface The green SCSI LE...

Page 32: ...ss Range The memory map of devices that respond to the normal address range is shown in the following tables The normal address range is defined by the Transfer Type TT signals on the local bus On the MVME167 Transfer Types 0 1 and 2 define the normal address range Table 3 1 Local Bus Memory Map is the entire map from 00000000 to FFFFFFFF Many areas of the map are user programmable and suggested u...

Page 33: ...s are programmed in the VMEchip2 3 Size is approximate 4 Cache inhibit depends on devices in area mapped 5 This area is not decoded If these locations are accessed and the local bus timer is enabled the cycle times out and is terminated by a TEA signal Table 3 1 Local Bus Memory Map Address Range Devices Accessed Port Size Size Software Cache Inhibit Notes 00000000 DRAMSIZE User Programmable Onboa...

Page 34: ...FFF40200 FFF40FFF reserved 3 5KB 5 7 FFF41000 FFF41FFF reserved 4KB 5 FFF42000 FFF42FFF PCCchip2 D32 D8 4KB 1 FFF43000 FFF430FF MEMC040 MCECC 1 D8 256B 1 FFF43100 FFF431FF MEMC040 MCECC 2 D8 256B 1 FFF43200 FFF43FFF MEMC040s MCECCs repeated 3 5KB 1 7 FFF44000 FFF44FFF reserved 4KB 5 FFF45000 FFF451FF CD2401 Serial Comm Cont D16 D8 512B 1 9 FFF45200 FFF45DFF reserved 3KB 7 9 FFF45E00 FFF45FFF reser...

Page 35: ... area does return an acknowledge signal 7 Size is approximate 8 Port commands to the 82596CA must be written as two 16 bit writes upper word first and lower word second 9 The CD2401 appears repeatedly from FFF45200 to FFF45FFF on the MVME167 If the local bus timer is enabled the access times out and is terminated by a TEA signal Detailed I O Memory Maps Tables 3 3 through 3 13 give the detailed me...

Page 36: ...Memory Maps MVME167 D3 3 7 3 This page intentionally left blank ...

Page 37: ...NG ADDRESS 4 MASTER ADDRESS TRANSLATION ADDRESS 4 VMEchip2 LCSR Base Address FFF40000 OFFSET 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MAST D16 EN MAST WP EN MAST D16 EN MAST WP EN MASTER AM 3 MASTER AM 4 GCSR GROUP SELECT GCSR BOARD SELECT MAST 4 EN MAST 3 EN MAST 2 EN MAST 1 EN TICK 2 1 TICK IRQ...

Page 38: ...SLATION SELECT 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IO2 EN IO2 WP EN IO2 S U IO2 P D IO1 EN IO1 D16 EN IO1 WP EN IO1 S U 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MASTER AM 2 MASTER AM 1 ROM SIZE ROM BANK B SPEED ROM BANK A SPEED DMA TBL INT DMA LB SNP MODE DMA INC VME DMA INC LB DMA D64 BLK DMA BLK DMA AM 5 DMA AM 4 DMA WRT DMA D16 DMA AM 3 DMA AM 2 DMA AM 1 D...

Page 39: ...Q PE IRQ IRQ1E IRQ TIC2 IRQ TIC1 IRQ VME IACK IRQ DMA IRQ SIG3 IRQ SIG2 IRQ SIG1 IRQ SIG0 IRQ LM1 IRQ LM0 IRQ ABORT IRQ LEVEL SYS FAIL IRQ LEVEL MST WP ERROR IRQ LEVEL VME IACK IRQ LEVEL DMA IRQ LEVEL SIG 3 IRQ LEVEL SIG 2 IRQ LEVEL SW7 IRQ LEVEL SW6 IRQ LEVEL SW5 IRQ LEVEL SW4 IRQ LEVEL SPARE IRQ LEVEL VME IRQ 7 IRQ LEVEL VME IRQ 6 IRQ LEVEL VME IRQ 5 IRQ LEVEL VECTOR BASE REGISTER 0 VECTOR BASE ...

Page 40: ...2 CLR IRQ 11 CLR IRQ 10 CLR IRQ 9 CLR IRQ 8 SET IRQ 15 SET IRQ 14 SET IRQ 13 SET IRQ 12 SET IRQ 11 SET IRQ 10 SET IRQ 9 SET IRQ 8 SW7 IRQ SW6 IRQ SW5 IRQ SW4 IRQ SW3 IRQ SW2 IRQ SW1 IRQ SW0 IRQ SPARE VME IRQ7 VME IRQ6 VME IRQ5 VME IRQ4 VME IRQ3 VME IRQ2 VME IRQ1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GPIOO P ERROR IRQ LEVEL IRQ1E IRQ LEVEL TIC TIMER 2 IRQ LEVEL TIC TIMER 1 IRQ LEVEL SW3 IRQ LEVEL S...

Page 41: ...Operating Instructions 3 12 MVME167 Single Board Computer User s Manual 3 This page intentionally left blank ...

Page 42: ...VISION CHIP ID 2 4 LM3 LM2 LM1 LM0 SIG3 SIG2 SIG1 SIG0 RST ISF BF SCON SYSFL X X X 4 8 GENERAL PURPOSE CONTROL AND STATUS REGISTER 0 6 C GENERAL PURPOSE CONTROL AND STATUS REGISTER 1 8 10 GENERAL PURPOSE CONTROL AND STATUS REGISTER 2 A 14 GENERAL PURPOSE CONTROL AND STATUS REGISTER 3 C 18 GENERAL PURPOSE CONTROL AND STATUS REGISTER 4 E 1C GENERAL PURPOSE CONTROL AND STATUS REGISTER 5 ...

Page 43: ...GPI PLTY D16 D23 D24 D31 CHIP ID CHIP REVISION TIC TIMER 1 TIC TIMER 1 TIC TIMER 2 TIC TIMER 2 PRESCALER COUNT REGISTER PRESCALER CLOCK ADJUST GPI E L GPI INT GPI IEN GPI ICLR GPI IRQ LEVEL GPI GPOE GPO SCC PAR ERR SCC EXT ERR SCC LTO ERR SCC SCLR SCC MDM ERR SCC MDM IEN SCC MDM AVEC SCC MODEM IRQ LEVEL SCC TRANSMIT PIACK LAN PAR ERR LAN EXT ERR LAN LTO ERR LAN SCLR SCSI PAR ERR SCSI EXT ERR SCSI ...

Page 44: ... TIC2 ICLR TIC1 INT TIC1 IEN TIC1 ICLR SCC TX IRQ SCC TX IEN SCC TX AVEC SCC SC1 SCC SC0 SCC RX IRQ SCC RX IEN SCC RX AVEC SCC MODEM PIACK LAN INT E L LAN INT LAN IEN LAN ICLR LAN INT IRQ LEVEL PRTR SEL PLTY PRTR SEL E L PRTR SEL INT PRTR SEL IEN PRTR SEL ICLR PRTR ANY INT PRTR ACK PRTR FLT PRTR SEL PRTR PE PRTR BSY PRTR SEL IRQ LEVEL PRINTER DATA LAN SC1 LAN SC0 LAN ERR INT LAN ERR IEN LAN ERR IC...

Page 45: ...put Status Register FFF42036 Printer Port Control Register FFF42037 Printer Data Register 16 bits FFF4203A BIT 31 30 29 28 27 26 25 24 NAME PLTY E L INT IEN ICLR IL2 IL1 IL0 BIT 23 22 21 20 19 18 17 16 NAME PLTY E L INT IEN ICLR IL2 IL1 IL0 BIT 15 14 13 12 11 10 9 8 NAME PLTY E L INT IEN ICLR IL2 IL1 IL0 BIT 7 6 5 4 3 2 1 0 NAME PLTY E L INT IEN ICLR IL2 IL1 IL0 BIT 31 30 29 28 27 26 25 24 NAME PL...

Page 46: ...5 BAD24 FFF43118 FFF43018 BAD23 BAD22 DMCTL SWAIT WWP PARINT PAREN RAMEN FFF4311C FFF4301C BCK7 BCK6 BCK5 BCK4 BCK3 BCK2 BCK1 BCK0 Table 3 7 MCECC Internal Register Memory Map MCECC Base Address FFF43000 1st FFF43100 2nd Register Offset Register Name RegisterBitNames D31 D30 D29 D28 D27 D26 D25 D24 00 CHIPID CID7 CID5 CID5 CID4 CID3 CID2 CID1 CID0 04 CHIPREVISION REV7 REV6 REV5 REV4 REV3 REV2 REV1...

Page 47: ...BTIMER ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 4C SCRUBADDRCNTR 0 0 0 0 0 SAC26 SAC25 SAC24 50 SCRUBADDRCNTR SAC23 SAC22 SAC21 SAC20 SAC19 SAC18 SAC17 SAC16 54 SCRUBADDRCNTR SAC15 SAC14 SAC13 SAC12 SAC11 SAC10 SAC9 SAC8 58 SCRUBADDRCNTR SAC7 SAC6 SAC5 SAC4 0 0 0 0 5C ERRORLOGGER ERRLOG ERD ESCRB ERA EALT 0 MBE SBE 60 ERRORADDRESS EA31 EA30E EA29 EA28 EA27 EA26 EA25 EA24 64 ERRORADDRESS EA23 EA22 EA21 EA20...

Page 48: ...l Character Register 1 SCHR1 1F B R W Async Special Character Register 2 SCHR2 1E B R W Async Special Character Register 3 SCHR3 1D B R W Async Special Character Register 4 SCHR4 1C B R W Async Special Character Range low SCRl 23 B R W Async Special Character Range high SCRh 22 B R W Async LNext Character LNXT 2E B R W Async Bit Rate and Clock Option Registers Receive Frame Address Register1 RFAR1...

Page 49: ...E1 B R W Receive Interrupt Register RIR ED B R Receive Interrupt Status Register RISR 88 W NOTE R W Receive Interrupt Status Register low RISRl 89 B R Receive Interrupt Status Register high RISRh 88 B R Receive FIFO Output Count RFOC 30 B R Receive Data Register RDR F8 B R Receive End Of Interrupt Register REOIR 84 B W Transmit Interrupt Registers Transmit Priority Interrupt Level Register TPILR E...

Page 50: ...te Count BRBCNT 48 W R W A Receive Buffer Status ARBSTS 4F B R W B Receive Buffer Status BRBSTS 4E B R W Receive Current Buffer Address Lower RCBADRL 3E W R Receive Current Buffer Address Upper RCBADRU 3C W R DMA Transmit Registers A Transmit Buffer Address Lower ATBADRL 52 W R W A Transmit Buffer Address Upper ATBADRU 50 W R W B Transmit Buffer Address Lower BTBADRL 56 W R W B Transmit Buffer Add...

Page 51: ...e out Period Regis low RTPRl 25 B R W Async Receive Time out Period Register high RTPRh 24 B R W Async General Timer 1 GT1 2A W R Sync General Timer 1 low GT1l 2B B R Sync General Timer 1 high GT1h 2A B R Sync General Timer 2 GT2 29 B R Sync Transmit Timer Register TTR 29 B R Async Table 3 8 Cirrus Logic CD2401 Serial Port Memory Map Continued Base Address FFF45000 Register Description Register Na...

Page 52: ...rite the System Configuration Pointer to the command registers before writing to the MPU Channel Attention register Writes to the System Configuration Pointer must be upper word first lower word second Table 3 9 82596CA Ethernet LAN Memory Map 82596CA Ethernet LAN Directly Accessible Registers Data Bits Address D31 D16 D15 D0 FFF46000 Upper Command Word Lower Command Word FFF46004 MPU Channel Atte...

Page 53: ...e Endian Mode 00 SIEN SDID SCNTL1 SCNTL0 00 04 SOCL SODL SXFER SCID 04 08 SBCL SBDL SIDL SFBR 08 0C SSTAT2 SSTAT1 SSTAT0 DSTAT 0C 10 DSA 10 14 CTEST3 CTEST2 CTEST1 CTEST0 14 18 CTEST7 CTEST6 CTEST5 CTEST4 18 1C TEMP 1C 20 LCRC CTEST8 ISTAT DFIFO 20 24 DCMD DBC 24 28 DNAD 28 2C DSP 2C 30 DSPS 30 34 SCRATCH 34 38 DCNTL DWT DIEN DMODE 38 3C ADDER 3C NOTE Accesses may be 8 bit or 32 bit but not 16 bit...

Page 54: ... Configuration Area Memory Map Address Range Description Size Bytes FFFC1EF8 FFFC1EFB Version 4 FFFC1EFC FFFC1F07 Serial Number 12 FFFC1F08 FFFC1F17 Board ID 16 FFFC1F18 FFFC1F27 PWA 16 FFFC1F28 FFFC1F2B Speed 4 FFFC1F2C FFFC1F31 Ethernet Address 6 FFFC1F32 FFFC1F33 Reserved 2 FFFC1F34 FFFC1F35 SCSI ID 2 FFFC1F36 FFFC1F3D System ID 8 FFFC1F3E FFFC1F45 Mezz Board 1 PWB 8 FFFC1F46 FFFC1F4D Mezz Boar...

Page 55: ... fourth area is used by the MVME167 board debugger MVME167Bug The fifth area detailed in Table 3 12 BBRAM Configuration Area Memory Map on page 3 25 is the configuration area The sixth area the TOD clock detailed in Table 3 13 TOD Clock Memory Map on page 3 26 is defined by the chip hardware The data structure of the configuration bytes starts at FFFC1EF8 and is as follows struct brdi_cnfg char ve...

Page 56: ...iring assembly PWA number assigned to this board in ASCII format This includes the 01 W prefix This is for the main logic board if more than one board is required for a set Additional boards in a set are defined by a structure for that set For example for a 16 MB 25 MHz MVME167 board at revision A the PWA field contains 01 W3899B03A The 12 characters are followed by four blanks 5 Four bytes contai...

Page 57: ...ebugging Package for Motorola 68K CISC CPUs User s Manual for security and data integrity of the configuration area of the NVRAM This data is stored in hexadecimal format Interrupt Acknowledge Map The local bus distinguishes interrupt acknowledge cycles from other cycles by placing the binary value 11 on TT1 TT0 It also specifies the level that is being acknowledged using TM2 TM0 The interrupt han...

Page 58: ...ME167 D3 3 29 3 VMEbus Short I O Memory Map The VMEchip2 includes a user programmable map decoder for the GCSR The GCSR map decoder allows you to program the starting address of the GCSR in the VMEbus short I O space ...

Page 59: ...s a subset of system reset SRST Local reset can be generated five ways expiration of the watchdog timer pressing the front panel RESET switch if the system controller function is disabled by asserting a bit in the board control register in the GCSR by SYSRESET or by powerup reset Note The GCSR allows a VMEbus master to reset the local bus This feature is very dangerous and should be used with caut...

Page 60: ...he functional description of the MVME167 module MVME167 Functional Description The MVME167 is a high functionality VMEbus single board computer designed around the MC68040 chip It has 4 8 16 32 64 128 256MB of dynamic RAM a SCSI mass storage interface four serial ports a printer port and an Ethernet transceiver interface Data Bus Structure The local data bus on the MVME167 is a 32 bit synchronous ...

Page 61: ...MEchip2 and the access time is programmable Refer to the VMEchip2 in the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide for more detail The boards are populated with 100 ns SRAMs SRAM battery backup is optionally available on the MVME167 The battery backup function is provided by a Dallas DS1210S Only one backup power source is supported on the MVME167 Each time the MV...

Page 62: ...ting in injury and or fire When dealing with lithium batteries carefully follow the precautions listed below in order to prevent accidents Do not short circuit Do not disassemble deform or apply excessive pressure Do not heat or incinerate Do not apply solder directly Do not use different models or new and old batteries together Do not charge Always check proper polarity To remove the battery from...

Page 63: ... MK48T08 is an 8 bit device however the interface provided by the PCCchip2 supports 8 16 and 32 bit accesses to the MK48T08 Refer to the PCCchip2 in the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide and to the MK48T08 data sheet for detailed programming information VMEbus Interface The local bus to VMEbus interface the VMEbus to local bus interface and the local VMEbu...

Page 64: ... to the CD2401 must be 8 or 16 bits 32 bit accesses are not permitted Refer to the CD2401 data sheet and to the PCCchip2 in the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide for detailed programming information The CD2401 supports DMA operations to local memory Because the CD2401 does not support a retry operation necessary to break VMEbus lockup conditions the CD2401...

Page 65: ...167 has a different value for XXXXX Each module has an Ethernet Station Address displayed on a label attached to the VMEbus P2 connector In addition the six bytes including the Ethernet address are stored in the configuration area of the BBRAM That is 08003E2XXXXX is stored in the BBRAM At an address of FFFC1F2C the upper four bytes 08003E2X can be read At an address of FFFC1F30 the lower two byte...

Page 66: ...rrupts to the processor Refer to the VMEchip2 and PCCchip2 in the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide for detailed programming information Watchdog Timer A watchdog timer function is provided in the VMEchip2 When the watchdog timer is enabled it must be reset by software within the programmed time or it times out The watchdog timer can be programmed to gener...

Page 67: ... required Burst write cycles require 5 2 1 1 1 bus clock cycles The parity DRAM is organized as four banks this requires the use of 256K by 4 chips for the data portion of the RAM and 256K by 4 chips with the write per bit option for the parity bits The use of four banks allows X 1 1 1 bursts with parity on ROM Cycle Times The ROM cycle time is programmable from 4 to 11 bus clock cycles The data t...

Page 68: ...ansfer rate of the LAN DMA controller is 20 MB sec at 25 MHz with parity off Assuming a continuous transfer rate of 1 MB sec on the LAN bus 5 of the local bus bandwidth is used by transfers from the LAN bus Remote Status and Control The remote status and control connector J3 is a 20 pin connector located behind the front panel of the MVME167 It provides system designers the flexibility to access c...

Page 69: ... REMOTE RESET ABORT LEDS LEDS AND SWITCHES CLOCKS GENERATOR J4 J5 SHEET 7 SHEET 28 SHEET 10 SHEET 9 P4 P5 SHEET 8 J3 SHEET 20 SHEET 21 SHEET 18 LANCE SHEET 19 SERIAL PORT SHEETS 24 26 PRINTER PORTS SHEET 22 SIA SHEET 20 BATTERY BACKUP SHEET 28 SRAMS AND SHEETS 16 17 EPROMS VME BUFFERS SHEETS 13 15 VMECHIP2 SHEET 12 MC68040 MPU SHEET 27 SCSI LAN VME P2 SHEET 6 P1 SHEET 5 BBRAM AND TOD SHEET 23 ...

Page 70: ...ANK A SHEET 8 CONNECTOR SHEET 5 DATA MUX SHEET 13 14 ADDRESS BUS MULTIPLEXED ADDRESS MEMORY ARRAY BANK B SHEET 9 MEMORY ARRAY BANK C SHEET 10 MEMORY ARRAY BANK D SHEET 11 ADDRESS MUX SHEET 7 10887 00 9401 TIMING CONTROL SHEET 6 ACKNOWLEDGE SHEET 15 CONNECTORS SHEET 4 DATA BUS CONTROL RDA BUS RDB BUS RDC BUS RDD BUS PARITY DATA DRAM STROBES ...

Page 71: ...DDDRESS MUX LOWER DATA MUX SHEET 7 UPPER DRAM ARRAY BLOCKS 0 AND 1 SHEET 13 14 LOWER DRAM ARRAY BLOCKS 0 AND 1 SHEET 11 12 CONNECTORS SHEET 4 5 BOARD DEFAULTS SHEET 6 TIMING_CONTROL ADDRESS MUX UPPER DATA MUX SHEET 8 DRAM ADDR CNTRL LOWER DATA 040 LOCAL BUS DRAM ADDR CNTRL UPPER DATA 040 ADDR CNTRL U DATA 040 ADDR CNTRL L DATA 10885 00 9401 ...

Page 72: ...at purpose Although handshaking is unnecessary in many applications the lines themselves remain part of many designs because they facilitate troubleshooting Table A 1 lists the standard EIA 232 D interconnections To interpret this information correctly remember that EIA 232 D was intended to connect a terminal to a modem When computers are connected to each other without modems one of them must be...

Page 73: ...R DATA SET READY Output from the modem to the terminal to indicate that the modem is ready to transmit data 07 SIG GND SIGNAL GROUND Common return line for all signals at the modem interface 08 DCD DATA CARRIER DETECT Output from the modem to the terminal to indicate that a valid carrier is being received 09 14 Not used 15 TxC TRANSMIT CLOCK DCE Output from the modem to the terminal clocks data fr...

Page 74: ...ide flow control to avoid buffer overflow This is not possible if modems are used It is usually necessary to make CTS high by connecting it to RTS or to some source of 12 volts such as the resistors shown in Figure A 1 CTS is also frequently jumpered to an MC1488 gate which has its inputs grounded the gate is provided for this purpose Another signal used in many systems is DCD The original purpose...

Page 75: ...y provide the needed signal Figure A 1 Middle of the Road EIA 232 D Configuration 3 TXD RXD RTS CTS DCD TXC RXC 12V TXD RXD RTS CTS DCD TXC RXC OPTIONAL HARDWARE TRANSPARENT MODE LOGIC 470Ω 39kΩ 39kΩ 39kΩ 470Ω 39kΩ 12V 2 1 5 6 8 7 7 1 20 2 3 4 5 6 CHASSIS GND CONNECTOR TO TERMINAL CONNECTOR TO MODEM OR HOST SYSTEM RXD TXD NC CTS DSR DCD SIG GND DTR TXD RXD RTS CTS DCD 12V 12V 12V 12V 12V GND 12V S...

Page 76: ...the CTS DCD and DSR signals Two of these connectors wired back to back can be used In this implementation however diagnostic messages that might otherwise be generated do not occur because all the handshaking is bypassed In addition the TX and RX lines may have to be crossed since TX from a terminal is outgoing but the TX line on a modem is an incoming signal Figure A 2 Minimum EIA 232 D Connectio...

Page 77: ...m is that when units are connected to different electrical outlets there may be several volts of difference in ground potential If pin 1 of each device is interconnected with the others via cable several amperes of current could result This condition may not only be dangerous for the small wires in a typical cable but may also produce electrical noise that causes errors in data transmission That i...

Page 78: ... 2 battery handling and disposal 4 3 battery lifetime 4 3 BBRAM see Battery Backed Up RAM MK48T08 and NVRAM 3 26 4 4 BBRAM configuration area memory map 3 25 BBRAM TOD Clock memory map 3 26 BG bus grant 2 7 big endian mode 3 24 binary number 1 9 block diagram ECC DRAM mezzanine module 4 13 MVME167 main module 4 11 parity DRAM mezzanine module 4 12 board ID 3 27 board serial number 3 27 board speed...

Page 79: ...96CA and LAN 2 8 4 6 Ethernet address 3 27 3 28 Ethernet interface 4 6 Ethernet station address 4 6 Ethernet transceiver interface 4 6 extended addressing 2 7 F factory jumper settings 2 2 FCC compliance 1 4 features 1 2 forced air cooling 1 3 front panel 3 1 front panel indicators DS1 DS4 3 2 functional description 4 1 fuse F1 2 8 fuse F2 2 8 G GCSR Global Control and Status Regis ters see VMEchi...

Page 80: ... resources 4 7 local SCSI ID 3 28 location monitors 2 8 longword 1 9 LRST local reset 3 1 3 30 M manual terminology 1 9 map decoders 3 29 MC68040 MPU 4 2 MCECC 1 5 MCECC internal register memory map 3 17 MEMC040 1 5 MEMC040 internal register memory map 3 17 memory maps 3 3 53C710 SCSI 3 24 82596CA Ethernet LAN 3 23 BBRAM configuration area 3 25 BBRAM TOD Clock 3 26 Cirrus Logic CD2401 serial port ...

Page 81: ...nstructions 3 1 operating systems 1 6 P P2 adapter board 1 5 2 7 2 8 parallel port interface 4 6 parallel printer port 4 6 parity DRAM mezzanine module block diagram 4 12 PCCchip2 1 5 PCCchip2 memory map 3 14 printer interface 4 6 printer memory map 3 16 printer port 4 6 programmable hardware interrupts 4 8 programmable tick timers 4 7 proper grounding A 6 R registers 3 30 default values 3 30 rela...

Page 82: ...2 2 2 system mode 1 6 system reset SRST 3 30 system reset SRST see SYSRESET 3 1 SYSTEM V 68 1 6 systems serial ID 3 28 T terminal s A 1 terminology 1 9 tick timers 4 7 timeout 4 8 global bus 2 8 local bus 4 8 timers 4 7 timing performance 4 8 TOD clock memory map 3 26 transfer type TT signals 3 3 transition modules 1 5 4 5 transparent mode A 4 TRXC4 Transmit Receive Clock 4 2 4 TT transfer type si...

Page 83: ...Index IN 6 MVME167 Single Board Computer User s Manual I N D E X ...

Page 84: ...quipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentation Artisan Scientific Corporation dba Artisan Technology Group is not an affiliate representative or authorized distributor for any manufacturer listed herein We re here to make your life easier How...

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