Motorola MVME167 Series, User Manual

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MVME167 Functional Description
MVME167/D3 4-9
4
LAN DMA Transfers
The MVME167 includes a LAN interface with DMA controller. The LAN DMA
controller uses a FIFO buffer to interface the serial LAN bus to the 32-bit local bus.
The FIFO buffer allows the LAN DMA controller to efficiently transfer data to the
local bus.
The 82596CA does not execute MC68040 compatible burst cycles, therefore the LAN
DMA controller does not use burst transfers. Parity DRAM write cycles require 3
clock cycles, and read cycles require 5 clock cycles with parity off and 6 clock cycles
with parity on.
The transfer rate of the LAN DMA controller is 20 MB/sec at 25 MHz with parity off.
Assuming a continuous transfer rate of 1 MB/sec on the LAN bus, 5% of the local bus
bandwidth is used by transfers from the LAN bus.
Remote Status and Control
The remote status and control connector, J3, is a 20-pin connector located behind the
front panel of the MVME167. It provides system designers the flexibility to access
critical indicator and reset functions. This allows a system designer to construct a
RESET/LED panel that can be located remotely from the MVME167.
In addition to the LED and RESET switch access, this connector also includes two
general purpose TTL-level I/O pins and one general purpose interrupt pin which can
also function as a trigger input. This interrupt pin is level programmable.