Motorola MPC860 PowerQUICC, User Manual

Page: 547 / 1106

MOTOROLA Chapter 18. Communications Processor Module and CPM Timers 18-11
Part V. The Communications Processor Module
Note that the counter registers may not be updated correctly if a write is made while the
timer is not running. Use TRRx to deÞne the preferred count value.
18.2.3.6 Timer Event Registers (TER1ÐTER4)
Each timer event register (TER1ÐTER4), shown in Figure 18-10, reports events recognized
by the timers. When an output reference event is recognized, the timer sets TERx[REF]
regardless of the corresponding TMRx[ORI]. The capture event is set only if it is enabled
in TMR[CE]. TER1ÐTER4 can be read at any time and are cleared by reset.
Writing ones clears event bits; writing zeros has no effect. Both event bits must be cleared
before the timer negates the interrupt to the CPIC.
Table 18-3 describes the TER Þelds,
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Up counter
Reset 0
R/W R/W
Addr 0x99C (TCN1), 0x99E (TCN2), 0x9AC (TCN3), 0x9AE (TCN4)
Figure 18-9. Timer Capture Registers (TCR1ÐTCR4)
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ REF CAP
Reset 0
Addr 0x9B0 (TER1), 0x9B2 (TER2), 0x9B4 (TER3), 0x9B6 (TER4)
Figure 18-10. Timer Event Registers (TER1ÐTER4)
Table 18-3. TER Field Descriptions
Bits Name Description
0Ð13 Ñ Reserved, should be cleared.
14 REF Output reference event. When set, indicates the counter reached the value in the TRR. TMR[ORI] is
used to enable the interrupt request caused by this event.
15 CAP Capture event. Indicates that the counter value has been latched into the TCR. TMR[CE] enables
generation of this event.