Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-3
Part II. PowerPC Microprocessor Module
9.3 Address Translation
The core generates 32-bit effective addresses (EA) for memory accesses. Setting MSR[IR]
and MSR[DR] enables the effective-to-real translation for instruction fetching and data
accesses, respectively. Section 9.3.1, ÒTranslation Disabled,Ó describes behavior when
translation is disabled. Section 9.3.2, ÒTranslation Enabled,Ó describes behavior when
translation is enabled.
9.3.1 Translation Disabled
Because the IMMU and DMMU are separate, translation can be disabled or enabled
independently for data and instruction accesses by clearing MSR[DR] and MSR[IR],
respectively. When translation is disabled, the effective address is also the physical address.
Because the page translation mechanism is not used, the protection attributes that are part
of the page table structure cannot be used, so defaults are used. The default for whether
accesses are cache-inhibited are programmed through Mx_CTR[CIDEF]. Data accesses
can be either write-through (memory writes go both to the cache and to external memory)
or write back (memory writes directly affect the cache only and memory is updated
indirectly, such as when a modiÞed data in the cache is cast-out by newer data at a different
address that maps to the same cache block). The default is conÞgured by
MD_CTR[WTDEF].
Also, when translation is disabled (real mode), the entire memory space is treated as
guarded by default. The implications of this are:
1. Speculative load/store accesses are stalled until they are no longer speculative.
2. Speculative instruction fetches outside of the current real-mode page are stalled until
they are no longer speculative. The size of real-mode page is determined by
MI_CTR[PPM]. If MI_CTR[PPM] = 0, the real-mode page size is 4 Kbytes; if
MI_CTR[PPM] = 1, the real-mode page size is 1 Kbyte.
This behavior can result in signiÞcant performance degradation.
9.3.2 Translation Enabled
Translations are generated on a per-page basis and are stored in tables in memory. Along
with the translation, each table entry holds attributes for that page, for example, whether a
location is cacheable.
Recently used translations are kept in translation lookaside buffers (TLBs) in hardware. In
the MPC860, software handles the table lookup and TLB reload with little hardware
assistance. This offers a ßexible translation table structure choice, because many systems
would not beneÞt from a full-featured hardware translation mechanism.
A TLB hit in multiple entries is avoided when a TLB is being reloaded. When TLB logic
detects that a new effective page number (EPN) overlaps one in the TLB (when taking into
account pages sizes, subpage validity ßags, user/supervisor state, address pace ID (ASID),
and the SH values of the TLB entries), the new EPN is written and the old one is invalidated.