Motorola MPC860 PowerQUICC, User Manual

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4-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part II. PowerPC Microprocessor Module
Table 4-4 summarizes MPC860 features with respect to the VEA deÞnition.
Integer load/
store multiple
instructions For these types of instructions, EA must be a multiple of four. If it is not, the system alignment
error handler is invoked. For an
lmw instruction (if r A is in the range of registers to be loaded), the
instruction completes normally. r A is then loaded from the memory location as follows:
r A <- MEM(EA+( r A- r D)*4, 4)
Integer load string
instructions Load string instructions behave like load multiple instructions with respect to invalid format in
which
r A is in the range of registers to be loaded. If r A is in the range, it is updated from memory.
Memory
synchronization
instructions For these instructions, if EA is not a multiple of four, the system alignment error handler is invoked.
Optional
instructions No optional instructions are supported.
Little-endian byte
ordering The LSU supports little-endian byte ordering as speciÞed in the UISA. In little-endian mode, trying
to execute an unaligned individual scalar or multiple/string access causes an alignment exception.
Table 4-4. VEA-Level Features
Functionality Description
Memory
coherency Memory coherency is not supported in the MPC860 hardware, but can be performed in the software
or by deÞning memory as cache inhibited. In addition, the MPC860 does not provide any data storage
attributes to an external system.
Atomic update
primitives Both the lwarx and stwcx. instructions are implemented according to the PowerPC architecture
requirements. When memory accessed by the lwarx and stwcx. instructions is in the cache-allowed
mode, it is assumed that the system works with the single master in this memory region. Therefore, if
a data cache miss occurs, the access on the internal and external buses does not have a reservation
attribute. The MPC860 does not cause the system DSI exception handler to be invoked if memory
accessed by the
lwarx and stwcx. instructions is in write-through required mode. Also, the MPC860
does not support snooping an external bus activity outside the chip. The provision is made to cancel
the reservation inside the MPC860 by using the CR and KR input signals. For accesses to internal
resources, internal snoop logic monitors the internal bus for communication processor module (CPM)
accesses of the address associated with the last
lwarx instruction.
The effect of
operand
placement on
performance The LSU hardware supports all PowerPC integer load/store instructions. Naturally-aligned operands
give optimal performance for a maximum size of four bytes. Unaligned operands are supported in
hardware and are broken into a series of aligned transfers. The effect of operand placement on
performance is as stated in the VEA, except for 8-byte operands. Because the MPC860 uses a 32-bit
data bus, performance is good rather than optimal. See Section 4.5.3.5, ÒUnaligned Accesses for a
description of integer unaligned instruction execution and timing and to Section 10.2.2, ÒString
Instruction Latency,Ó for a description of string instruction timing.
Table 4-3. UISA-Level Features (Continued)
Functionality Description