Motorola MCX600E, Service Manual, Page: 58 / 105

Transmitter Power Amplifier (PA) 5-25W
4-20 Theory of Operation
A high impedance resonant circuit formed by D8551 in off state and L8554, C8559 prevents an
influence of the receive signal by the PA stages. The high impedance of D8631 in off state doesn´t
influence the receiver signal.
9.5 Harmonic Filter
The transmitter signal from the antenna switch is channelled through the harmonic filter to the
antenna connector J8501.The harmonic filter is formed by inductors L8552, L8553, and capacitors
C8551 through C8554. This network forms a low-pass filter to attenuate harmonic energy of the
transmitter to specifications level. R8550 is used for electro-static protection.
9.6 Power Control
The power control loop regulates transmitter power with an automatic level control (ALC) loop and
provides protection features against excessive control voltage and high operating temperatures.
MOS FET device bias, power and control voltage limit are adjusted under microprocessor control
using a Digital to Analog (D/A) converter (U0731). The microprocessor writes the data into the D/A
converter via serial interface (SRL) composed of the lines SPI CLCK SRC (clock), SPI DATA SRC
(data) and DAC CE (chip enable). The D/A adjustable control voltage limit increases transmitter rise
time and reduces adjacent channel splatter as it is adjusted closer to the actual operating control
voltage.
The microprocessor controls K9V1 ENABLE (U0101-3) to switch on the first and the second PA
stage via transistors Q0741, Q0742 and signal K9V1. The antenna switch is turned on by the
collector current of the second PA stage. In TX mode the front-end control D/A (U0731-11) is used
for BIAS VOLTAGE 2 (via R0736) and K9V1 ENABLE pulls signal FE CNTL VLTG to ground via
Q0743. PA DISABLE, also microprocessor controlled (U0101-26), sets BIAS VLTG (U0731-4) and
VLTG LIMIT SET (U0731-13) via D0731 and BIAS VLTG 2 via D0733 in receive mode to low to
switch off the biases of the MOS FET devices Q8530, Q8531 and to switch off the power control
voltage (PWR CNTL).
Through an Analog to Digital (A/D) input (VLTG LIMIT) the microprocessor can read the PA control
voltage (PWR CNTL) during the tuning process.The ALC loop regulates power by adjusting the PA
control line PWR CNTL to keep the forward power voltage PWR DETECT at a constant level.
Opamp U0701-2 and resistors R0701 to R0703 and R0731 subtract the negative PWR DETECT
voltage from the PA PWR SET D/A output U0731 pin 2. The result is connected to opamp inverting
input U0701-4 pin 9 which is compared with a 4.6 volt reference VAG present at noninverting input
U0701-4 pin 10 and controls the output power of the PA via pin 8 and control line PWR CNTL. The
4.6 volt reference VAG is set by a resistive divider circuit (R0251, R0252) which is connected to
ground and 9.3 volts, and buffered by opamp U0251-1.
During normal transmitter operation the voltages at the opamp inputs U0701-4 pins 9 and 10 should
be equal to 4.6 volts and the PA control voltage output at pin 8 should be between 4 and 7 volts. If
power falls below the desired setting, PWR DETECT becomes less negative, causing the output at
U0701-2 pin 7 to decrease and the opamp output U0701-4 pin 8 to increase.
A comparator formed by U0701-4 increases the PA control voltage PA CNTL until PWR DETECT is
at the desired level. The power set D/A output voltage PA PWR SET (U0731-2) at U0701-2 pin 5
adjusts power in steps by adjusting the required value of PWR DETECT. As PA PWR SET (U0731-
2) decreases, transmitter power must increase to make PWR DETECT more negative and keep the
inverting input U0701-4 pin 9 at 4.6 volts.
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