Motorola MCX600E, Service Manual, Page: 53 / 105

Receive Signalling Circuits
Theory of Operation 4-15
The audio PA is enabled via AUDIO PA ENABLE signal from the ASFIC (U0201-B5). When the base
of Q0401 is low, the transistor is off and U0401-8 is high, using pull up resistor R0406, and the Audio
PA is ON. The voltage at U0401-8 must be above 8.5VDC to properly enable the device. If the
voltage is between 3.3 and 6.4V, the device will be active but has its input (U0401-1/9) off. This is a
mute condition which is not employed in this radio design. R0404 ensures that the base of Q0401 is
high on power up. Otherwise there may be an audio pop due to R0406 pulling U0401-8 high before
the software can switch on Q0401.
The SPK+ and SPK- outputs of the audio PA have a DC bias which varies proportionately with FLT
A+ (U0401-7). FLT A+ of 11V yields a DC offset of 5V, and FLT A+ of 17V yields a DC offset of 8.5V.
If either of these lines is shorted to ground, it is possible that the audio PA will be damaged. SPK+
and SPK- are routed to the accessory connector (J400-16 and 1) and to the control head (connector
J0101-1 and 2).
6.4 Filtered Audio
The ASFIC has an audio whose output at U0201-B2 has been filtered and de-emphasized, but has
not gone through the digital volume attenuator. From ASFIC U0201-B2 the signal is AC coupled to
U0202-2 by capacitor C0230. R0224 and R0225 determine the gain of op-amp U0202-2. The output
of U0202-2 is the routed to J0400-11.Note that any volume adjustment of the signal on this path
must be done by the accessory.
7.0 Receive Signalling Circuits
Refer to Figure 4.4 for reference for the following sections.
Figure 4.4 Receive Signalling Path.
DET AUDIO
DISCRIMINATOR AUDIO
FROM RF SECTION
(IF IC)
G4
A4
GEPD 5431
C5 J3
G1 C3
J7
11
10
6 5
LOW SPEED
CLOCK
PL
IN
RX LIM
CAP
PL
LIM
RX
LIM
OUT
LOW SPEED
LIM CAP
HIGH SPEED
CLOCK
DATA FILTER
AND DEEMPHASIS
LIMITER
FILTER LIMITER
ASFIC
U0201
MICRO
CONTROLLER
U0101
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