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Hardware Preparation and Installation

Figure 1-5. TMCP700 Serial Ports 3 and 4 DCE Configuration

TMCP700

TXD

RTS#

RXD

CTS#

DCD#

TRXC

RTXC

DTR#

LLB#

RLB#

DSR#

RI#

TM#

J3/MX

Z85230 SCC

Z8536 CIO

EIA232-DTE SIM

2097 9709

MCP750

J8/J9

Summary of Contents for MCP750

Page 1: ...MCP750 CompactPCI Single Board Computer Installation and Use MCP750A IH4 July 2000 ...

Page 2: ...and the Motorola symbol are registered trademarks of Motorola Inc PowerPC and PowerPC750 are trademarks of IBM Corporation and are used by Motorola Inc under license from IBM Corporation All other products mentioned in this document are trademarks or registered trademarks of their respective holders ...

Page 3: ...ide the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the po...

Page 4: ...losion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Attention Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du même type ou d un type équivalent recommandé par le constructeur M...

Page 5: ...tion of Conformity is available on request Please contact your sales representative Notice While reasonable efforts have been made to assure the accuracy of this document Motorola Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the ...

Page 6: ...d to in writing by Motorola Inc Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 ...

Page 7: ...lection J6 1 6 TMCP700 Transition Module Preparation 1 9 Serial Ports 1 and 2 1 11 Configuration of Serial Ports 3 and 4 1 11 Hardware Installation 1 16 ESD Precautions 1 16 Compact FLASH Memory Card Installation 1 16 RAM300 Memory Mezzanine Installation 1 18 PMC Module Installation 1 20 MCP750 Module Installation 1 22 TMCP700 Transition Module Installation 1 24 System Considerations 1 26 MCP750 M...

Page 8: ... 7 PC87307 ISA Super I O Device ISASIO 3 7 Asynchronous Serial Ports 3 8 Parallel Port Printer Interface 3 8 Floppy Disk Tape Drive Controller 3 8 Keyboard and Mouse Interface 3 9 PCI Peripheral Bus Controller PBC 3 9 Real Time Clock NVRAM Watchdog Timer Function 3 10 Programmable Timers 3 11 Raven General Purpose Timers 3 11 Raven Watchdog Timers 3 11 M48T559 Watchdog Timer 3 12 Interval Timers 3...

Page 9: ...11 J12 J13 J14 4 8 Front USB Connectors J17 J18 4 10 10 100 Base T Connector J8 4 11 COM1 Connector J15 4 12 Debug Connector J19 4 12 DRAM Mezzanine Connector J10 4 17 EIDE Compact FLASH Connector J9 4 20 TMCP700 Transition Module 4 21 CompactPCI Connectors J3 J4 J5 4 22 Serial Ports 1 and 2 J10 J11 TMCP700 I O Mode 4 22 Serial Ports 3 and 4 J6 J24 TMCP700 I O Mode 4 23 Parallel Connector J7 TMCP7...

Page 10: ...tem Call Interfaces 5 13 Bug Diagnostics 5 13 Diagnostic Tests 5 14 High Availability Specific PPCBug Diagnostic Commands 5 15 Unsupported PPCBug Diagnostic Commands 5 15 CHAPTER 6 CNFG and ENV Commands Overview 6 1 CNFG Configure Board Information Block 6 1 ENV Set Environment 6 2 Configuring the PPCBug Parameters 6 3 APPENDIX A Specifications Specifications A 1 Cooling Requirements A 2 EMC Compl...

Page 11: ...P700 Serial Ports 3 and 4 DCE Configuration 1 14 Figure 1 6 TMCP700 Serial Ports 3 and 4 DTE Configuration 1 15 Figure 1 7 Compact FLASH Placement on MCP750 1 17 Figure 1 8 RAM300 Placement on MCP750 1 19 Figure 1 9 PMC Module Placement on MCP750 1 21 Figure 1 10 TMCP700 MCP750 Mating Configuration 1 25 Figure 2 1 PPCBug System Startup 2 2 Figure 3 1 MCP750 Block Diagram 3 4 Figure 3 2 Serial Port...

Page 12: ...Table 4 8 USB 0 Connector J18 4 10 Table 4 9 USB 1 Connector J17 4 11 Table 4 10 10 100 Base T Connector J8 4 11 Table 4 11 COM1 Connector J15 4 12 Table 4 12 Debug Connector J19 4 12 Table 4 13 DRAM Mezzanine Connector J10 4 17 Table 4 14 EIDE Compact FLASH Connector J9 4 20 Table 4 15 Serial Connections Ports 1 and 2 J10 and J11 TMCP700 4 22 Table 4 16 Serial Connections Ports 3 and 4 J6 and J24...

Page 13: ...stem Calls 5 13 Table 5 6 Specific Diagnostic Test Groups 5 14 Table 5 7 PPCBug Diagnostic Commands For High Availability Systems 5 15 Table 5 8 Unsupported PPCBug Diagnostic Commands 5 16 Table A 1 MCP750 Specifications A 1 Table B 1 Motorola Computer Group Documents B 1 Table B 2 Manufacturers Documents B 2 Table B 3 Related Specifications B 6 ...

Page 14: ...M 5MB FLASH 1MB L2 Cache MCP750 1252A MPC750 233 MHz CPU 128MB ECC DRAM 5MB FLASH 1MB L2 Cache MCP750 1262A MPC750 233 MHz CPU 256MB ECC DRAM 5MB FLASH 1MB L2 Cache MCP750 1432 MPC750 366 MHz CPU 32 MB ECC DRAM 9MB FLASH 1MB L2 Cache MCP750 1442 MPC750 366 MHz CPU 64 MB ECC DRAM 9MB FLASH 1MB L2 Cache MCP750 1452 MPC750 366 MHz CPU 128 MB ECC DRAM 9MB FLASH 1MB L2 Cache MCP750 1462 MPC750 366 MHz ...

Page 15: ...ard computer on a block diagram level The General Description section provides an overview of the MCP750 followed by a detailed description of several blocks of circuitry Chapter 4 Connector Pin Assignments summarizes the pin assignments for the groups of interconnect signals for the MCP750 and the TMCP700 Chapter 5 PPCBug provides information on the PPCBug and its architecture Additionally it des...

Page 16: ...s DW164 2900 S Diablo Way Tempe Arizona 85282 You can also submit comments to the following e mail address reader comments mcg mot com In all your correspondence please list your name position and company Be sure to include the title and part number of the manual and tell how you used it Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements Conventi...

Page 17: ...les and to introduce new terms courier is used for system output for example screen displays reports examples and system prompts Enter Return or CR CR represents the carriage return or Enter key CTRL represents the Control key Execute control characters by pressing the Ctrl key and the letter simultaneously for example Ctrl d ...

Page 18: ... of ECC DRAM is provided with 1m to 9m of linear FLASH memory IDE Compact Flash memory and 1MB of L2 cache memory level 2 secondary cache memory The complete MCP750 consists of the base main board plus an ECC DRAM module RAM300 for memory shipped with the board and an Optional PCI Mezzanine Card PMC for additional versatility The diagram in Figure 1 1 illustrates the architecture of the MCP750 bas...

Page 19: ...net DEC21140 PBC VT82C586B Serial P MC SLot RTC MK48T559 Super I O PC87307 Front Panel 10BT 100BTx Ethernet USB 1 USB 0 NVRAM ISA 33 MHz 32 64 bit PCI Bus WD J4 PCI PCI BRIDGE DEC21154 USB Clock Generator Reset Control Arbitration Control Flash DRAM Expansion Up to 8M Linear Flash 256M DRAM IDE USB 32 64 bit PMC Slot MPIC Controller SERIAL KEYBOARD MOUSE PARALLEL CIO z8536 ESCC Z85230 2 SYNC ASYNC...

Page 20: ... MCP750 modules are factory configured for I O handling via a TMCP700 transition module There are various MCP750 models available that correspond to different memory configurations One transition module supports all configurations of the board Note Contact your local Motorola sales representative and or your designated sales systems engineer for the latest configuration specifications on the vario...

Page 21: ...n Ensure memory mezzanines are properly installed on the board RAM300 Memory Mezzanine Installation Install PMC Module if required PMC Module Installation Install the MCP750 in the chassis MCP750 Module Installation Install transition module into chassis TMCP700 Transition Module Installation Connect any other devices or equipment used Chapter 4 Connector Pin Assignments Refer also to the document...

Page 22: ...onfiguration To produce the desired configuration and ensure proper operation of the MCP750 you may need to carry out certain hardware modifications before installing the module The MCP750 provides software control over most options by setting bits in control registers after installing the module in a system you can modify its configuration Note that the MCP750 control registers are described in C...

Page 23: ...entation The MCP750 is factory tested and shipped with the configurations described in the following sections The board s factory installed debug monitor and PPCBug operates properly with these factory settings Flash Bank Selection J6 The MCP750 has provisions for 1MB of 16 bit Flash memory The RAM300 memory mezzanine accommodates 4MB or 8MB of additional 64 bit Flash memory The flash memory is or...

Page 24: ...P750 Base Board Preparation http www motorola com computer literature 1 7 1 3 2 1 3 2 1 Flash Bank A Enabled Flash Bank B Enabled 1MB on base board J6 J6 Factory Configuration 4MB 8MB on RAM300 mezzanine ...

Page 25: ... and Installation 1 Figure 1 2 MCP750 Switches Headers Connectors Fuses LEDs 1 J15 189 190 2 1 J10 2 DS2 4 1 XU2 J11 49 50 3 J8 S2 S1 1 DS1 DS3 DS4 J17 J18 4 1 1 5 6 9 8 2 7 1 1 2 J12 49 50 1 2 J13 49 50 1 2 J14 49 50 XU1 J6 J5 J4 J3 J2 J1 J9 189 190 2 1 J19 F1 F2 F3 ...

Page 26: ...2 on the transition module s panel Two synchronous serial ports identified as SERIAL 3 and SERIAL 4 on the transition module s panel configured for EIA 232 D EIA 530 V 35 or X 21 protocols via Serial Interface Module modules Two Universal Serial Bus USB ports Two 60 pin Serial Interface Module SIM connectors used for configuring serial ports 3 and 4 A combination keyboard mouse connector A 40 pin ...

Page 27: ... Connector and Header Locations 2214 9804 COM 1 1 USB 1 SERIAL 4 2 4 1 J1 59 60 J11 1 8 J18 J19 4 1 8 2 7 1 USB 0 J14 J8 2 1 64 63 J21 J9 J13 2 1 1 2 J23 59 60 2 1 64 63 J2 3 1 3 1 2 1 40 39 J15 2 1 34 33 J17 J10 8 2 7 1 J7 17 1 34 18 J24 13 1 26 14 J6 13 1 26 14 COM 2 SERIAL 3 PARALLEL KB MS J16 J3 J5 J4 ...

Page 28: ...s Serial Port 3 and 4 are configured through a combination of serial interface module SIM selection and jumper settings The following table lists the SIM connectors and jumper headers corresponding to each of the synchronous serial ports Port 3 is routed to board connector J6 Port 4 is available at board connector J24 Typical interface modules include EIA 232 D DCE and DTE EIA 530 DCE and DTE V 35...

Page 29: ...tch the configuration of the corresponding SIM module When installing the SIM modules note that the headers are keyed for proper orientation For further information on the preparation of the transition module refer to the user s manual for the TMCP700 listed in Appendix B Related Documentation The next three figures illustrate the MCP750 base board and TMCP700 transition module with the interconne...

Page 30: ...literature 1 13 1 Figure 1 4 MCP750 TMCP700 Serial Ports 1 and 2 DTE Only MCP750 2098 9710 4 2 5 7 8 TMCP700 1 3 6 COM1 COM2 4 2 5 7 8 1 3 6 9 1 8 2 6 4 7 3 5 COM1 Front Panel DB9 SOUT1 RTS1 DTR1 SIN1 RI1 CTS1 DSR1 DCD1 PC87307 SOUT2 RTS2 DTR2 SIN2 RI2 CTS2 DSR2 DCD2 J5 ...

Page 31: ...Preparation and Installation 1 Figure 1 5 TMCP700 Serial Ports 3 and 4 DCE Configuration TMCP700 TXD RTS RXD CTS DCD TRXC RTXC DTR LLB RLB DSR RI TM J3 MX Z85230 SCC Z8536 CIO 3 5 4 2 15 17 24 25 22 21 18 6 7 EIA232 DTE SIM 2097 9709 20 8 MCP750 J8 J9 3 2 1 ...

Page 32: ...com computer literature 1 15 1 Figure 1 6 TMCP700 Serial Ports 3 and 4 DTE Configuration TMCP700 TXD RTS RXD CTS DCD TRXC RTXC DTR LLB RLB DSR RI TM J3 MX Z85230 SCC Z8536 CIO 2 4 5 3 24 15 17 18 21 22 25 6 7 EIA232 DTE SIM 2096 9709 8 20 MCP750 J8 J9 3 2 1 ...

Page 33: ...trongly recommends that you use an antistatic wrist strap and a conductive foam pad when installing or upgrading a system Electronic components such as disk drives computer boards and memory modules are extremely sensitive to ESD After removing a component from the system or its protective wrapper place the component on a grounded static free surface In handling a board place it component side up ...

Page 34: ...ove the AC cord or DC power lines from the system Remove the chassis or system cover s as necessary to access the compact PCI module Figure 1 7 Compact FLASH Placement on MCP750 Caution Inserting or removing modules with power applied may result in damage to module components Warning To prevent injury use extreme caution when handling testing and adjusting this equipment Dangerous voltages capable...

Page 35: ...nnector on the underside of the mezzanine should connect smoothly with the corresponding connector J10 on the MCP750 7 Insert the four short phillips head screws through the holes at the corners of the RAM300 mezzanine and into the standoffs on the MCP750 Tighten the screws 8 Reinstall the MCP750 assembly in the proper card slot Ensure that the module is properly seated in the backplane connectors...

Page 36: ...om the system Remove chassis or system cover s as necessary for access to the compact PCI module Figure 1 8 RAM300 Placement on MCP750 Caution Inserting or removing modules with power applied may result in damage to module components Warning To prevent injury use extreme caution when handling testing and adjusting this equipment Dangerous voltages capable of causing death exist 11661 00 9611 2 3 ...

Page 37: ...Tighten the screws 6 Reinstall the MCP750 assembly in its proper card slot Be sure the module is well seated in the backplane connectors Do not damage or bend connector pins 7 Replace the chassis or system cover s reconnect the system to the AC or DC power source and turn the equipment power on PMC Module Installation PCI mezzanine card PMC module mounts beside the RAM300 mezzanine on top of the M...

Page 38: ... Warning To prevent injury use extreme caution when handling testing and adjusting this equipment Dangerous voltages capable of causing death exist 3 Carefully remove the MCP750 from the CompactPCI card slot and place it on a clean and adequately protected working surface with connectors J1 and J5 facing you Caution Avoid touching areas of integrated circuitry static discharge can damage these cir...

Page 39: ... the module is well seated in the backplane connectors Do not damage or bend connector pins 8 Replace the chassis or system cover s reconnect the system to the AC or DC power source and turn the equipment power on MCP750 Module Installation With mezzanine board s installed and headers properly configured proceed as follows to install the MCP750 in the CompactPCI chassis 1 Attach an ESD strap to yo...

Page 40: ... Some CompactPCI subracks may have a red guide rail to mark the system slot 4 Set the VIO on the backplane to either 3 3V or 5V depending upon your system s signaling requirements and ensure the backplane does not bus J3 J4 or J5 signals 5 Slide the MCP750 into the system slot Grasping the top and bottom injector handles be sure the module is well seated in the P1 through P5 connectors on the back...

Page 41: ...AC cord or DC power lines from the system Remove chassis or system cover s as necessary for access to the chassis backplane Caution Inserting or removing modules with the power applied may result in damage to the module components Warning To prevent injury use extreme caution when handling testing and adjusting this equipment Dangerous voltages capable of causing death exist 3 If Serial Ports 3 an...

Page 42: ...entation 5 Secure in place with the screws provided making good contact with the transverse mounting rails to minimize RF emissions 6 Replace the chassis or system cover s making sure no cables are pinched Cable the peripherals to the panel connectors reconnect the system to the AC or DC power source and turn the equipment power on Figure 1 10 TMCP700 MCP750 Mating Configuration MCP750 TMCP700 ...

Page 43: ...EC21154 data sheet for additional details listed in Appendix B Related Documentation On the MCP750 base board the standard serial console port COM1 serves as the PPCBug debugger console port The firmware console should be set up as follows Eight bits per character One stop bit per character Parity disabled no parity Baud rate of 9600 baud 9600 is the default baud rate for serial ports on MCP750 bo...

Page 44: ...able fuses The 12Vdc and 12Vdc voltages are used only by the SIM modules on the TMCP700 All fused voltages are available on either J3 J4 or J5 for use on the transition module Separately fused 5Vdc is also provided for the keyboard mouse Separate 5Vdc fused power is also provided for each USB channel and the PMC slot 5V See Table 3 3 on page 3 18 for fuse assignments ...

Page 45: ...he MPU hardware and firmware initialization process is performed by the PowerPC PPCBug power up or system reset The firmware initializes the devices on the SBC module in preparation for booting the operating system The firmware is shipped from the factory with an appropriate set of defaults In most cases there is no need to modify the firmware configuration before you boot the operating system The...

Page 46: ...d RESET switches and four LED status indicators BFL CPU PCI CPCI For additional information on front panel operation refer to Chapter 3 Functional Description Memory Maps There are three points of view for memory maps STARTUP SYSTEM INITIALIZATION CONSOLE DETECTION OPERATING SYSTEM RUN SELFTESTS IF ENABLED AUTOBOOT IF ENABLED 11734 00 9702 ...

Page 47: ...ration is under the control of the Raven bridge controller ASIC and the Falcon memory controller chip set The Raven and Falcon devices adjust system mapping to suit a given application via programmable map decoder registers At system power up or reset a default processor memory map takes over Default Processor Memory Map The default processor memory map that is valid at power up or reset remains i...

Page 48: ...ding suggested PREP compatible memory maps refer to the MCP750 Series Single Board Computer Programmer s Reference Guide MCP750A PG PCI Local Bus Memory Map The PCI memory map is controlled by the Raven ASIC and by the 21154 PCI to PCI bridges The Raven and the PCI to PCI bridges adjust system mapping to suit a given application via programmable map decoder registers A no default PCI memory map ex...

Page 49: ... bus secondary bus All devices on the CompactPCI bus must be configured for addressing within this defined range Conversely these registers also define the addresses for which transactions will be forwarded upstream Any CompactPCI bus address generated by a CompactPCI bus master not in the defined memory range will be forwarded upstream to the Primary PCI bus There is no address translation betwee...

Page 50: ...terrupt sources It controls PHB PCI Host Bridge MPU local bus interface functions on the MCP750 as well as performing interrupt handling Sources of interrupts may be any of the following The Raven ASIC itself timer interrupts or transfer error interrupts The processor processor self interrupts The Falcon chip set memory error interrupts The PCI bus interrupts from PCI devices The CPCI bus interrup...

Page 51: ...g timer Reset function controlled by the SGS Thomson MK48T559 Watchdog Timer or the Raven Watchdog Timer 4 Port 92 Register via the PBC 5 CompactPCI Bus via the 21154 Bridge Control Register Table 2 2 PBC DMA Channel Assignments PBC Priority PBC Label Controller DMA Assignment 1 Channel 0 DMA1 Serial Port 3 Receiver Z85230 Port A Rx 2 Channel 1 Serial Port 3 Transmitter Z85230 Port A Tx 3 Channel ...

Page 52: ...hardware differences in big and little endian operations For further details on endian considerations refer to the MCP750 Series Single Board Computer Programmer s Reference Guide MCP750A PG Processor Memory Domain The MPC750 processor can operate in both big endian and little endian mode However it always treats the external processor memory bus as big endian by performing address rearrangement a...

Page 53: ...en reverse rearranges the address for PCI bound accesses and rearranges the address for memory bound accesses from PCI In this case no byte swapping is done PCI Domain The PCI bus is inherently little endian All devices connected directly to the PCI bus operate in little endian mode regardless of the mode of operation in the processor s domain PCI and Ethernet Ethernet is also byte stream oriented...

Page 54: ...this guide for a more detailed functional description of the MCP750 Features The following table summarizes the features of the MCP750 single board computers Table 3 1 MCP750 Features Feature Description Microprocessor MPC750 PowerPC processor 233 MHz 366 MHz or 450MHz ECC DRAM 16MB 256MB on RAM300 module L2 cache memory Populated with 1MB on base board Flash Memory Two 32 pin PLCC sockets 1MB 16 ...

Page 55: ...eral Bus Controller Serial I O 1 async port COM1 via front panel 2 async ports 2 sync async ports via the transition module Parallel I O IEEE 1284 bidirectional parallel port PC87307 SIO via the transition module Ethernet I O 10 100 Base T connection via the front panel PCI interface One IEEE P1386 1 PCI Mezzanine Card PMC slot one 110 pin CompactPCI connector J4 for PCI expansion Keyboard mouse i...

Page 56: ...ces to a CompactPCI bus using a DEC 21154 PCI to PCI bridge device This device provides a 64 bit primary and a 64 bit secondary interface allowing full 64 bit data access between CompactPCI bus devices and the host PCI bridge This bus is capable of driving seven CompactPCI slots Another key feature of the MCP750 family is the PCI Peripheral Component Interconnect bus In addition to the on board lo...

Page 57: ...Keyboard Mouse Async Serial RTC PMC Slot 1 RTC DRAM Raven 32 64 Bit PCI Local Bus ISA SIO Peripheral Bus PCI to PCI Bridge 1 FLASH Falcon Falcon MPC750 L2 Cache Sys CSR ISA CSR ISA Local Resource Bus Bridge 2 IDE Bus Compact FLASH SRAM SROM USB 2 Sync Async 2 channels 2 channels Controller Serial FDD USB 1 Connector Expansion 60X System Bus ...

Page 58: ...serted After a reset the 21154 parks the CPCI bus at itself until a new request is asserted The 21154 provides the 33MHz clocks for each of the CompactPCI slots All clock source outputs are active following power up or reset The 21154 provides a control register to allow individual clock sources to be disabled For additional information refer to the DEC21154 data sheet The 21154 supports 3 3V or 5...

Page 59: ...et SROM The Ethernet information in the SROM is stored in DEC Version 3 format For further information on this subject refer to the Digital Semiconductor 21x4 Serial ROM Format Version 3 03 document listed in Appendix B Related Documentation Caution Use extreme caution when viewing the contents of the Ethernet SROM via the PPCBUG SROM command If the contents are modified incorrectly this could cau...

Page 60: ... bit or 64 bit IEEE P1386 1 PMC compatible mezzanines to add any desirable function The PCI Mezzanine Card slot has the following characteristics Refer to Chapter 4 Connector Pin Assignments for the pin assignments of the PMC connectors For additional programming information refer to the PCI bus descriptions in the MCP750 Programmer s Reference Guide MCP750A PG and to the user documentation for th...

Page 61: ... PG and to the vendor documentation for the ISASIO device Parallel Port Printer Interface The parallel port is a full IEEE1284 bidirectional parallel port printer interface that supports standard enhanced and extended port modes All parallel I O interface signals are routed to the transition module that includes series damping resistors Hardware initializes the parallel port as PPT1 with an ISA IO...

Page 62: ...ignals are routed to a single 6 pin circular DIN connector on the transition module Keyboard functions can be obtained by plugging the keyboard directly into this connector To get both keyboard and mouse functions requires a Y adapter cable Motorola Part Number 30 W2309E01A Refer to the TMCP700 Installation and Use manual for details PCI Peripheral Bus Controller PBC The MCP750 uses the VIA Techno...

Page 63: ... clock oscillator crystal power failure detection memory write protection 8KB of NVRAM and a battery in a package consisting of two parts A 28 pin 330mil SO device containing the real time clock the oscillator power failure detection circuitry timer logic 8KB of static RAM and gold plated sockets for a battery A SNAPHAT battery housing a crystal along with the battery The SNAPHAT battery package i...

Page 64: ...y software The timeout period is programmable from 1 microsecond up to 4 seconds If the timer count reaches 0 a timer output signal will be asserted The output of Watchdog Timer 1 is routed to generate an MPIC interrupt The output of Watchdog Timer 2 is logically ORed onboard to provide a hard reset Following a device reset WDT1 is enabled with a default timeout of 512 milliseconds and WDT 2 is en...

Page 65: ...c function Counter 0 is associated with interrupt request line IRQ0 It can be used for system timing functions such as a timer interrupt for a time of day function Counter 1 generates a refresh request signal for ISA memory This timer is not used in the MCP750 Counter 2 provides the tone for the speaker output function on the PBC the SPEAKER_OUT signal which can be cabled to an external speaker vi...

Page 66: ...and pseudo interrupt acknowledge cycles for the Z85230 and the Z8536 in ISA I O space The PBC controller supplies DMA support for the Z85230 The Z85230 receives a 10MHz clock input The two synchronous ports will support data transfers up to 2 5Mbits sec The Z85230 supplies an interrupt vector during pseudo interrupt acknowledge cycles The vector is modified within the Z85230 according to the inter...

Page 67: ...t no PCI mezzanine card is installed in PMC slot 1 If cleared PMC slot 1 contains a PCI mezzanine card LANP Ethernet present If set no Ethernet transceiver interface is installed If cleared there is on board Ethernet support Serial Port Signal Multiplexing Due to pin limitations of the J3 connector the MCP750 multiplexes and de multiplexes some signals between the MCP750 board and the TMCP700 tran...

Page 68: ...nes MXDO and MXDI MXSYNC is asserted for one bit time at Time Slot 15 by the MCP750 board MXSYNC is used by the transition module to synchronize with the MCP750 board MXDO is the time multiplexed output line from the main board and MXDI is the time multiplexed line from the transition module A 16 to 1 multiplexing scheme is used with 10MHz bit rate Sixteen Time Slots are defined and allocated as f...

Page 69: ...sing edge The timing relationships among MXCLK MXSYNC MXDO and MXDI are shown in Figure 3 3 Table 3 2 Multiplexing Sequence of the MX Function MXDO From MCP750 MXDI From TMCP700 TIME SLOT SIGNAL NAME TIME SLOT SIGNAL NAME 0 RTS3 0 CTS3 1 DTR3 1 DSR3 MID1 2 LLB3 MODSEL 2 DCD3 3 RLB3 3 TM3 MID0 4 RTS4 4 RI3 5 DTR4 5 CTS4 6 LLB4 6 DSR4 MID3 7 RLB4 7 DCD4 8 IDREQ 8 TM4 MID2 9 Reserved 9 RI4 10 Reserve...

Page 70: ...ule via ISA bus interrupt line IRQ8 The signal is also available at pin PB7 of the Z8536 CIO device which handles various status signals serial I O lines and counters The interrupter connected to the ABORT switch is an edge sensitive circuit filtered to remove switch bounce RESET RST Switch S1 The RESET switch resets all onboard devices and generates a CompactPCI backplane reset Front Panel Indica...

Page 71: ...tches Resettable Fuses The MCP750 provides inline slow blow fuses for each power rail including 5Vdc 3 3Vdc and PMC 5Vdc Polyswitches are provided for VIO keyboard mouse Vcc and the two USB output voltages 12Vdc and 12Vdc The Table 3 3 lists the fuses with the voltages they protect Table 3 3 Fuse Assignments Fuse Type Voltage Purpose J Number Fuse Rating F1 Slow Blow 3 3Vdc for onboard voltage to ...

Page 72: ...f level 2 cache L2 cache and up to 9MB of Flash memory The L2 cache and 1MB of 16 bit Flash memory reside on the MCP750 base board The ECC DRAM and 4MB or 8MB of additional 64 bit Flash memory are located on the RAM300 memory mezzanine The MPC750 is a 64 bit processor with 64KB on chip cache 32KB data cache and 32KB instruction cache The L2 cache is implemented with an on chip two way set associat...

Page 73: ... after a reset Displaying and modifying configuration variables Running self tests and diagnostics Updating firmware ROM Under normal operation the Flash devices are in read only mode their contents are pre defined and they are protected against inadvertent writes due to loss of power conditions However for programming purposes programming voltage is always supplied to the devices and the Flash co...

Page 74: ...P750 supports a single EIDE compatible Compact FLASH Memory Card off of the PBC Primary EIDE interface Currently available Compact FLASH memory cards provide from 2 Mbytes to 24 Mbytes of formatted capacity Once configured this memory will appear as a standard ATA EIDE disk drive TMCP700 Transition Module The TMCP700 transition module is used in conjunction with all models of the MCP750 base board...

Page 75: ...nted circuit boards which contain all the circuitry needed to convert a TTL level port to the standard voltage levels needed by various industry standard serial interfaces such as EIA 232 EIA 530 etc SIMs are available for the following configurations For additional information about the serial interface modules refer to the TMCP700 Transition Module Installation and Use manual listed in Appendix ...

Page 76: ...ser I O Connector J5 PCI Mezzanine Card PMC Connectors Front USB Connectors 10 100 Base T Connector COM1 Connector Debug Connector Add On Memory Mezzanine Connector Compact FLASH Memory Card Connector CompactPCI Connectors J3 J4 J5 Serial Ports 1 and 2 TMCP700 I O Mode Serial Ports 3 and 4 TMCP700 I O Mode Parallel Connector TMCP700 I O Mode Keyboard Mouse Connector J16 TMCP700 I O Mode USB Connec...

Page 77: ... Z pack 2mm hard metric type A connector with keying for 3 3V or 5V J2 is 110 pin AMP Z pack 2mm hard metric type B connector Each of these connectors conform to the CompactPCI specification The pinout for connectors J1 and J2 are shown below Table 4 1 J1 CompactPCI Connector ROW A ROW B ROW C ROW D ROW E 25 5V REQ64_L ENUM_L 3 3V 5V 25 24 AD1 5V VIO AD0 ACK64_L 24 23 3 3V AD4 AD3 5V AD2 23 22 AD7...

Page 78: ...ST_L GND GNT_L 5 4 No Connect BRSVP1A4 GND VIO No Connect INTP No Connect INTS 4 3 INTA_L INTB_L INTC_L 5V INTD_L 3 2 TCK 5V TMS TDO TDI 2 1 5V 12V TRST_L 12V 5V 1 Table 4 2 J2 CompactPCI Connector ROW A ROW B ROW C ROW D ROW E 22 No Connect RSV No Connect RSV No Connect RSV No Connect RSV No Connect RSV 22 21 CLK6 GND No Connect RSV No Connect RSV No Connect RSV 21 20 CLK5 GND No Connect RSV GND ...

Page 79: ...2E18 18 17 No Connect BRSVP2A17 GND PRST_L REQ6_L GNT6_L 17 16 No Connect BRSVP2A16 No Connect BRSVP2B16 DEG_L GND No Connect BRSVP2E16 16 15 No Connect BRSVP2A15 GND FAL_L REQ5_L GNT5_L 15 14 AD35 AD34 AD33 GND AD32 14 13 AD38 GND VIO AD37 AD36 13 12 AD42 AD41 AD40 GND AD39 12 11 AD45 GND VIO AD44 AD43 11 10 AD49 AD48 AD47 GND AD46 10 9 AD52 GND VIO AD51 AD50 9 8 AD56 AD55 AD54 GND AD53 8 7 AD59 ...

Page 80: ...O4 PMCIO3 PMCIO2 PMCIO1 13 12 PMCIO10 PMCIO9 PMCIO8 PMCIO7 PMCIO6 12 11 PMCIO15 PMCIO14 PMCIO13 PMCIO12 PMCIO11 11 10 PMCIO20 PMCIO19 PMCIO18 PMCIO17 PMCIO16 10 9 PMCIO25 PMCIO24 PMCIO23 PMCIO22 PMCIO21 9 8 PMCIO30 PMCIO29 PMCIO28 PMCIO27 PMCIO26 8 7 PMCIO35 PMCIO34 PMCIO33 PMCIO32 PMCIO31 7 6 PMCIO40 PMCIO39 PMCIO38 PMCIO37 PMCIO36 6 5 PMCIO45 PMCIO44 PMCIO43 PMCIO42 PMCIO41 5 4 PMCIO50 PMCIO49 P...

Page 81: ...ROW C ROW D ROW E 25 AD36 AD35 AD34 AD33 AD32 25 24 AD40 AD39 AD38 GND AD37 24 23 AD45 AD44 AD43 AD42 AD41 23 22 AD49 3 3V AD48 AD47 AD46 22 21 AD53 AD52 AD51 GND AD50 21 20 AD57 3 3V AD56 AD55 AD54 20 19 AD61 AD60 AD59 GND AD58 19 18 CBE4 3 3V PAR64 AD63 AD62 18 17 REQ64 CBE7 CBE6 GND CBE5 17 16 AD2 3 3V AD1 AD0 ACK64 16 15 AD6 AD5 AD4 GND AD3 15 12 14 KEY AREA 12 14 11 AD9 AD8 CBE0 GND AD7 11 10...

Page 82: ...nector ROW A ROW B ROW C ROW D ROW E 22 Reserved GRD Reserved 5V SPKROC_L 22 21 KBDDAT KBDCLK KBAUXVCC AUXDAT AUXCLK 21 20 Reserved Reserved Reserved GND Reserved 20 19 STB_L GND UVCC0 UDATA0 UDATA0 19 18 AFD_L UDATA1 UDATA1 GND UVCC1 18 17 PD2 INIT_L PD1 ERR_L PD0 17 16 PD6 PD5 PD4 PD3 SLIN_L 16 15 SLCT PE BUSY ACK_L PD7 15 14 RTSa CTSa RIa GND DTRa 14 13 DCDa 5V RXDa DSRa TXDa 13 12 RTSb CTSb RI...

Page 83: ...8 DD6 1 Table 4 6 PCI Mezzanine Card Connector J11 J12 1 TCK 12V 2 1 12V TRST 2 3 GND PMCINTA 4 3 TMS TDO 4 5 PMCINTB PMCINTC 6 5 TDI GND 6 7 PMC1P 5V 8 7 GND Not Used 8 9 PMCINTD Not Used 10 9 Not Used Not Used 10 11 GND Not Used 12 11 Pull up 3 3V 12 13 PCICLK GND 14 13 PCIRST Pull down 14 15 GND PMC1GNT 16 15 3 3V Pull down 16 17 PMC1REQ 5V 18 17 Not Used GND 18 19 5V AD31 20 19 AD30 AD29 20 21...

Page 84: ...D03 58 57 Not Used Not Used 58 59 AD02 AD01 60 59 GND Not Used 60 61 AD00 5V 62 61 ACK64 3 3V 62 63 GND REQ64 64 63 GND Not Used 64 Table 4 7 PCI Mezzanine Card Connector J13 J14 1 Not Used GND 2 1 PMCIO1 PMCIO2 2 3 GND C BE7 4 3 PMCIO3 PMCIO4 4 5 C BE6 C BE5 6 5 PMCIO5 PMCIO6 6 7 C BE4 GND 8 7 PMCIO7 PMCIO8 8 9 5V Vio PAR64 10 9 PMCIO9 PMCIO10 10 11 AD63 AD62 12 11 PMCIO11 PMCIO12 12 13 AD61 GND ...

Page 85: ... 36 35 PMCIO35 PMCIO36 36 37 AD45 GND 38 37 PMCIO37 PMCIO38 38 39 5V Vio AD44 40 39 PMCIO39 PMCIO40 40 41 AD43 AD42 42 41 PMCIO41 PMCIO42 42 43 AD41 GND 44 43 PMCIO43 PMCIO44 44 45 GND AD40 46 45 PMCIO45 PMCIO46 46 47 AD39 AD38 48 47 PMCIO47 PMCIO48 48 49 AD37 GND 50 49 PMCIO49 PMCIO50 50 51 GND AD36 52 51 PMCIO51 PMCIO52 52 53 AD35 AD34 54 53 PMCIO53 PMCIO54 54 55 AD33 GND 56 55 PMCIO55 PMCIO56 5...

Page 86: ...nector located on the front panel of the MCP750 SBC The pin assignments for this connector are as follows 4 GND Table 4 9 USB 1 Connector J17 1 UVCC1 2 UDATA1N 3 UDATA1P 4 GND Table 4 10 10 100 Base T Connector J8 1 TD 2 TD 3 RD 4 AC Terminated 5 AC Terminated 6 RD 7 AC Terminated 8 AC Terminated Table 4 8 USB 0 Connector J18 Continued ...

Page 87: ...the transition module but not both at the same time The pin assignments for this connector is as follows Debug Connector J19 A 190 pin connector J19 on the MCP750 base board provides access to the processor bus MPU bus and some bridge memory controller signals It can be used for debugging purposes The pin assignments are listed in the following table Table 4 11 COM1 Connector J15 1 DCD 2 RXD 3 TXD...

Page 88: ...6 27 PA26 PA27 28 29 PA28 PA29 30 31 PA30 PA31 32 33 PA_PAR0 PA_PAR1 34 35 PA_PAR2 PA_PAR3 36 37 APE RSRV 38 39 PD0 PD1 40 41 PD2 PD3 42 43 PD4 PD5 44 45 PD6 PD7 46 47 PD8 PD9 48 49 PD10 PD11 50 51 PD12 PD13 52 53 PD14 PD15 54 55 PD16 PD17 56 57 PD18 5V PD19 58 59 PA20 PD21 60 61 PD22 PD23 62 63 PD24 PD25 64 65 PD26 PD27 66 67 PD28 PD29 68 69 PD30 PD31 70 Table 4 12 Debug Connector J19 Continued ...

Page 89: ...3 PD54 PD55 94 95 PD56 GND PD57 96 97 PD58 PD59 98 99 PD60 PD61 100 101 PD62 PD63 102 103 PDPAR0 PDPAR1 104 105 PDPAR2 PDPAR3 106 107 PDPAR4 PDPAR5 108 109 PDPAR6 PDPAR7 110 111 No Connection No Connection 112 113 DPE DBDIS 114 115 TT0 TSIZ0 116 117 TT1 TSIZ1 118 119 TT2 TSIZ2 120 121 TT3 No Connection 122 123 TT4 No Connection 124 125 CI No Connection 126 127 WT No Connection 128 129 GLOBAL No Co...

Page 90: ...132 133 AACK 3 3V TS 134 135 ARTY XATS 136 137 DRTY TBST 138 139 TA No Connection 140 141 TEA No Connection 142 143 No Connection DBG 144 145 No Connection DBB 146 147 No Connection ABB 148 149 TCLK_OUT MPUBG 0 150 151 No Connection MPUBR0 152 Table 4 12 Debug Connector J19 Continued ...

Page 91: ...164 165 CLAIM TLBISYNC 166 167 No Connection TBEN 168 169 No Connection No Connection 170 171 No Connection GND No Connection 172 173 No Connection No Connection 174 175 No Connection NAPRUN 176 177 SRST1 QREQ 178 179 SRESET QACK 180 181 HRESET CPUTDO 182 183 GND CPUTDI 184 185 CPUCLK1 CPUTCK 186 187 No Connection CPUTMS 188 189 No Connection CPUTRST 190 Table 4 12 Debug Connector J19 Continued ...

Page 92: ...ing table Table 4 13 DRAM Mezzanine Connector J10 1 A_RAS A_CAS 2 3 B_RAS B_CAS 4 5 C_RAS C_CAS 6 7 D_RAS D_CAS 8 9 OEL OEU 10 11 WEL WEU 12 13 ROMACS ROMBCS 14 15 RAMAEN RAMBEN 16 17 RAMCEN EN5VPWR 18 19 RAL0 GND RAL1 20 21 RAL2 RAL3 22 23 RAL4 RAL5 24 25 RAL6 RAL7 26 27 RAL8 RAL9 28 29 RAL10 RAL11 30 31 RAL12 RAU0 32 33 RAU1 RAU2 34 35 RAU3 RAU4 36 37 RAU5 RAU6 38 39 RAU7 RAU8 40 41 RAU9 RAU10 4...

Page 93: ...9 RDL24 RDL25 70 71 RDL26 RDL27 72 73 RDL28 RDL29 74 75 RDL30 RDL31 76 77 RDL32 RDL33 78 79 RDL34 RDL35 80 81 RDL36 RDL37 82 83 RDL38 RDL39 84 85 RDL40 RDL41 86 87 RDL42 RDL43 88 89 RDL44 RDL45 90 91 RDL46 RDL47 92 93 RDL48 RDL49 94 95 RDL50 GND RDL51 96 97 RDL52 RDL53 98 99 RDL54 RDL55 100 101 RDL56 RDL57 102 103 RDL58 RDL59 104 105 RDL60 RDL61 106 107 RDL62 RDL63 108 109 CDL0 CDL1 110 Table 4 13...

Page 94: ... 120 121 RDU2 RDU3 122 123 RDU4 RDU5 124 125 RDU6 RDU7 126 127 RDU8 RDU9 128 129 RDU10 RDU11 130 131 RDU12 RDU13 132 133 RDU14 3 3V RDU15 134 135 RDU16 RDU17 136 137 RDU18 RDU19 138 139 RDU20 RDU21 140 141 RDU22 RDU23 142 143 RDU24 RDU25 144 145 RDU26 RDU27 146 147 RDU28 RDU29 148 149 RDU30 RDU31 150 151 RDU32 RDU33 152 Table 4 13 DRAM Mezzanine Connector J10 Continued ...

Page 95: ...DU37 156 157 RDU38 RDU39 158 159 RDU40 RDU41 160 161 RDU42 RDU43 162 163 RDU44 RDU45 164 165 RDU46 RDU47 166 167 RDU48 RDU49 168 169 RDU50 RDU51 170 171 RDU52 GND RDU53 172 173 RDU54 RDU55 174 175 RDU56 RDU57 176 177 RDU58 RDU59 178 179 RDU60 RDU61 180 181 RDU62 RDU63 182 183 CDU0 CDU1 184 185 CDU2 CDU3 186 187 CDU4 CDU5 188 189 CDU6 CDU7 190 Table 4 14 EIDE Compact FLASH Connector J9 1 GND DATA3 ...

Page 96: ...ND GND 10 11 GND GND 12 13 5V GND 14 15 GND GND 16 17 GND DA2 18 19 DA1 DA0 20 21 DATA0 DATA1 22 23 DATA2 NO CONNECT 24 25 CD2_L CD1_L 26 27 DATA11 DATA12 28 29 DATA13 DATA14 30 31 DATA15 DCS3A_L 32 33 NO CONNECT DIORA_L 34 35 DIOWA_L NO CONNECT 36 37 INTRQA 5V 38 39 MASTER SLAVE NO CONNECT 40 41 RST_L DIORDYA 42 43 NO CONNECT NO CONNECT 44 45 NO CONNECT NO CONNECT 46 47 DATA8 DATA9 48 49 DATA10 G...

Page 97: ...nector J5 is a 110 pin 2mm hard metric type B connector which routes I O signals for IDE keyboard mouse USB and printer ports The pinout for this connector has been previously described in Table 4 3 Serial Ports 1 and 2 J10 J11 TMCP700 I O Mode The MCP750 provides both asynchronous ports 1 and 2 and synchronous asynchronous ports 3 and 4 serial connections The asynchronous interface is implemented...

Page 98: ...connectors J6 and J24 located on the front panel of the transition module The pin assignments for serial ports 3 and 4 are listed in the following table Table 4 16 Serial Connections Ports 3 and 4 J6 and J24 TMCP700 1 No Connection 2 TXDn 3 RXDn 4 RTSn 5 CTSn 6 DSRn 7 GND 8 DCDn 9 SPn_P9 10 SPn_P10 11 SPn_P11 12 SPn_P12 13 SPn_P13 14 SPn_P14 15 TXCIn 16 SPn_P16 17 RXCIn 18 LLBn 19 SPn_P19 20 DTRn ...

Page 99: ...d in the following table 23 SPn_P23 24 TXCOn 25 TMn 26 SPn P26 Table 4 17 Parallel Connector J7 TMCP700 1 PRBSY GND 19 2 PRSEL GND 20 3 PRACK GND 21 4 PRFAULT GND 22 5 PRPE GND 23 6 PRD0 GND 24 7 PRD1 GND 25 8 PRD2 GND 26 9 PRD3 GND 27 10 PRD4 GND 28 11 PRD5 GND 29 12 PRD6 GND 30 13 PRD7 GND 31 14 PRINIT GND 32 15 PRSTB GND 33 16 SELIN GND 34 17 AUTOFD GND 35 18 Pull up No Connection 36 Table 4 16...

Page 100: ...nto this connector To get keyboard and mouse operations a Y adapter cable is required Motorola part number 30 W2309E01A The pin assignments are listed in the following table USB Connectors J18 J19 Optional TMCP700 I O Mode The TMCP700 has two USB series A receptacles J18 and J19 However the standard version of the MCP700 board does not route the USB signals to these connectors in order to prevent ...

Page 101: ...onnector are listed in the following table Table 4 19 EIDE Connector J15 Pin Signal Signal Pin 1 DRESET_L GND 2 3 DD7 DD8 4 5 DD6 DD9 6 7 DD5 DD10 8 9 DD4 DD11 10 11 DD3 DD12 12 13 DD2 DD13 14 15 DD1 DD14 16 17 DD0 DD15 18 19 GND No Connect 20 21 DMARQ GND 22 23 DIOW_L GND 24 25 DIOR_L GND 26 27 IORDY No Connect 28 29 DMACK_L GND 30 31 INTRQ No Connect 32 33 DA1 No Connect 34 35 DA0 DA2 36 37 CS1F...

Page 102: ...ffboard devices This power is derived from the fused 5Vdc power on the MCP750 Any external device powered from this connector must not draw more than 200mA The pin assignments are listed in the following table Table 4 20 Floppy Connector J17 Pin Signal Signal Pin 1 GND No Connect 2 3 GND No Connect 4 5 GND No Connect 6 7 GND Index_L 8 9 GND MTRQ_L 10 11 GND DS1_L 12 13 No Connect DSQ_L 14 15 GND M...

Page 103: ...PMC I O Connectors J2 J21 The PMC I O connectors consist of two 64 pin header connectors J2 and J21 The pin assignments and signal mnemonics for these connectors are listed in the following two tables Table 4 21 5Vdc Power Connector J14 Pin Signal 1 5Vdc 2 GND 3 GND 4 No Connect Table 4 22 Speaker Output Connector J13 Pin Signal 1 GND 2 SPKROC_L Table 4 23 PMC I O Connector J2 Pin Signal Signal Pi...

Page 104: ...ND PMCIO13 26 27 GND PMCIO14 28 29 GND PMCIO15 30 31 GND PMCIO16 32 33 GND PMCIO17 34 35 GND PMCIO18 36 37 GND PMCIO19 38 39 GND PMCIO20 40 41 GND PMCIO21 42 43 GND PMCIO22 44 45 GND PMCIO23 46 47 GND PMCIO24 48 49 GND PMCIO25 50 51 GND PMCIO26 52 53 GND PMCIO27 54 55 GND PMCIO28 56 57 GND PMCIO29 58 59 GND PMCIO30 60 61 GND PMCIO31 62 63 GND PMCIO32 64 Table 4 23 PMC I O Connector J2 Continued Pi...

Page 105: ...11 GND PMCIO38 12 13 GND PMCIO39 14 15 GND PMCIO40 16 17 GND PMCIO41 18 19 GND PMCIO42 20 21 GND PMCIO43 22 23 GND PMCIO44 24 25 GND PMCIO45 26 27 GND PMCIO46 28 29 GND PMCIO47 30 31 GND PMCIO48 32 33 GND PMCIO49 34 35 GND PMCIO50 36 37 GND PMCIO51 38 39 GND PMCIO52 40 41 GND PMCIO53 42 43 GND PMCIO54 44 45 GND PMCIO55 46 47 GND PMCIO56 48 49 GND PMCIO57 50 51 GND PMCIO58 52 53 GND PMCIO59 54 55 G...

Page 106: ...00 Transition Module http www motorola com computer literature 4 31 4 57 GND PMCIO61 58 59 GND PMCIO62 60 61 GND PMCIO63 62 63 GND PMCIO64 64 Table 4 24 PMC I O Connector J21 Continued Pin Signal Signal Pin ...

Page 107: ...s system calls and other advanced user topics For additional information about the PPCBug refer to the PPCBug Firmware Package User s Manual PPCBUGA1 UM and PPCBUGA2 UM and the PPCBug Diagnostics Manual PPCDIAA UM as listed in Appendix B Related Documentation PPCBug Basics The PowerPC debug firmware PPCBug is a powerful evaluation and debugging tool for systems built around the Motorola PowerPC mi...

Page 108: ... PPCBug Diagnostics Manual PPCDIAA UM A user interface or debug diagnostics monitor that accepts commands from the system console terminal When using the PPCBug you operate out of either the debugger directory or the diagnostic directory If you are in the debugger directory the debugger prompt PPC1 Bug is displayed and you have all of the debugger commands at your disposal If you are in the diagno...

Page 109: ...ity Where necessary assembly language has been used in the form of separately compiled program modules containing only assembler code No mixed language modules are used Physically PPCBug is contained in two socketed 32 pin PLCC Flash devices that together provide 1MB of storage The executable code is checksummed at every power on or reset firmware entry and the result which includes a precalculate...

Page 110: ...speed of read write memory from NVRAM 14 Initializes the read write memory controller with the speed of read write memory 15 Retrieves the speed of read only memory that is Flash from NVRAM 16 Initializes the read only memory controller with the speed of read only memory 17 Enables the MPU s instruction cache 18 Copies the MPU s exception vector table from FFF00000 to 00000000 19 Initializes the P...

Page 111: ...and displays a warning message if the verification fails 30 Displays the BUS clock speed verifies that the BUS clock speed matches the configuration data and displays a warning message if the verification fails 31 Displays any Keyboard Controller initialization error that occurs 32 Probes PCI bus for supported network devices 33 Probes PCI bus for supported mass storage devices 34 Initializes the ...

Page 112: ...e for example GO then control may or may not return to the debugger depending on what the user program does For example if a breakpoint has been specified then control returns to the debugger when the breakpoint is encountered during execution of the user program Alternately the user program could return to the debugger by means of the System Call Handler routine RETURN described in the PPCBug Fir...

Page 113: ... the available debugger commands by entering the Help HE command alone You can view the syntax description for a particular command by entering HE followed by a space followed by the particular command mnemonic listed below followed by a carriage return Keep in mind that help is now available on both the BUG and DIAG side In addition issuing help on a DIAG test category will give more information ...

Page 114: ...ump S Records ECHO Echo String ENV Set Environment FORK Fork Idle MPU at Address FORKWR Fork Idle MPU with Registers GD Go Direct Ignore Breakpoints GEVBOOT Global Environment Variable Boot GEVDEL Global Environment Variable Delete GEVDUMP Global Environment Variable s Dump GEVEDIT Global Environment Variable Edit GEVINIT Global Environment Variable Initialization GEVSHOW Global Environment Variab...

Page 115: ...Display NOMA Macro Delete MAE Macro Edit MAL Enable Macro Listing NOMAL Disable Macro Listing MAR Load Macros MAW Save Macros MD MDS Memory Display MENU System Menu MM Memory Modify MMD Memory Map Diagnostic MS Memory Set MW Memory Write NAB Automatic Network Boot NAP Nap MPU NBH Network Boot Operating System Halt NBO Network Boot Operating System NIOC Network I O Control NIOP Network I O Physical...

Page 116: ...e RB ROMboot Enable NORB ROMboot Disable RD Register Display REMOTE Remote RESET Cold Warm Reset RL Read Loop RM Register Modify RS Register Set RUN MPU Execution Status SD Switch Directories SET Set Time and Date SROM SROM Examine Modify SYM Symbol Table Attach NOSYM Symbol Table Detach SYMS Symbol Table Display Search T Trace TA Terminal Attach TIME Display Time and Date TM Transparent Mode Tabl...

Page 117: ...upport High Availability HA features You can list the syntax for one of these commands using the HE command with the command name For example HE PWROFF Return shows the syntax for using the PWROFF command to power an I O module TT Trace to Temporary Breakpoint VE Verify S Records Against Memory VER Revision Version Display WL Write Loop Table 5 2 High Availability Specific Debugger Commands Name D...

Page 118: ...an active standby arrangement for example the CPU in domain A uses PCIDOM to take control of both the local PCI domain domain A and of the remote domain domain B Table 5 3 Unsupported Debugger Commands Name Description DMA DMA Block of Memory Move FORK Fork Idle MPU at Address FORKWR Fork Idle MPU with Registers IDLE Idle Master MPU IRD Idle MPU Register Display IRM Idle MPU Register Modify IRS Id...

Page 119: ...0 Bug Diagnostics PPCBug hardware diagnostics package allows for testing and troubleshooting the MPC750 hardware including the High Availability HA features of the CPU module It includes tests for Memory Read Write L2 Cache Real Time Clock Ethernet Controller ISA Bridge Serial Communications Controller UART Keyboard Mouse Controller Parallel Interface PCI PMC Interface EIDE Table 5 5 Unsupported D...

Page 120: ...mpt PPC1 Diag displays and all of the debugger and diagnostic commands are available Note that not all tests are valid for the MCP750 Using the HE command you can list the diagnostic routines available in each test group Refer to the PPCBug Diagnostics Manual listed in Appendix B Related Documentation for complete descriptions of the diagnostic routines and instructions on how to invoke them Table...

Page 121: ...lists PPCBug diagnostic commands that have been added to support High Availability features PPCBug Diagnostic Commands Specific for HA systems Unsupported PPCBug Diagnostic Commands The following table lists PPCBug diagnostic commands that are part of the standard PPCBug package but are not supported on the MPC750 system SCC Serial Communications Controller Tests UART Serial Input Output UART Test...

Page 122: ...Web Site PPCBug 5 Table 5 8 Unsupported PPCBug Diagnostic Commands Name Description CL1283 Parallel Interface Cirrus CL CD1283 Tests CS4231 CS4231 Audio Codec Tests NCR NCR 53C8XX SCSI I O Processor Tests VGA543X VGA Controller GD543X Tests ...

Page 123: ... and PPCBUGA2 UM Refer to that manual for general information about their use and capabilities The following paragraphs present additional information aboutCNFG and ENV that is specific to the PPCBug debugger along with the parameters that can be configured with the ENV command CNFG Configure Board Information Block This command is used to display and configure the Board Information Block which is...

Page 124: ... There is no need to modify block parameters unless the NVRAM is corrupted Refer to the Programmer s Reference Guide MCP750A PG for the actual location and other information about the Board Information Block Refer also to the PPCBug Firmware Package User s Manual PPCBUGA1 UM and PPCBUGA2 UM for a description of CNFG and examples ENV Set Environment Use the ENV command to view and or configure inte...

Page 125: ...stem for Supported I O Controllers Y N Y B Bug is the mode where no system type of support is displayed However system related items are still available Default S System is the standard mode of operation and is the default mode if NVRAM should fail System mode is defined in the PPCBug Firmware Package User s Manual Y Display the field service menu N Do not display the field service menu Default Y ...

Page 126: ...e set to the SCSI ID value entered here Y NVRAM PReP partition header space will be initialized automatically during board initialization but only if the PReP partition fails a sanity check Default N NVRAM header space will not be initialized automatically during board initialization Y Enable PReP style network booting same boot image from a network interface as from a mass storage device N Do not...

Page 127: ... you the option of stopping the boot by use of the BREAK key The time value is from 0 255 seconds Default 5 seconds Auto Boot Enable Y N N Auto Boot at power up only Y N N Y Give boot priority to devices defined in the fw boot path global environment variable GEV N Do not give boot priority to devices listed in the fw boot path GEV Default Y Give boot priority to devices defined in the fw boot pat...

Page 128: ...0 Which disk partition is to be booted as specified in the PowerPC Reference Platform PRP specification If set to zero the firmware will search the partitions in order 1 2 3 4 until it finds the first bootable partition That is then the partition that will be booted Other acceptable values are 1 2 3 or 4 In these four cases the partition specified will be booted without searching Auto Boot Abort D...

Page 129: ... 255 seconds Default 5 seconds ROM Boot Direct Starting Address FFF00000 The first location tested when PPCBug searches for a ROMboot module Default FFF00000 ROM Boot Direct Ending Address FFFFFFFC The last location tested when PPCBug searches for a ROMboot module Default FFFFFFFC Network Auto Boot Enable Y N N Network Auto Boot at power up only Y N N Y The ROMboot function is enabled N The ROMboo...

Page 130: ... Boot Configuration Parameters Offset NVRAM 00001000 The address where the network interface configuration parameters are to be saved retained in NVRAM these parameters are the necessary parameters to perform an unattended network boot A typical offset might be 1000 but this value is application specific Default 00001000 Caution If you use the NIOT debugger command these parameters need to be save...

Page 131: ...west speed found on the available banks of DRAM memory ROM First Access Length 0 31 10 This is the value programmed into the MPC105 ROMFAL field Memory Control Configuration Register 8 bits 23 27 to indicate the number of clock cycles used in accessing the ROM The lowest allowable ROMFAL setting is 00 the highest allowable is 1F The value to enter depends on processor speed refer to your Processor...

Page 132: ...s ignored by PPCBug DRAM Parity Enable On Detection Always Never O A N 0 Note This parameter above also applies to enabling ECC for DRAM L2 Cache Parity Enable On Detection Always Never O A N O PCI Interrupts Route Control Registers PIRQ0 1 2 3 0A0B0E0F Initializes the PIRQx PCI Interrupts route control registers in the IBC PCI ISA bus bridge controller The ENV parameter is a 32 bit value that is ...

Page 133: ...ebugger fail to come up to a prompt the last code displayed will indicate how far the initialization sequence had progressed before stalling The codes are enabled by an ENV parameter Serial Startup Code LF Enable Y N N A line feed can be inserted after each code is displayed to prevent it from being overwritten by the next code This is also enabled by an ENV parameter A list of LED serial codes is...

Page 134: ... Table A 1 MCP750 Specifications Characteristics Specifications Power requirements Excluding transition module PMC keyboard mouse 5Vdc 5 3 8A typical 4 4A max 3 3Vdc 5 1 9A typical 2 5A max Operating temperature 5 C to 55 C entry air with forced air cooling refer to Cooling Requirements section Storage temperature 40 C to 85 C Relative humidity 5 to 85 non condensing Physical dimensions Base board...

Page 135: ...are is executed as the module is subjected to ambient temperature variations Case temperatures of critical high power density integrated circuits are monitored to ensure component vendors specifications are not exceeded While the exact amount of airflow required for cooling depends on the ambient air temperature and the type number and location of boards and other heat sources adequate cooling can...

Page 136: ...ctive module front panel Conductive chassis rails connected to earth ground This provides the path for connecting shields to earth ground Front panel screws properly tightened For minimum RF emissions it is essential that the conditions above be implemented Failure to do so could compromise the EMC compliance of the equipment containing the module ...

Page 137: ... com computer literature To obtain the most up to date product information in PDF or HTML format visit http www motorola com computer literature Table B 1 Motorola Computer Group Documents Document Title Publication Number MCP750 CompactPCI Single Board Computer Installation and Use MCP750A IH MCP750 CompactPCI Single Board Computer Programmer s Reference Guide MCP750A PG TMCP700 Transition Module...

Page 138: ...ion Number MPC750TM RISC Microprocessor Technical Summary Motorola Literature Distribution Center Telephone 800 441 2447 or 303 675 2140 FAX 602 994 6430 or 303 675 2150 E mail ldcformotorola hibbertco com MPC750 D MPC750TM RISC Microprocessor User s Manual Literature Distribution Center for Motorola Semiconductor Products Telephone 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail ldcformotoro...

Page 139: ... 769 3732 MPCFPE AD MPRPPCFPE 01 DECchip 21140 PCI Fast Ethernet LAN Controller Hardware Reference Manual Digital Equipment Corporation Maynard Massachusetts DECchip Information Line Telephone United States and Canada 1 800 332 2717 TTY United States only 1 800 332 2515 Telephone outside North America 1 508 568 6868 EC QC0CA TE DECchip 21154 PCI to PCI Bridge Data Sheet Digital Equipment Corporati...

Page 140: ... IDE Interface National Semiconductor Corporation Customer Support Center or nearest Sales Office 2900 Semiconductor Drive P O Box 58090 Santa Clara California 95052 8090 Telephone 1 800 272 9959 PC87307VUL MK48T559 CMOS 8K x 8 TIMEKEEPERTM SRAM Data Sheet SGS Thomson Microelectronics Group Marketing Headquarters or nearest Sales Office 1000 East Bell Road Phoenix Arizona 85022 Telephone 602 867 6...

Page 141: ...6600 Telephone 408 370 8016 FAX 408 370 8056 DC 8319 00 VT82C586B PIPC PCI Integrated Peripheral Controller VIA Technologies Inc 5020 Brandin Court Fremont CA 94538 Telephone 510 683 3300 FAX 510 683 3301 VT82C586B ATMEL Nonvolitile Memory Data Book Atmel Corporation 2325 Orchord Parkway San Jose CA 95131 Telephone 408 441 0311 FAX 408 436 4300 Website http www atmel com AT24C04 Table B 2 Manufact...

Page 142: ...tment 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 P1386 IEEE PCI Mezzanine Card Specification PMC Institute of Electrical and Electronics Engineers Inc Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 P1386 1 Bidirectional Parallel Port Interface Specification Institute of Electrical and Electronics Enginee...

Page 143: ...ewell Junction NY 12533 6531 Telephone 800 PowerPC OR Morgan Kaufmann Publishers Inc 340 Pine Street Sixth Floor San Francisco CA 94104 3205 USA Telephone 415 392 2665 FAX 415 982 2665 TB338 D MPRPPCHRP 01 ISBN 1 55860 394 8 PowerPC Reference Platform PRP Specification Third Edition Version 1 0 Volumes I and II International Business Machines Corporation Power Personal Systems Architecture 11400 B...

Page 144: ...ith Collision Detection CSMA CD Access Method and Physical Layer Specifications Institute of Electrical and Electronics Engineers Inc Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 IEEE 802 3 Table B 3 Related Specifications Continued Document Title and Source Publication Number ...

Page 145: ... Terminal Equipment and Data Circuit Terminating Equipment Employing Serial Binary Data Interchange EIA 232 D Electronic Industries Association Engineering Department 2001 Eye Street N W Washington D C 20006 ANSI EIA 232 D Standard Compact PCI Specification PCI Industrial Manufacturers Group PICMG 401 Edgewater Pl Suite 500 Wakefield MA 01880 Telephone 781 246 9318 Fax 781 224 1239 CPCI Rev 2 1 Da...

Page 146: ...al ports as ISASIO function 3 7 as transition module feature 3 21 Autoboot enable 6 5 6 6 B base board layout 1 6 base module feature register 3 14 battery 3 11 for timer 3 10 baud rate power up default 1 26 reconfiguring 1 26 BFL board failure light 3 18 big endian 2 8 board configuration 1 5 board failure LED 3 18 Board Information Block hardware display 6 1 board information block 6 1 6 2 board...

Page 147: ...ponding to PMC connectors 1 22 control signals support for 3 13 cooling requirements A 2 counters 3 11 CPCI activity LED 3 18 CPU activity LED 3 18 CPU Type register 2 4 CTS support for 3 13 D DB9 connector 1 11 3 8 DCD support for 3 13 debug firmware PPCBug 5 1 debugger directory 5 14 prompt 5 2 debugger command parts of 5 6 debugger commands 5 7 debugger console port 1 26 debugger firmware 2 1 3...

Page 148: ...atures hardware 3 1 firmware initialization 5 3 firmware PPCBug 5 1 Flash contents modify conditions 3 20 Flash memory 1 6 as location of PPCBug 3 20 sources size 3 20 floppy port as transition module feature 3 22 forced air cooling A 2 front panel LEDs 3 17 front panel connector DB9 3 8 front panel controls 2 2 functions ISA bus 3 3 fuses polyswitches 3 18 H hardware diagnostics 5 13 initializati...

Page 149: ...odule connector 4 28 J14 transition module connector 4 27 J15 connector 4 17 J15 transition module connector 4 26 J16 transition module connector 4 25 J17 connector 4 10 J17 transition module connector 4 27 J18 connector 4 10 J18 J19 transition module connector 4 25 J19 connector 4 12 J2 connector 4 2 J2 J21 transition module connectors 4 28 J3 as multiplex control lines 3 13 J3 connector 4 4 J3 I...

Page 150: ... memory capacities 3 21 memory map default 2 3 PCI local bus 2 3 2 4 memory maps types 2 2 memory size 6 9 6 10 modem line support 3 13 MPIC Interrupt Controller provided by Raven ASIC 2 6 MPU bus processor bus 4 12 MPU initialization 5 3 MPU PCI bus bridge controller 2 3 multiplex support 3 15 multiplexing when used 3 16 N NETboot enable 6 7 Network Auto Boot enable 6 7 NIOT command restrictions ...

Page 151: ...g navigation 5 2 PPCBug parameter Auto Boot at power up only 6 5 Auto Boot Enable 6 5 Auto Boot Scan Enable 6 6 Auto Initialize of NVRAM Header En able 6 4 Bug or System explained 6 3 DRAM Parity Enable 6 10 DRAM Speed in NANO Seconds 6 9 Field Service Menu Enable explained 6 3 L2 Cache Parity Enable 6 10 Memory Size Enable 6 9 Memory Size Ending Address 6 9 Memory Size Starting Address 6 9 Networ...

Page 152: ... status connector 3 12 RESET switch as hard reset 2 7 resets devices affected 2 8 source of 3 21 resetting the system 2 7 3 17 restart mode 5 15 RF emissions A 3 minimized on TMCP700 1 25 proper grounding 1 23 RJ45 connector on MCP750 3 5 ROM Flash Bank A or B mapping 2 4 ROMboot enable 6 7 ROMFAL 6 9 RTS support for 3 13 RxD support for 3 13 S SCSI bus 6 4 SCSI bus controller 6 2 SD PPCBug switch...

Page 153: ... System Call Handler PPCBug subroutine 5 6 system reset signal 3 17 system startup 2 1 T testing the hardware 5 13 timer 16 bit MCP750 function 3 12 interval 3 12 Raven 3 11 Watchdog 3 12 timers programmable 3 11 TMCP700 features 3 21 Transaction forwarding as device access mechanism 2 5 Transition Module installation 1 24 transition module as added multiplex support 3 14 as serial communication c...

Page 154: ... www motorola com computer literature IN 9 I N D E X Raven Watchdog timer 3 11 Z Z85230 Zilog serial communications interface 3 13 Z8536 CIO for added modem control lines 3 13 Z8536 CIO device function 3 13 ...

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