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Device User Guide — 9S12C128DGV1/D V01.05

100

beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped

B.4.3 Factors influencing accuracy

Three factors - source resistance, source capacitance and current injection - have an influenceon the
accuracy of the ATD.

B.4.3.1 Source Resistance:

Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance R

S

specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance is allowable.

B.4.3.2 Source capacitance

When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage

≤

1LSB, then the external filter capacitor, C

f

≥

1024 * (C

INS

- C

INN

).

Table B-4 ATD Operating Characteristics

Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= V

DDA

<= 3.3V+10%

Num C

Rating

Symbol

Min

Typ

Max

Unit

1

D

Reference Potential

Low

High

V

RL

V

RH

V

SSA

V

DDA

/2

V

DDA

/2

V

DDA

V
V

2

C Differential Reference Voltage

V

RH

-V

RL

3.0

3.3

3.6

V

3

D ATD Clock Frequency

f

ATDCLK

0.5

2.0

MHz

4

D

ATD 10-Bit Conversion Period

Clock Cycles

1

Conv, Time at 2.0MHz ATD Clock f

ATDCLK

NOTES

:

1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample

period of 16 ATD clocks.

N

CONV10

T

CONV10

14

7

28
14

Cycles

µ

s

5

D

ATD 8-Bit Conversion Period

Clock Cycles

(1)

Conv, Time at 2.0MHz ATD Clock f

ATDCLK

N

CONV8

T

CONV8

12

6

26
13

Cycles

µ

s

6

D Recovery Time (V

DDA

=3.3 Volts)

t

REC

20

µ

s

7

P

Reference Supply current

I

REF

0.250

mA

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Summary of Contents for MC9S12C Series

Page 1: ...nts in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and ...

Page 2: ...changed to 4mA for 3V range 01 00 15 JUL 03 15 JUL03 LVR level defined for C32 Run IDD changed for C32 Block guide reference table updated Added PCB layout guide for Pierce oscillator configuration IOL parameter updated in 3 3V range 01 01 12 AUG 03 12 AUG 03 Updated PARTID listing due to C128 ECO revision 01 02 20 NOV 03 20 NOV 03 Changed DOC number and CPU DOC reference number Included separate ...

Page 3: ... 57 2 3 5 BKGD TAGHI MODC Background Debug Tag High Mode Pin 58 2 3 6 PA 7 0 ADDR 15 8 DATA 15 8 Port A I O Pins 58 2 3 7 PB 7 0 ADDR 7 0 DATA 7 0 Port B I O Pins 58 2 3 8 PE7 NOACC XCLKS Port E I O Pin 7 58 2 3 9 PE6 MODB IPIPE1 Port E I O Pin 6 60 2 3 10 PE5 MODA IPIPE0 Port E I O Pin 5 60 2 3 11 PE4 ECLK Port E I O Pin 4 E Clock Output 60 2 3 12 PE3 LSTRB Port E I O Pin 3 Low Byte Strobe LSTRB ...

Page 4: ...ins 63 2 4 1 VDDX VSSX Power Ground Pins for I O Drivers 63 2 4 2 VDDR VSSR Power Ground Pins for I O Drivers for Internal Voltage Regulator 63 2 4 3 VDD1 VDD2 VSS1 VSS2 Internal Logic Power Pins 63 2 4 4 VDDA VSSA Power Supply Pins for ATD and VREG 64 2 4 5 VRH VRL ATD Reference Voltage Input Pins 64 2 4 6 VDDPLL VSSPLL Power Supply Pins for PLL 64 Section 3 System Clock Description Section 4 Mod...

Page 5: ...specific information 72 7 1 1 VREGEN 72 7 1 2 VDD1 VDD2 VSS1 VSS2 72 Section 8 Recommended Printed Circuit Board Layout Section 9 Clock Reset Generator CRG Block Description 9 1 Device specific information 79 9 1 1 XCLKS 80 Section 10 Oscillator OSC Block Description Section 11 Timer TIM Block Description Section 12 Analog to Digital Converter ATD Block Description 12 1 Device specific information...

Page 6: ... 7 Operating Conditions 86 A 1 8 Power Dissipation and Thermal Characteristics 87 A 1 9 I O Characteristics 89 A 1 10 Supply Currents 92 Appendix B Electrical Specifications B 1 Voltage Regulator Operating Conditions 95 B 2 Chip Power up and LVI LVR graphical explanation 96 B 3 Output Loads 96 B 3 1 Resistive Loads 96 B 3 2 Capacitive Loads 97 B 4 ATD Characteristics 99 B 4 1 ATD Operating Charact...

Page 7: ...endix C Electrical Specifications C 1 Master Mode 119 C 2 Slave Mode 121 C 3 External Bus Timing 123 C 3 1 General Muxed Bus Timing 123 Appendix D Package Information D 1 General 127 D 2 80 pin QFP package 128 D 3 52 pin LQFP package 129 D 4 48 pin LQFP package 130 Appendix E Emulation Information E 1 General 131 E 1 1 PK 2 0 XADDR 16 14 132 E 2 112 pin LQFP package 133 ...

Page 8: ...Device User Guide 9S12C128DGV1 D V01 05 8 ...

Page 9: ...re 2 7 External Clock Connections PE7 0 59 Figure 3 1 Clock Connections 65 Figure 8 1 Recommended PCB Layout 48 LQFP 74 Figure 8 2 Recommended PCB Layout 52 LQFP 75 Figure 8 3 Recommended PCB Layout 80 QFP 76 Figure 8 4 Recommended PCB Layout for 48 LQFP Pierce Oscillator 77 Figure 8 5 Recommended PCB Layout for 52 LQFP Pierce Oscillator 78 Figure 8 6 Recommended PCB Layout for 80QFP Pierce Oscill...

Page 10: ...1 05 10 Figure D 3 48 pin LQFP Mechanical Dimensions case no 932 03 ISSUE F 130 Figure 19 1 Pin Assignments in 112 pin LQFP 131 Figure 19 2 112 pin LQFP mechanical dimensions case no 987 80 pin QFP Mechanical Di mensions case no 841B 133 ...

Page 11: ...er Guide 35 001C 001D MMC map 3 of 4 HCS12 Module Mapping Control 36 Device User Guide 36 001E 001E MEBI map 2 of 3 HCS12 Multiplexed External Bus Interface 36 001F 001F INT map 2 of 2 HCS12 Interrupt 36 0020 002F DBG including BKP map 1 of 1 HCS12 Debug 36 0030 0031 MMC map 4 of 4 HCS12 Module Mapping Control 37 0032 0033 MEBI map 3 of 3 HCS12 Multiplexed External Bus Interface 37 0034 003F CRG C...

Page 12: ...4 Operating Conditions 87 Table A 5 Thermal Package Characteristics 89 Table A 6 5V I O Characteristics 90 Table A 7 3 3V I O Characteristics 91 Table A 8 Supply Current Characteristics for MC9S12C32 93 Table A 9 Supply Current Characteristics for MC9S12C64 MC9S12C96 MC9S12C128 94 Table B 1 Voltage Regulator Electrical Parameters 95 Table B 2 Voltage Regulator Capacitive Loads 97 Table B 3 ATD Ope...

Page 13: ...V01 05 13 Table C 2 SPI Master Mode Timing Characteristics 120 Table C 3 SPI Slave Mode Timing Characteristics 122 Table C 4 Expanded Bus Timing Characteristics 5V Range 124 Table C 5 Expanded Bus Timing Characteristics 3 3V Range 125 ...

Page 14: ...Device User Guide 9S12C128DGV1 D V01 05 14 ...

Page 15: ...mily members Table 0 2 summarizes the package option and size configuration Table 0 3 lists the part number coding based on the package speed and temperature and preliminary die options for the C Family Table 0 4 lists the part number coding based on the package speed and temperature and preliminary die options for the GC Family Table 0 2 MC9S12C Family Package Option Summary Table 0 1 List of MC9...

Page 16: ...L45J M V C 60 48LQFP MC9S12GC16 MC9S12GC16 1L45J M V C 16K 2K 31 52LQFP MC9S12GC16 MC9S12GC16 1L45J M V C 35 80QFP MC9S12GC16 MC9S12GC16 1L45J M V C 60 NOTES 1 Maskset dependent errata can be accessed at http e www motorola com wbapp sps site prod_summary jsp 2 C TA 85 C f 25MHz V TA 105 C f 25MHz M TA 125 C f 25MHz 3 All C Family derivatives feature 1 CAN 1 SCI 1 SPI an 8 channel A D a 6 channel ...

Page 17: ...S12C96PVFA16 0L09S 40 C 105 C 48LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PVPB16 0L09S 40 C 105 C 52LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PVFU16 0L09S 40 C 105 C 80QFP 16MHz Preliminary C96 using C128 die MC9S12C96VFA16 TBD 40 C 105 C 48LQFP 16MHz Final C96 using C96 die MC9S12C96VPB16 TBD 40 C 105 C 52LQFP 16MHz Final C96 using C96die MC9S12C96VFU16 TBD 40 C 105 C 80QFP 16MH...

Page 18: ... using C64 die MC9S12C64PMFA16 0L09S 40 C 125 C 48LQFP 16MHz Preliminary C64 using C128 die MC9S12C64PMPB16 0L09S 40 C 125 C 52LQFP 16MHz Preliminary C64 using C128 die MC9S12C64PMFU16 0L09S 40 C 125 C 80QFP 16MHz Preliminary C64 using C128 die MC9S12C64MFA16 TBD 40 C 125 C 48LQFP 16MHz Final C64 using C64 die MC9S12C64MPB16 TBD 40 C 125 C 52LQFP 16MHz Final C64 using C64 die MC9S12C64MFU16 TBD 40...

Page 19: ...8 die MC9S12GC128PCFU25 0L09S 40 C 85 C 80QFP 25MHz Preliminary GC128 using C128 die MC9S12GC128CFA25 TBD 40 C 85 C 48LQFP 25MHz Final GC128 using GC128 die MC9S12GC128CPB25 TBD 40 C 85 C 52LQFP 25MHz Final GC128 using GC128 die MC9S12GC128CFU25 TBD 40 C 85 C 80QFP 25MHz Final GC128 using GC128 die MC9S12GC128PVFA25 0L09S 40 C 105 C 48LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PVPB25 0...

Page 20: ... using GC32 die MC9S12GC32PVFA25 1L45J 40 C 105 C 48LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PVPB25 1L45J 40 C 105 C 52LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PVFU25 1L45J 40 C 105 C 80QFP 25MHz Preliminary GC32 using C32 die MC9S12GC32VFA25 TBD 40 C 105 C 48LQFP 25MHz Final GC32 using GC32 die MC9S12GC32VPB25 TBD 40 C 105 C 52LQFP 25MHz Final GC32 using GC32 die MC9S12GC32V...

Page 21: ...4 D HCS12 Module Mapping Control MMC Block Guide V04 S12MMCV4 D HCS12 Multiplexed External Bus Interface MEBI Block Guide V03 S12MEBIV3 D HCS12 Interrupt INT Block Guide V01 S12INTV1 D Analog To Digital Converter 10 Bit 8 Channel ATD_10B8C Block Guide V02 S12ATD10B8CV2 D Clock and Reset Generator CRG Block Guide V04 S12CRGV4 D Serial Communications Interface SCI Block Guide V02 S12SCIV2 D Serial P...

Page 22: ...Device User Guide 9S12C128DGV1 D V01 05 22 ...

Page 23: ...mily has full 16 bit data paths throughout The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements In addition to the I O ports available in each module up to 10 dedicated I O port bits are available with Wake Up capability from STOP or WAIT mode The MC9S12C Family and the MC9S12GC Family devices are available in 48 52 and 80 pin QFP ...

Page 24: ...ation Timer Module TIM 8 Channel Timer Each Channel Configurable as either Input Capture or Output Compare Simple PWM Mode Modulo Reset of Timer Counter 16 Bit Pulse Accumulator External Event Counting Gated Time Accumulation 6 PWM channels Programmable period and duty cycle 8 bit 6 channel or 16 bit 3 channel Separate control for each pulse width and duty cycle Center aligned or left aligned outp...

Page 25: ...om 2 97V to 5 5V Low power mode capability Includes low voltage reset LVR circuitry Includes low voltage interrupt LVI circuitry 48 Pin LQFP 52 Pin LQFP or 80 Pin QFP package Up to 58 I O lines with 5V input and drive capability 80 pin package Up to 2 dedicated 5V input only lines IRQ XIRQ 5V 8 A D converter inputs and 5V I O Development support Single wire background debug mode BDM On chip hardwa...

Page 26: ...de 9S12C128DGV1 D V01 05 26 Special Single Chip Mode with active Background Debug Mode Special Test Mode Motorola use only Special Peripheral Mode Motorola use only Low power modes Stop Mode Pseudo Stop Mode Wait Mode ...

Page 27: ...a Bus Multiplexed Wide Bus IRQ LSTRB TAGLO ECLK MODA IPIPE0 PA4 PA3 PA2 PA1 PA0 PA7 PA6 PA5 TEST VPP ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR15 ADDR14 ADDR13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA15 DATA14 DATA13 PB4 PB3 PB2 PB1 PB0 PB7 PB6 PB5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 ADDR7 ADDR6 ADDR5 DATA4 DATA3 DATA2 DATA1 DATA0 DATA7 DATA6 DATA5 PE3 PE4 PE5 PE6 PE7 PE0 PE1 PE2 DDRA DDRB PTA PTB DDRE PTE Cloc...

Page 28: ...4 020 02F CORE DBG 16 030 033 CORE PPAGE1 NOTES 1 External memory paging is not supported on this device 6 1 1 PPAGE 4 034 03F Clock and Reset Generator CRG 12 040 06F Standard Timer Module16 bit 8 channels TIM 48 070 07F Reserved 16 080 09F Analog to Digital Convert ATD 32 0A0 0C7 Reserved 40 0C8 0CF Serial Communications Interface SCI 8 0D0 0D7 Reserved 8 0D8 0DF Serial Peripheral Interface SPI ...

Page 29: ...h EEPROM 8000 BFFF 16K Page Window 8 16K Flash EEPROM Pages 4000 7FFF 16K Fixed Flash EEPROM 3000 3FFF 0000 03FF 1K Register Space Mappable to any 2K Boundary Mappable to any 4K Boundary 4K Bytes RAM 3000 The figure shows a useful map which is not the map out of reset After reset the map is 0000 03FF Register Space 0000 0FFF 4K RAM only 3K visible 0400 0FFF 0000 3FFF 16K Fixed Flash EEPROM VECTORS...

Page 30: ... 8000 BFFF 16K Page Window 6 16K Flash EEPROM Pages 4000 7FFF 16K Fixed Flash EEPROM 3000 3FFF 0000 03FF 1K Register Space Mappable to any 2K Boundary Mappable to any 4K Boundary 4K Bytes RAM 3000 The figure shows a useful map which is not the map out of reset After reset the map is 0000 03FF Register Space 0000 0FFF 4K RAM only 3K visible 0400 0FFF 0000 3FFF 16K Fixed Flash EEPROM VECTORS Flash E...

Page 31: ... EEPROM 8000 BFFF 16K Page Window 4 16K Flash EEPROM Pages 4000 7FFF 16K Fixed Flash EEPROM 3000 3FFF 0000 03FF 1K Register Space Mappable to any 2K Boundary Mappable to any 4K Boundary 4K Bytes RAM 3000 The figure shows a useful map which is not the map out of reset After reset the map is 0000 03FF Register Space 0000 0FFF 4K RAM only 3K visible 0400 0FFF 0000 3FFF 16K Fixed Flash EEPROM VECTORS ...

Page 32: ...F00 FFFF BDM If Active C000 FFFF 16K Fixed Flash EEPROM 8000 BFFF 16K Page Window 2 16K Flash EEPROM Pages 3800 3FFF 0000 03FF 1K Register Space Mappable to any 2K Boundary Mappable to any 2K Boundary 2K Bytes RAM 3800 The figure shows a useful map which is not the map out of reset After reset the map is 0000 03FF Register Space 0800 0FFF 2K RAM VECTORS Flash Erase Sector Size is 512 Bytes PAGE MA...

Page 33: ...FF00 EXT NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE CHIP VECTORS VECTORS FF00 FFFF BDM If Active C000 FFFF 16K Fixed Flash EEPROM 3800 3FFF 0000 03FF 1K Register Space Mappable to any 2K Boundary Mappable to any 2K Boundary 2K Bytes RAM 3800 The figure shows a useful map which is not the map out of reset After reset the map is 0000 03FF Register Space 0800 0FFF 2K RAM VECTORS Flash Erase Sector Si...

Page 34: ... 0 0 0 0 0 Write 0008 PORTE Read Bit 7 6 5 4 3 2 Bit 1 Bit 0 Write 0009 DDRE Read Bit 7 6 5 4 3 Bit 2 0 0 Write 000A PEAR Read NOACCE 0 PIPOE NECLK LSTRE RDWE 0 0 Write 000B MODE Read MODC MODB MODA 0 IVIS 0 EMK EME Write 000C PUCR Read PUPKE 0 0 PUPEE 0 0 PUPBE PUPAE Write 000D RDRIV Read RDPK 0 0 RDPE 0 0 RDPB RDPA Write 000E EBICTL Read 0 0 0 0 0 0 0 ESTR Write 000F Reserved Read 0 0 0 0 0 0 0 ...

Page 35: ...017 MMC map 2 of 4 HCS12 Module Mapping Control Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0017 Reserved Read 0 0 0 0 0 0 0 0 Write Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0018 Reserved Read 0 0 0 0 0 0 0 0 Write Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0019 VREGCTRL Read 0 0 0 0 0 LVDS LVIE LVIF Write 001A 001B Miscellaneous Peripherals D...

Page 36: ...6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0 Write 0020 002F DBG including BKP map 1 of 1 HCS12 Debug Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0020 DBGC1 read DBGEN ARM TRGSEL BEGIN DBGBRK 0 CAPMOD write 0021 DBGSC read AF BF CF 0 TRG write 0022 DBGTBH read Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 write 0023 DBGTBL read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 write 00...

Page 37: ...applicable in special emulation only bond outs for emulation of extended memory map Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0033 DDRK 1 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0034 003F CRG Clock and Reset Generator Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0034 SYNR Read 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 Write 0035 REFDV Read 0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0 Write 0036 CTFLG TEST ONLY...

Page 38: ...C7M2 OC7M1 OC7M0 Write 0043 OC7D Read OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 Write 0044 TCNT hi Read Bit 15 14 13 12 11 10 9 Bit 8 Write 0045 TCNT lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0046 TSCR1 Read TEN TSWAI TSFRZ TFFCA 0 0 0 0 Write 0047 TTOV Read TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 Write 0048 TCTL1 Read OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 Write 0049 TCTL2 Read OM3 OL3 OM2 OL2 OM1 OL1...

Page 39: ...rite 005A TC5 hi Read Bit 15 14 13 12 11 10 9 Bit 8 Write 005B TC5 lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 005C TC6 hi Read Bit 15 14 13 12 11 10 9 Bit 8 Write 005D TC6 lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 005E TC7 hi Read Bit 15 14 13 12 11 10 9 Bit 8 Write 005F TC7 lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0060 PACTL Read 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI Write 0061 PAFLG Read 0 0 0 0 0 0 PAOVF ...

Page 40: ...it 8 Channel Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0080 ATDCTL0 Read 0 0 0 0 0 0 0 0 Write 0081 ATDCTL1 Read 0 0 0 0 0 0 0 0 Write 0082 ATDCTL2 Read ADPU AFFC AWAI ETRIGLE ETRIGP ETRIG ASCIE ASCIF Write 0083 ATDCTL3 Read 0 S8C S4C S2C S1C FIFO FRZ1 FRZ0 Write 0084 ATDCTL4 Read SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 Write 0085 ATDCTL5 Read DJM DSGN SCAN MULT 0 CC CB CA Writ...

Page 41: ... 13 12 11 10 9 Bit8 Write 0095 ATDDR2L Read Bit7 Bit6 0 0 0 0 0 0 Write 0096 ATDDR3H Read Bit15 14 13 12 11 10 9 Bit8 Write 0097 ATDDR3L Read Bit7 Bit6 0 0 0 0 0 0 Write 0098 ATDDR4H Read Bit15 14 13 12 11 10 9 Bit8 Write 0099 ATDDR4L Read Bit7 Bit6 0 0 0 0 0 0 Write 009A ATDDR5H Read Bit15 14 13 12 11 10 9 Bit8 Write 009B ATDDR5L Read Bit7 Bit6 0 0 0 0 0 0 Write 009C ATDDR6H Read Bit15 14 13 12 1...

Page 42: ...0 BRK13 TXDIR RAF Write 00CE SCIDRH Read R8 T8 0 0 0 0 0 0 Write 00CF SCIDRL Read R7 R6 R5 R4 R3 R2 R1 R0 Write T7 T6 T5 T4 T3 T2 T1 T0 00D0 00D7 Reserved Read 0 0 0 0 0 0 0 0 Write 00D8 00DF SPI Serial Peripheral Interface Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00D8 SPICR1 Read SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE Write 00D9 SPICR2 Read 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC...

Page 43: ...E8 PWMSCLA Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00E9 PWMSCLB Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00EA PWMSCNTA Read 0 0 0 0 0 0 0 0 Write 00EB PWMSCNTB Read 0 0 0 0 0 0 0 0 Write 00EC PWMCNT0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0 0 0 0 0 0 0 0 00ED PWMCNT1 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0 0 0 0 0 0 0 0 00EE PWMCNT2 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0 0 0 0 0 0 0 0 00EF PWMCNT3 Read Bit 7 6 5 4 3 ...

Page 44: ...LKDIV Read FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 Write 0101 FSEC Read KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0 Write 0102 FTSTMOD Read 0 0 0 WRALL 0 0 0 0 Write 0103 FCNFG Read CBEIE CCIE KEYACC 0 0 0 BKSEL1 BKSEL0 Write 0104 FPROT Read FPOPEN NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 Write 0105 FSTAT Read CBEIF CCIF PVIOL ACCERR 0 BLANK 0 0 Write 0106 FCMD Read 0 CMDB6 CMDB5 0 0 CMDB2 ...

Page 45: ...BRP3 BRP2 BRP1 BRP0 Write 0143 CANBTR1 Read SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Write 0144 CANRFLG Read WUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF Write 0145 CANRIER Read WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE Write 0146 CANTFLG Read 0 0 0 0 0 TXE2 TXE1 TXE0 Write 0147 CANTIER Read 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 Write 0148 CANTARQ Read 0 0 0 0 0 ABTRQ2 ABT...

Page 46: ...ress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 xxx0 Extended ID Read ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 Standard ID Read ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 CANxRIDR0 Write xxx1 Extended ID Read ID20 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 Standard ID Read ID2 ID1 ID0 RTR IDE 0 CANxRIDR1 Write xxx2 Extended ID Read ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 Standard ID Read CANxRIDR2 Write xxx...

Page 47: ...te xx1E CANxTTSRH Read TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 Write xx1F CANxTTSRL Read TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 Write 0180 023F Reserved Read 0 0 0 0 0 0 0 0 Write 0240 PTT Read PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 Write 0241 PTIT Read PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 Write 0242 DDRT Read DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 Write 0243 RDRT Read ...

Page 48: ...DRM1 RDRM0 Write 0254 PERM Read 0 0 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 Write 0255 PPSM Read 0 0 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 Write 0256 WOMM Read 0 0 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 Write 0257 Reserved Read 0 0 0 0 0 0 0 0 Write 0258 PTP Read PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 Write 0259 PTIP Read PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 Write 025A DDRP Read DDRP7 DDRP7 DDR...

Page 49: ... 0 0 0 Write 026C PERJ Read PERJ7 PERJ6 0 0 0 0 0 0 Write 026D PPSJ Read PPSJ7 PPSJ6 0 0 0 0 0 0 Write 026E PIEJ Read PIEJ7 PIEJ6 0 0 0 0 0 0 Write 026F PIFJ Read PIFJ7 PIFJ6 0 0 0 0 0 0 Write 0270 PTAD Read PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 Write 0271 PTIAD Read PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIJ7 Write 0272 DDRAD Read DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDR...

Page 50: ... space Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0280 2FF Reserved Read 0 0 0 0 0 0 0 0 Write 0300 03FF Unimplemented Read 0 0 0 0 0 0 0 0 Write Table 1 3 Assigned Part ID Numbers Device Mask Set Number Part ID1 NOTES 1 The coding is as follows Bit 15 12 Major family identifier Bit 11 8 Minor family identifier Bit 7 4 Major mask set revision number including FAB transfers Bit 3 ...

Page 51: ...D V01 05 51 MC9S12C32 MC9S12GC32 MEMSIZ0 00 MEMSIZ1 80 MC9S12C64 MC9S12GC64 MEMSIZ0 01 MEMSIZ1 C0 MC9S12C96 MEMSIZ0 01 MEMSIZ1 C0 MC9S12C128 MC9S12GC128 MEMSIZ0 01 MEMSIZ1 C0 Table 1 4 Memory size registers Device Register name Value ...

Page 52: ...PP5 KWP5 PW5 PP7 KWP7 VDDX VSSX PM0 RXCAN PM1 TXCAN PM2 MISO PM3 SS PM4 MOSI PM5 SCK PJ6 KWJ6 PJ7 KWJ7 PP6 KWP6 ROMCTL PS3 PS2 PS1 TXD PS0 RXD VSSA VRL PW3 KWP3 PP3 PW2 KWP2 PP2 PW1 KWP1 PP1 PW0 KWP0 PP0 PW0 IOC0 PT0 PW1 IOC1 PT1 PW2 IOC2 PT2 PW3 IOC3 PT3 VDD1 VSS1 PW4 IOC4 PT4 IOC5 PT5 IOC6 PT6 IOC7 PT7 MODC TAGHI BKGD ADDR0 DATA0 PB0 ADDR1 DATA1 PB1 ADDR2 DATA2 PB2 ADDR3 DATA3 PB3 ADDR4 DATA4 PB...

Page 53: ... in Bold italic are not available on the 48 Pin Package PP4 KWP4 PW4 PP5 KWP5 PW5 VDDX VSSX PM0 RXCAN PM1 TXCAN PM2 MISO PM3 SS PM4 MOSI PM5 SCK PS1 TXD PS0 RXD VSSA VRH VDDA PAD07 AN07 PAD06 AN06 PAD05 AN05 PAD04 AN04 PAD03 AN03 PAD02 AN02 PAD01 AN01 PAD00 AN00 PA2 PA1 PA0 XCLKS PE7 ECLK PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST VPP IRQ PE1 XIRQ PE0 PW3 KWP3 PP3 PW0 IOC0 PT0 PW1 IOC1 ...

Page 54: ...7 46 45 44 43 42 41 40 39 38 37 PP5 KWP5 PW5 VDDX VSSX PM0 RXCAN PM1 TXCAN PM2 MISO PM3 SS PM4 MOSI PM5 SCK PS1 TXD PS0 RXD VSSA PW0 IOC0 PT0 PW1 IOC1 PT1 PW2 IOC2 PT2 PW3 IOC3 PT3 VDD1 VSS1 PW4 IOC4 PT4 IOC5 PT5 IOC6 PT6 IOC7 PT7 MODC BKGD PB4 XCLKS PE7 ECLK PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST VPP IRQ PE1 VRH VDDA PAD07 AN07 PAD06 AN06 PAD05 AN05 PAD04 AN04 PAD03 AN03 PAD02 AN02...

Page 55: ...Port E I O pin R W in expanded modes PE1 IRQ VDDX PUCR Up Port E input external interrupt pin PE0 XIRQ VDDX PUCR Up Port E input non maskable interrupt pin PA 7 3 ADDR 15 1 DATA 15 1 VDDX PUCR Disabled Port A I O pin multiplexed address data PA 2 1 ADDR 10 9 DATA 10 9 VDDX PUCR Disabled Port A I O pin multiplexed address data PA 0 ADDR 8 DATA 8 VDDX PUCR Disabled Port A I O pin multiplexed address...

Page 56: ...Port M I O Pin and SPI SS signal PM2 MISO VDDX PERM PPSM Up Port M I O Pin and SPI MISO signal PM1 TXCAN VDDX PERM PPSM Up Port M I O Pin and CAN transmit signal2 PM0 RXCAN VDDX PERM PPSM Up Port M I O Pin and CAN receive signal2 PS 3 2 VDDX PERS PPSS Up Port S I O Pins PS1 TXD VDDX PERS PPSS Up Port S I O Pin and SCI transmit signal PS0 RXD VDDX PERS PPSS Up Port S I O Pin and SCI receive signal ...

Page 57: ...e RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one within 32 ECLK cycles after the low drive is released Upon detection of any reset an internal circuit drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal processing 2 3 3 TEST VPP Test Pin This pin is reserved for test and mus...

Page 58: ...neral purpose input or output pins In MCU expanded modes of operation these pins are used for the multiplexed external address and data bus PB 7 5 and PB 3 0 pins are not available in the 48 nor 52 pin package version 2 3 8 PE7 NOACC XCLKS Port E I O Pin 7 PE7 is a general purpose input or output pin During MCU expanded modes of operation the NOACC signal when enabled is used to indicate that the ...

Page 59: ...L ceramic resonator C1 CDC Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal Please contact the crystal manufacturer for crystal DC MCU EXTAL XTAL RS RB VSSPLL Crystal or ceramic resonator C2 C1 Rs can be zero shorted when use with higher frequency crystals Refer to manufacturer s data MCU EXTAL XTAL CMOS COMPATIBLE EXTERNAL OSCILLATOR not con...

Page 60: ...he NECLK bit in the PEAR register the IVIS bit in the MODE register and the ESTR bit in the EBICTL register All clocks including the E clock are halted when the MCU is in STOP mode It is possible to configure the MCU to interface to slow external memory ECLK can be stretched for such accesses Reference the MISC register EXSTR 1 0 bits for more information In normal expanded narrow mode the E clock...

Page 61: ... PUCR register 2 3 16 PAD 7 0 AN 7 0 Port AD I O Pins 7 0 PAD7 PAD0 are general purpose I O pins and also analog inputs for the analog to digital converter In order to use a PAD pin as a standard I O the corresponding ATDDIEN register bit must be set These bits are cleared out of reset to configure the PAD pins for A D operation When the A D converter is active in multi channel mode port inputs ar...

Page 62: ...ion 2 3 21 PM5 SCK Port M I O Pin 5 PM5 is a general purpose input or output pin and also the serial clock pin SCK for the Serial Peripheral Interface SPI 2 3 22 PM4 MOSI Port M I O Pin 4 PM4 is a general purpose input or output pin and also the master output during master mode or slave input during slave mode pin for the Serial Peripheral Interface SPI 2 3 23 PM3 SS Port M I O Pin 3 PM3 is a gene...

Page 63: ...OC 4 0 PW 4 0 Port T I O Pins 4 0 PT4 PT0 are general purpose input or output pins They can also be configured as the timer system input capture or output compare pins IOC4 IOC0 or as the PWM outputs PW 4 0 2 4 Power Supply Pins 2 4 1 VDDX VSSX Power Ground Pins for I O Drivers External power and ground for I O drivers Bypass requirements depend on how heavily the MCU pins are loaded 2 4 2 VDDR VS...

Page 64: ...d place them as close to the MCU as possible Bypass requirements depend on MCU pin load Section 3 System Clock Description Mnemonic Nominal Voltage Description VDD1 VDD2 2 5 V Internal power and ground generated by internal regulator These also allow an external source to supply the core VDD VSS voltages and bypass the internal voltage regulator In the 48 and 52 LQFP packages VDD2 and VSS2 are not...

Page 65: ...ion of the MC9S12C Family Each mode has an associated default memory map and external bus configuration controlled by a further pin Three low power modes exist for the device 4 2 Chip Configuration Summary The operating mode out of reset is determined by the states of the MODC MODB and MODA pins during reset The MODC MODB and MODA bits in the MODE register show the current operating mode and provi...

Page 66: ...security must lie with the user s code An extreme example would be user s code that dumps the contents of the internal program This code would defeat the purpose of security At the same time the user may also wish to put a back door in the user s program An example Table 4 1 Mode Selection BKGD MODC PE6 MODB PE5 MODA PP6 ROMCTL ROMON Bit Mode Description 0 0 0 X 1 Special Single Chip BDM allowed a...

Page 67: ...SH will be disabled BDM operations will be blocked 4 3 3 Unsecuring the Microcontroller In order to unsecure the microcontroller the internal FLASH must be erased This can be done through an external program in expanded mode or via a sequence of BDM commands Unsecuring is also possible via the Backdoor Key Access Refer to Flash Block Guide for details Once the user has erased the FLASH the part ca...

Page 68: ...ignals address and databus will be fully static All peripherals stay active For further power consumption reduction the peripherals can individually turn off their local clocks 4 4 4 Run Although this is not a low power mode unused peripheral modules should not be enabled in order to save power Section 5 Resets and Interrupts 5 1 Overview Consult the Exception Processing section of the CPU12 Refer...

Page 69: ...FDE FFDF Standard Timer overflow I Bit TMSK2 TOI DE FFDC FFDD Pulse accumulator A overflow I Bit PACTL PAOVI DC FFDA FFDB Pulse accumulator input edge I Bit PACTL PAI DA FFD8 FFD9 SPI I Bit SPICR1 SPIE SPTIE D8 FFD6 FFD7 SCI I Bit SCICR2 TIE TCIE RIE ILIE D6 FFD4 FFD5 Reserved FFD2 FFD3 ATD I Bit ATDCTL2 ASCIE D2 FFD0 FFD1 Reserved FFCE FFCF Port J I Bit PIEP PIEP7 6 CE FFCC FFCD Reserved FFCA FFC...

Page 70: ...igured as outputs after reset in order to avoid current drawn from floating inputs Refer to Table 2 1 for affected pins Section 6 HCS12 Core Block Description Consult the individual block guides for information about the HCS12 core modules i e central processing unit CPU interrupt module INT module mapping control module MMC multiplexed external bus interface MEBI debug12 module DBG12 and backgrou...

Page 71: ...e of PUPKE in the PUCR register is 1 enabling the internal PortK pullups In this reset state the pull ups provide a defined state and prevent a floating input thereby preventing unnecessary current flow at the input stage Device PAGE PAGE visible with PPAGE contents MC9S12GC16 3F 00 01 02 03 04 05 06 07 08 09 36 37 38 39 3A 3B 3C 3D 3E 3F MC9S12C32 MC9S12GC32 3E 00 02 04 06 08 0A 0C 0E 10 12 2C 2E...

Page 72: ...rnally The extra pin pair enables systems using the 80 pin package to employ better supply routing and further decoupling Section 8 Recommended Printed Circuit Board Layout The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself The following rules must be observed Every supply pair must be decoupled by a ceramic capacitor connected as ne...

Page 73: ...pacitor ceramic X7R 100nF C4 VDDR filter capacitor X7R tantalum 100nF C5 VDDPLL filter capacitor ceramic X7R 100nF C6 VDDX filter capacitor X7R tantalum 100nF C7 OSC load capacitor See PLL specification chapter C8 OSC load capacitor C9 PLL loop filter capacitor See PLL specification chapter C10 PLL loop filter capacitor C11 DC cutoff capacitor Colpitts mode only if recommended by quartz manufactur...

Page 74: ...ce User Guide 9S12C128DGV1 D V01 05 74 Figure 8 1 Recommended PCB Layout 48 LQFP C5 C4 C1 C6 C3 C8 C7 Q1 C10 C9 R1 VDDX VSSX VDDR VSSR VDD1 VSS1 VDDPLL VSSPLL VDDA VSSA C11 Oscillator in Note Colpitts mode ...

Page 75: ...ce User Guide 9S12C128DGV1 D V01 05 75 Figure 8 2 Recommended PCB Layout 52 LQFP C4 C1 C6 C8 C7 Q1 C10 C9 R1 VDDX VSSX VDDR VSSR VDD1 VSS1 VDDPLL VSSPLL VDDA VSSA C11 NOTE Oscillator in Colpitts mode C3 C5 ...

Page 76: ...r Guide 9S12C128DGV1 D V01 05 76 Figure 8 3 Recommended PCB Layout 80 QFP VDDA C5 C4 C8 C7 Q1 C10 C9 R1 VDDR VSSR VDDPLL VSSPLL C11 C6 C3 VDDX VSSX VSSA C1 VDD1 VSS1 C2 VDD2 VSS2 NOTE Oscillator in Colpitts mode ...

Page 77: ...Device User Guide 9S12C128DGV1 D V01 05 77 Figure 8 4 Recommended PCB Layout for 48 LQFP Pierce Oscillator C4 C1 C6 VDDX VSSX VDDR VSSR VDD1 VSS1 VDDA VSSA C3 C5 C10 C9 R1 VSSPLL VDDPLL R2 C7 R3 C8 Q1 ...

Page 78: ...Device User Guide 9S12C128DGV1 D V01 05 78 Figure 8 5 Recommended PCB Layout for 52 LQFP Pierce Oscillator C4 C1 C6 VDDX VSSX VDDR VSSR VDD1 VSS1 VDDA VSSA C3 C5 C10 C9 R1 VSSPLL VDDPLL R2 C7 R3 C8 Q1 ...

Page 79: ...Clock Reset Generator CRG Block Description Consult the CRG Block User Guide for information about the Clock and Reset Generator module 9 1 Device specific information The CRG is part of the IPBus domain C5 C4 C3 C2 C10 C9 R1 C6 C1 VDD1 VSS1 VSS2 VDD2 VSSR VDDR VSSPLL VDDPLL VDDA VSSA VSSX VDDX R2 C7 R3 C8 Q1 VSSPLL ...

Page 80: ...ion about the Oscillator module Section 11 Timer TIM Block Description Consult the TIM_16B8C Block User Guide for information about the Timer module Section 12 Analog to Digital Converter ATD Block Description 12 1 Device specific information 12 1 1 VRL voltage reference low In the 48 and 52 pin package versions the VRL pad is bonded internally to the VSSA pin Consult the ATD_10B8C Block User Guid...

Page 81: ...TS128K Block User Guide for information about the Flash module for the MC9S12C128or MC9S12GC128 Section 16 RAM Block Description This module supports single cycle misaligned word accesses without wait states The MC912GC16 features a single 1K byte RAM module The MC9S12C32 and MC9S12GC32 feature a 2K byte RAM module The MC9S12C64 MC9S12GC64 MC9S12C96 MC9S12C128 and MC9S12GC128 versions feature a 4K...

Page 82: ...er within the PIM allows for mapping of PWM channels to PortT in the absence of PortP pins for the low pin count packages For the 80QFP package option it is recommended not to use MODRR since this is intended to support PWM channel availability in low pin count packages Note that when mapping PWM channels to PortT in an 80QFP option the associated PWM channels are then mapped to both PortP and Por...

Page 83: ...ive the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate NOTE This classification will be added at a later release of the specification P Those parameters are guaranteed during production testing on each individual device C Those parameters are achieved by the design characterization by measuring a statis...

Page 84: ...pins is identical however some of the functionality may be disabled E g pull up and pull down resistors may be disabled permanently A 1 3 2 Analog Reference This class is made up by the two VRH and VRL pins In 48 and 52 pin package versions the VRL pad is bonded to the VSSA pin A 1 3 3 Oscillator The pins XFC EXTAL XTAL dedicated to the oscillator have a nominal 2 5V level They are supplied by VDD...

Page 85: ...ate the logic and PLL supply out of the I O supply The absolute maximum ratings apply when the device is powered from an external source VDD 0 3 3 0 V 3 PLL Supply Voltage 1 VDDPLL 0 3 3 0 V 4 Voltage difference VDDX to VDDR and VDDA VDDX 0 3 0 3 V 5 Voltage difference VSSX to VSSR and VSSA VSSX 0 3 0 3 V 6 Digital I O Input Voltage VIN 0 3 6 5 V 7 Analog Reference VRH VRL 0 3 6 5 V 8 XFC EXTAL XT...

Page 86: ...n A 1 7 Operating Conditions This chapter describes the operating conditions of the devices Unless otherwise noted those conditions apply to all the following data Table A 2 ESD and Latch up Test Conditions Model Description Symbol Value Unit Human Body Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF Number of Pulse per pin positive negative 3 3 Machine Series Resistance R1 0 Ohm Storag...

Page 87: ...g Supply Voltage VDD5 2 97 5 5 5 V Digital Logic Supply Voltage1 NOTES 1 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source VDD 2 35 2 5 2 75 V PLL Supply Voltage 1 VDDPLL 2 35 2 5 2 75 V Voltage Difference VDDX to VDDA VDDX ...

Page 88: ...For RDSON is valid respectively 2 Internal voltage regulator enabled IDDR is the current shown in Table A 8 and not the overall current flowing into VDDR which additionally contains the current flowing into the external loads with output high P INT I DD V DD I DDPLL V DDPLL I DDA V DDA P IO R DSON i I IOi 2 R DSON V OL I OL for outputs driven low R DSON V DD5 V OH I OH for outputs driven high P IN...

Page 89: ...ance LQFP48 double sided PCB with 2 internal planes3 3 PC Board according to EIA JEDEC Standard 51 7 θJA 53 o C W 3 T Junction to Board LQFP48 θJB 30 oC W 4 T Junction to Case LQFP48 θJC 20 o C W 5 T Junction to Package Top LQFP48 ΨJT 4 o C W 6 T Thermal Resistance LQFP52 single sided PCB θJA 65 o C W 7 T Thermal Resistance LQFP52 double sided PCB with 2 internal planes θJA 49 o C W 8 T Junction t...

Page 90: ... Drive IOH 2mA V OH VDD5 0 8 V 6 P Output High Voltage pins in output mode Full Drive IOH 10mA VOH VDD5 0 8 V 7 C Output Low Voltage pins in output mode Partial Drive IOL 2mA VOL 0 8 V 8 P Output Low Voltage pins in output mode Full Drive IOL 10mA V OL 0 8 V 9 P Internal Pull Up Device Current tested at V IL Max IPUL 130 µA 10 C Internal Pull Up Device Current tested at V IH Min IPUH 10 µA 11 P In...

Page 91: ...Drive IOH 0 75mA V OH VDD5 0 4 V 6 P Output High Voltage pins in output mode Full Drive IOH 4mA V OH VDD5 0 4 V 7 C Output Low Voltage pins in output mode Partial Drive IOL 0 9mA V OL 0 4 V 8 P Output Low Voltage pins in output mode Full Drive IOL 4 75mA V OL 0 4 V 9 P Internal Pull Up Device Current tested at V IL Max IPUL 60 µA 10 C Internal Pull Up Device Current tested at VIH Min IPUH 6 µA 11 ...

Page 92: ...ted the currents are measured in single chip mode internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator A 1 10 2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address data and control signals as well as on the duty cycle of those signals No generally applicable numbers can be given A very good estimat...

Page 93: ...tion 140 C IDDPS 1 NOTES 1 STOP current measured in production test at increased junction temperature hence for Temp Option C the test is carried out at 100 C although the Temperature specification is 85 C Similarly for v and M options the temperature used in test lies 15 C above the temperature option specification 340 360 500 550 590 720 780 1100 450 1450 1900 4500 µA 4 C C C C C Pseudo Stop Cur...

Page 94: ... M Temp Option 140 C IDDPS 1 NOTES 1 STOP current measured in production test at increased junction temperature hence for Temp Option C the test is carried out at 100 C although the Temperature specification is 85 C Similarly for v and M options the temperature used in test lies 15 C above the temperature option specification 190 200 300 400 450 600 650 1000 250 1400 1900 4800 µA 4 C C C C C Pseud...

Page 95: ...A active only in Full Performance Mode Indicates I O ADC performance degradation due to low supply voltage VLVIA VLVIA VLVID VLVID 4 30 4 10 4 42 4 25 4 53 4 37 4 65 4 52 4 77 4 66 4 89 4 77 V V V V 5 P Low Voltage Reset2 Assert Level C32 GC32 Assert Level C64 C96 C128 GC64 GC128 2 Monitors VDD active only in Full Performance Mode MCU is monitored by the POR in RPM see Figure B 1 VLVRA 2 25 2 25 2...

Page 96: ...p power up or drops of the supply voltage Their function is described in Figure B 1 Figure B 1 Voltage Regulator Chip Power up and Voltage Drops not scaled B 3 Output Loads B 3 1 Resistive Loads The on chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no external DC loads VLVID VLVIA VLVRD VLVRA VPORD LVI POR LVR t V VDDA VDD LVI enabled LVI disabled du...

Page 97: ... are specified in Table B 2 Ceramic capacitors with X7R dielectricum are required Table B 2 Voltage Regulator Capacitive Loads Num Characteristic Symbol Min Typical Max Unit 1 VDD external capacitive load CDDext 400 440 12000 nF 2 VDDPLL external capacitive load CDDPLLext 90 220 5000 nF ...

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Page 99: ...nge The Table B 3 shows conditions under which the ATD operates The following constraints exist to obtain full scale full range results VSSA VRL VIN VRH VDDA This constraint exists since the sample buffer amplifier can not drive Table B 3 ATD Operating Characteristics Conditions are shown in Table A 4 unless otherwise noted Supply Voltage 5V 10 VDDA 5V 10 Num C Rating Symbol Min Typ Max Unit 1 D R...

Page 100: ...capacitor is switched to the input This can cause a voltage drop due to charge sharing with the external and the pin capacitance For a maximum sampling error of the input voltage 1LSB then the external filter capacitor Cf 1024 CINS CINN Table B 4 ATD Operating Characteristics Conditions are shown in Table A 4 unless otherwise noted Supply Voltage 3 3V 10 VDDA 3 3V 10 Num C Rating Symbol Min Typ Ma...

Page 101: ...g ratio K This additional current impacts the accuracy of the conversion depending on the source resistance The additional input voltage error on the converted channel can be calculated as VERR K RS IINJ with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel Table B 5 ATD Electrical Characteristics Conditions are shown in Table A 4 unless otherwise not...

Page 102: ... quantization error which is inherently 1 2 count for any A D converter AE 2 5 2 5 Counts 5 P 8 Bit Resolution LSB 20 mV 6 P 8 Bit Differential Nonlinearity DNL 0 5 0 5 Counts 7 P 8 Bit Integral Nonlinearity INL 1 0 0 5 1 0 Counts 8 P 8 Bit Absolute Error 1 AE 1 5 1 1 5 Counts Table B 7 ATD Conversion Performance Conditions are shown in Table A 4 unless otherwise noted VREF VRH VRL 3 328V Resultin...

Page 103: ...ollowing definitions see also Figure B 2 Differential Non Linearity DNL is defined as the difference between two adjacent switching steps The Integral Non Linearity INL is defined as the sum of all DNLs DNL i Vi Vi 1 1LSB 1 INL n DNL i i 1 n Vn V0 1LSB n ...

Page 104: ...in mV 6 5 9 75 13 16 25 19 5 22 75 26 3305 3309 3312 3315 3318 3321 3324 3328 3292 3295 3299 3302 3289 0 3 2 5 4 7 6 29 25 3F7 3F9 3F8 3FB 3FA 3FD 3FC 3FE 3FF 3F4 3F6 3F5 8 9 1 2 FF FE FD 3F3 10 Bit Resolution 8 Bit Resolution Ideal Transfer Curve 10 Bit Transfer Curve 8 Bit Transfer Curve 3286 10 Bit Absolute Error Boundary 8 Bit Absolute Error Boundary LSB Vi 1 Vi DNL ...

Page 105: ...mes shown in Table B 8 are calculated for maximum fNVMOP and maximum fbus The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz B 5 1 1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency f NVMOP and can be calculated according to the following formula B 5 1 2 Row Programming Generally the time to...

Page 106: ...d Programming times are achieved under particular combinations of f NVMOP and bus frequency f bus Refer to formulae in Sections A 3 1 1 A 3 1 4 for guidance µs 5 D Flash Burst Programming consecutive word tbwpgm 20 42 313 µs 6 D Flash Burst Programming Time for 32 Word row tbrpgm 678 42 1035 53 µs 6 D Flash Burst Programming Time for 64 Word row tbrpgm 1331 22 2027 53 µs 7 P Sector Erase Time tera...

Page 107: ...at the operating conditions noted A program erase cycle is specified as two transitions of the cell value from erased programmed erased 1 0 1 NOTE All values shown in Table B 9 are target values and subject to further extensive characterization Table B 9 NVM Reliability Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 C Data Retention ...

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Page 109: ...assert level VLVRA are derived from the VDD Supply They are also valid if the device is powered externally After releasing the LVR reset the oscillator and the clock quality check are started If after a time tCQOUT no valid oscillation is detected the MCU will start using the internal self clock The fastest startup time possible is given by nuposc B 6 1 3 SRAM Data Retention Provided an appropriat...

Page 110: ... and Wait are essentially the same since the oscillator was not stopped in both modes The controller can be woken up by internal or external interrupts After twrs the CPU starts fetching the interrupt vector B 6 2 Oscillator The device features an internal Colpitts oscillator By asserting the XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave Before assert...

Page 111: ...llator range Colpitts fOSC 0 5 16 MHz 1b C Crystal oscillator range Pierce 1 4 NOTES 1 Depending on the crystal a damping series resistor might be necessary fOSC 0 5 40 MHz 2 P Startup Current iOSC 100 µA 3 C Oscillator start up time Colpitts tUPOSC 82 2 fosc 4MHz C 22pF 1003 3 Maximum value is for extreme cases using high Q low frequency crystals ms 4 D Clock Quality check time out tCQOUT 0 45 2 ...

Page 112: ...bus clock The VCO Gain at the desired VCO frequency is approximated by The phase detector relationship is given by ich is the current in tracking mode The loop bandwidth fC should be chosen to fulfill the Gardner s stability criteria by at least a factor of 10 typical values are 50 ζ 0 9 ensures a good transient response fosc 1 refdv 1 fref Phase Detector VCO KV 1 synr 1 fvco Loop Divider KΦ 1 2 f...

Page 113: ...With each transition of the clock fcmp the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly The adjustment is done continuously with no abrupt changes in the clock output frequency Noise voltage temperature and other factors cause slight variations in the control loop resulting in a clock jitter This jitter affects the real minimum and maximu...

Page 114: ... clock period and decreases towards zero for larger number of clock periods N Defining the jitter as For N 100 the following equation is a good fit for the maximum jitter Figure B 5 Maximum bus clock jitter approximation 2 3 N 1 N 1 0 tnom tmax1 tmin1 tmaxN tminN J N max 1 tmax N N tnom 1 tmin N N tnom J N j1 N j2 1 5 10 20 N J N ...

Page 115: ...t frequency 4 D Lock Detection Lock 0 1 5 1 5 D Un Lock Detection unl 0 5 2 5 1 6 D Lock Detector transition from Tracking to Acquisition mode unt 6 8 1 7 C PLLON Total Stabilization delay Auto Mode 2 2 fOSC 4MHz fBUS 25MHz equivalent fVCO 50MHz REFDV 03 SYNR 018 Cs 4 7nF Cp 470pF Rs 10KΩ tstab 0 5 ms 8 D PLLON Acquisition mode stabilization delay 2 tacq 0 3 ms 9 D PLLON Tracking mode stabilizatio...

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Page 117: ...17 B 7 MSCAN Table B 13 MSCAN Wake up Pulse Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max 1 P MSCAN Wake up dominant pulse filtered tWUP 2 2 P MSCAN Wake up dominant pulse pass tWUP 5 ...

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Page 119: ...SPI Master Timing CPHA 0 In Figure C 2 the timing diagram for master mode with transmission format CPHA 1 is depicted Table C 1 Measurement Conditions Description Value Unit Drive mode full drive mode Load capacitance CLOAD on all outputs 50 pF Thresholds for delay measurement points 20 80 VDDX V SCK OUTPUT SCK OUTPUT MISO INPUT MOSI OUTPUT SS1 OUTPUT 1 9 5 6 MSB IN2 BIT 6 1 LSB IN MSB OUT2 LSB OU...

Page 120: ... Clock SCK High or Low Time twsck 1 2 tsck 5 D Data Setup Time Inputs tsu 8 ns 6 D Data Hold Time Inputs thi 8 ns 9 D Data Valid after SCK Edge tvsck 30 ns 10 D Data Valid after SS fall CPHA 0 tvss 15 ns 11 D Data Hold Time Outputs tho 20 ns 12 D Rise and Fall Time Inputs trfi 8 ns 13 D Rise and Fall Time Outputs trfo 8 ns SCK OUTPUT SCK OUTPUT MISO INPUT MOSI OUTPUT 1 5 6 MSB IN2 BIT 6 1 LSB IN M...

Page 121: ... 0 is depicted Figure C 3 SPI Slave Timing CPHA 0 In Figure C 4 the timing diagram for slave mode with transmission format CPHA 1 is depicted SCK INPUT SCK INPUT MOSI INPUT MISO OUTPUT SS INPUT 1 9 5 6 MSB IN BIT 6 1 LSB IN SLAVE MSB SLAVE LSB OUT BIT 6 1 11 4 4 2 7 CPOL 0 CPOL 1 3 13 NOTE Not defined 12 12 11 SEE 13 NOTE 8 10 see note ...

Page 122: ...Data Setup Time Inputs tsu 8 ns 6 D Data Hold Time Inputs thi 8 ns 7 D Slave Access Time time to data active ta 20 ns 8 D Slave MISO Disable Time tdis 22 ns 9 D Data Valid after SCK Edge tvsck 30 tbus 1 NOTES 1 tbus added due to internal synchronization delay ns 10 D Data Valid after SS fall tvss 30 tbus 1 ns 11 D Data Hold Time Outputs tho 20 ns 12 D Rise and Fall Time Inputs trfi 8 ns 13 D Rise ...

Page 123: ...cycle are shown only one or the other would occur on a particular bus cycle C 3 1 General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions The timing parameters shown assume a balanced load across all outputs Figure C 5 General External Bus Timing Addr Data read Addr Data write addr data data 5 10 11 8 16 6 ECLK 1 2 3 4 addr data data 12 15 9 7 14 13 LSTRB 22 N...

Page 124: ...D Write data hold time tDHW 2 ns 14 D Write data setup time 1 PWEH tDDW tDSW 12 ns 15 D Address access time 1 tcyc tAD tDSR tACCA 19 ns 16 D E high access time 1 PWEH tDSR tACCE 6 ns 17 D Read write delay time tRWD 7 ns 18 D Read write valid time to E rise PWEL tRWD tRWV 14 ns 19 D Read write hold time tRWH 2 ns 20 D Low strobe delay time tLSD 7 ns 21 D Low strobe valid time to E rise PWEL tLSD tL...

Page 125: ...W 15 ns 13 D Write data hold time tDHW 2 ns 14 D Write data setup time 1 PWEH tDDW tDSW 15 ns 15 D Address access time 1 tACCA 29 ns 16 D E high access time 1 PWEH tDSR tACCE 15 ns 17 D Read write delay time tRWD 14 ns 18 D Read write valid time to E rise PWEL tRWD tRWV 16 ns 19 D Read write hold time tRWH 2 ns 20 D Low strobe delay time tLSD 14 ns 21 D Low strobe valid time to E rise PWEL tLSD tL...

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Page 127: ...evice User Guide 9S12C128DGV1 D V01 05 127 Appendix D Package Information D 1 General This section provides the physical dimensions of the MC9S12C Family and MC9S12GC Family packages 48LQFP 52LQFP 80QFP ...

Page 128: ...E DETERMINED AT DATUM PLANE H 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT SECTION B B 61 60 DETAIL A L 41 40 80 A L D A S A B M 0 20 D S H 0 05 A B S 1 20 21 B B V J F N D VIEW ROTATED 90 DETAIL A B B P A B D E H G M M DETAIL C SEA...

Page 129: ...MUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0 07 0 003 VIEW AA AB AB VIEW Y SECTION AB AB ROTATED 90 CLOCKWISE DIM A MIN MAX MIN MAX INCHES 10 00 BSC 0 394 BSC MILLIMETERS A1 5 00 BSC 0 197 BSC B 10 00 BSC 0 394 BSC B1 5 00 BSC 0 197 BSC C 1 70 0 067 C1 0 05 0 20 0 002 0 008 C2 1 30 1 50 0 051 0 059 D 0 20 0 40 0 008 0 016 E 0 45 0 030 F 0 22 0 35 0 009 0 014 G 0 65 BSC 0 75 0 018...

Page 130: ... T U AND Z TO BE DETERMINED AT DATUM PLANE AB 4 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC 5 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 250 PER SIDE DIMENSIONS AANDBDOINCLUDEMOLDMISMATCHAND ARE DETERMINED AT DATUM PLANE AB 6 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0 350 7 MINIMUM SOLDER...

Page 131: ...6 PJ7 KWJ7 NC NC PP6 KWP6 ROMONE NC NC PS3 PS2 PS1 TXD PS0 RXD NC NC VSSA VRL PW3 KWP3 PP3 PW2 KWP2 PP2 PW1 KWP1 PP1 PW0 KWP0 PP0 NC XADDR16 PK2 XADDR15 PK1 XADDR14 PK0 IOC0 PT0 IOC1 PT1 IOC2 PT2 IOC3 PT3 VDD1 VSS1 IOC4 PT4 IOC5 PT5 IOC6 PT6 IOC7 PT7 NC NC NC NC MODC TAGHI BKGD ADDR0 DATA0 PB0 ADDR1 DATA1 PB1 ADDR2 DATA2 PB2 ADDR3 DATA3 PB3 ADDR4 DATA4 PB4 ADDR5 DATA5 PB5 ADDR6 DATA6 PB6 ADDR7 DAT...

Page 132: ...is 00 configuring the pins as inputs The reset state of PUPKE in the PUCR register of the S12_CORE is 1 enabling the internal pullup resistors at PortK 2 0 In this reset state the pull up resistors provide a defined state and prevent a floating input thereby preventing unneccesary current consumption at the input stage Pin Name Function 1 Pin Name Function 2 Power Domain Internal Pull Resistor Des...

Page 133: ...DENT 1 112 85 84 28 57 29 56 B V V1 B1 A1 S1 A S VIEW AB 0 10 3 C C2 θ 2 θ 0 050 SEATING PLANE GAGE PLANE 1 θ θ VIEW AB C1 Z Y E K R2 R1 0 25 J1 VIEW Y J1 P G 108X 4X SECTION J1 J1 BASE ROTATED 90 COUNTERCLOCKWISE METAL J AA F D L M M 0 13 N T 1 2 3 C L L M 0 20 N T L N M T T 112X X X L M OR N R R NOTES 1 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 2 DIMENSIONS IN MILLIMETERS 3 DATUMS L M AN...

Page 134: ...Device User Guide 9S12C128DGV1 D V01 05 134 ...

Page 135: ...Device User Guide 9S12C128DGV1 D V01 05 135 Device User Guide End Sheet ...

Page 136: ...Device User Guide 9S12C128DGV1 D V01 05 136 FINAL PAGE OF 136 PAGES ...

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