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Motorola MC68HC908GP32 Technical Data Manual Download Page 270

Serial Communications Interface Module (SCI)

Technical Data

MC68HC908GP32

•

MC68HC08GP32

 — 

Rev. 6

268

Serial Communications Interface Module (SCI)

MOTOROLA

18.9.4  SCI Status Register 1 

SCI status register 1 (SCS1) contains flags to signal these conditions:

•

Transfer of SCDR data to transmit shift register complete

•

Transmission complete

•

Transfer of receive shift register data to SCDR complete

•

Receiver input idle

•

Receiver overrun

•

Noisy data

•

Framing error

•

Parity error

SCTE — SCI Transmitter Empty Bit

This clearable, read-only bit is set when the SCDR transfers a 
character to the transmit shift register. SCTE can generate an SCI 
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, 
SCTE generates an SCI transmitter CPU interrupt request. In normal 
operation, clear the SCTE bit by reading SCS1 with SCTE set and 
then writing to SCDR. Reset sets the SCTE bit.

1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register

Address:

$0016

Bit  7

6

5

4

3

2

1

Bit  0

Read:

SCTE

TC

SCRF

IDLE

OR

NF

FE

PE

Write:

Reset:

1

1

0

0

0

0

0

0

= Unimplemented

Figure 18-12. SCI Status Register 1 (SCS1)

 

   

  

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Freescale Semiconductor, Inc.

For More Information On This Product,

   Go to: www.freescale.com

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Summary of Contents for MC68HC908GP32

Page 1: ...DUCTORS M68HC08 Microcontrollers MC68HC908GP32 H Rev 6 8 2002 MC68HC908GP32 MC68HC08GP32 Technical Data Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 2: ...Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 3: ...igned intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized applicati...

Page 4: ...ppropriate location Revision History Date Revision Level Description Page Number s August 2002 6 Section 22 Timer Interface Module TIM Timer discrepancies corrected throughout this section 341 Section 24 Mechanical Specifications Replaced incorrect 44 pin QFP drawing case 824E to case 824A 393 July 2001 5 In Table 15 1 second cell in Comment column corrected PTC to PTC1 199 In Figure 21 2 Timebase...

Page 5: ...ation Register CONFIG 137 Section 9 Computer Operating Properly COP 141 Section 10 Central Processor Unit CPU 147 Section 11 FLASH Memory 165 Section 12 External Interrupt IRQ 175 Section 13 Keyboard Interrupt Module KBI 181 Section 14 Low Voltage Inhibit LVI 189 Section 15 Monitor ROM MON 195 Section 16 Input Output I O Ports 211 Section 17 Random Access Memory RAM 235 Section 18 Serial Communica...

Page 6: ...303 Section 21 Timebase Module TBM 335 Section 22 Timer Interface Module TIM 341 Section 23 Electrical Specifications 365 Section 24 Mechanical Specifications 391 Section 25 Ordering Information 395 Appendix A MC68HC08GP32 397 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 7: ... 6 2 Oscillator Pins OSC1 and OSC2 40 1 6 3 External Reset Pin RST 40 1 6 4 External Interrupt Pin IRQ 40 1 6 5 CGM Power Supply Pins VDDA and VSSA 41 1 6 6 External Filter Capacitor Pin CGMXFC 41 1 6 7 ADC Power Supply Reference Pins VDDAD VREFH and VSSAD VREFL 41 1 6 8 Port A Input Output I O Pins PTA7 KBD7 PTA0 KBD0 41 1 6 9 Port B I O Pins PTB7 AD7 PTB0 AD0 41 1 6 10 Port C I O Pins PTC6 PTC0 ...

Page 8: ...l Converter ADC 59 3 3 1 Wait Mode 59 3 3 2 Stop Mode 59 3 4 Break Module BRK 59 3 4 1 Wait Mode 59 3 4 2 Stop Mode 60 3 5 Central Processor Unit CPU 60 3 5 1 Wait Mode 60 3 5 2 Stop Mode 60 3 6 Clock Generator Module CGM 60 3 6 1 Wait Mode 60 3 6 2 Stop Mode 61 3 7 Computer Operating Properly Module COP 61 3 7 1 Wait Mode 61 3 7 2 Stop Mode 61 3 8 External Interrupt Module IRQ 62 3 8 1 Wait Mode ...

Page 9: ...1 and TIM2 64 3 13 1 Wait Mode 64 3 13 2 Stop Mode 64 3 14 Timebase Module TBM 65 3 14 1 Wait Mode 65 3 14 2 Stop Mode 65 3 15 Exiting Wait Mode 65 3 16 Exiting Stop Mode 67 Section 4 Resets and Interrupts 4 1 Contents 69 4 2 Introduction 70 4 3 Resets 70 4 3 1 Effects 70 4 3 2 External Reset 70 4 3 3 Internal Reset 71 4 3 3 1 Power On Reset 72 4 3 3 2 COP Reset 73 4 3 3 3 Low Voltage Inhibit Rese...

Page 10: ...upt Status Registers 84 4 4 3 1 Interrupt Status Register 1 85 4 4 3 2 Interrupt Status Register 2 85 4 4 3 3 Interrupt Status Register 3 86 Section 5 Analog to Digital Converter ADC 5 1 Contents 87 5 2 Introduction 88 5 3 Features 88 5 4 Functional Description 88 5 4 1 ADC Port I O Pins 89 5 4 2 Voltage Conversion 90 5 4 3 Conversion Time 90 5 4 4 Conversion 90 5 4 5 Accuracy and Precision 91 5 5...

Page 11: ...onal Description 98 6 4 1 Flag Protection During Break Interrupts 100 6 4 2 CPU During Break Interrupts 100 6 4 3 TIM1 and TIM2 During Break Interrupts 100 6 4 4 COP During Break Interrupts 100 6 5 Low Power Modes 100 6 5 1 Wait Mode 100 6 5 2 Stop Mode 101 6 6 Break Module Registers 101 6 6 1 Break Status and Control Register 101 6 6 2 Break Address Registers 102 6 6 3 Break Status Register 103 6...

Page 12: ...ble Signal SIMOSCEN 120 7 5 7 Oscillator Stop Mode Enable Bit OSCSTOPENB 120 7 5 8 Crystal Output Frequency Signal CGMXCLK 121 7 5 9 CGMC Base Clock Output CGMOUT 121 7 5 10 CGMC CPU Interrupt CGMINT 121 7 6 CGMC Registers 121 7 6 1 PLL Control Register 123 7 6 2 PLL Bandwidth Control Register 125 7 6 3 PLL Multiplier Select Register High 127 7 6 4 PLL Multiplier Select Register Low 128 7 6 5 PLL ...

Page 13: ...OP Instruction 143 9 4 3 COPCTL Write 144 9 4 4 Power On Reset 144 9 4 5 Internal Reset 144 9 4 6 Reset Vector Fetch 144 9 4 7 COPD COP Disable 144 9 4 8 COPRS COP Rate Select 144 9 5 COP Control Register 145 9 6 Interrupts 145 9 7 Monitor Mode 145 9 8 Low Power Modes 145 9 8 1 Wait Mode 146 9 8 2 Stop Mode 146 9 9 COP Module During Break Mode 146 Section 10 Central Processor Unit CPU 10 1 Content...

Page 14: ...155 10 7 CPU During Break Interrupts 155 10 8 Instruction Set Summary 156 10 9 Opcode Map 163 Section 11 FLASH Memory 11 1 Contents 165 11 2 Introduction 165 11 3 Functional Description 165 11 4 FLASH Control Register 166 11 5 FLASH Page Erase Operation 167 11 6 FLASH Mass Erase Operation 168 11 7 FLASH Program Operation 169 11 8 FLASH Block Protection 170 11 8 1 FLASH Block Protect Register 172 1...

Page 15: ... 13 2 Introduction 181 13 3 Features 182 13 4 Functional Description 182 13 5 Keyboard Initialization 185 13 6 Low Power Modes 186 13 6 1 Wait Mode 186 13 6 2 Stop Mode 186 13 7 Keyboard Module During Break Interrupts 186 13 8 I O Registers 187 13 8 1 Keyboard Status and Control Register 187 13 8 2 Keyboard Interrupt Enable Register 188 Section 14 Low Voltage Inhibit LVI 14 1 Contents 189 14 2 Int...

Page 16: ...duction 195 15 3 Features 196 15 4 Functional Description 196 15 4 1 Entering Monitor Mode 198 15 4 2 Data Format 202 15 4 3 Break Signal 202 15 4 4 Baud Rate 203 15 4 5 Commands 203 15 5 Security 208 Section 16 Input Output I O Ports 16 1 Contents 211 16 2 Introduction 212 16 3 Port A 215 16 3 1 Port A Data Register 215 16 3 2 Data Direction Register A 216 16 3 3 Port A Input Pullup Enable Regist...

Page 17: ...andom Access Memory RAM 17 1 Contents 235 17 2 Introduction 235 17 3 Functional Description 235 Section 18 Serial Communications Interface Module SCI 18 1 Contents 237 18 2 Introduction 238 18 3 Features 238 18 4 Pin Name Conventions 240 18 5 Functional Description 240 18 5 1 Data Format 243 18 5 2 Transmitter 243 18 5 2 1 Character Length 245 18 5 2 2 Character Transmission 245 18 5 2 3 Break Cha...

Page 18: ... 258 18 9 I O Registers 259 18 9 1 SCI Control Register 1 259 18 9 2 SCI Control Register 2 262 18 9 3 SCI Control Register 3 265 18 9 4 SCI Status Register 1 268 18 9 5 SCI Status Register 2 272 18 9 6 SCI Data Register 273 18 9 7 SCI Baud Rate Register 274 Section 19 System Integration Module SIM 19 1 Contents 277 19 2 Introduction 278 19 3 SIM Bus Clock Control and Generation 281 19 3 1 Bus Tim...

Page 19: ... Interrupts 288 19 6 1 1 Hardware Interrupts 291 19 6 1 2 SWI Instruction 292 19 6 1 3 Interrupt Status Registers 292 19 6 2 Reset 294 19 6 3 Break Interrupts 294 19 6 4 Status Flag Protection in Break Mode 295 19 7 Low Power Modes 295 19 7 1 Wait Mode 295 19 7 2 Stop Mode 297 19 8 SIM Registers 298 19 8 1 SIM Break Status Register 298 19 8 2 SIM Reset Status Register 300 19 8 3 SIM Break Flag Con...

Page 20: ...20 10 Resetting the SPI 322 20 11 Low Power Modes 323 20 11 1 Wait Mode 323 20 11 2 Stop Mode 323 20 12 SPI During Break Interrupts 324 20 13 I O Signals 324 20 13 1 MISO Master In Slave Out 325 20 13 2 MOSI Master Out Slave In 325 20 13 3 SPSCK Serial Clock 326 20 13 4 SS Slave Select 326 20 13 5 CGND Clock Ground 327 20 14 I O Registers 328 20 14 1 SPI Control Register 328 20 14 2 SPI Status and...

Page 21: ... 5 2 Input Capture 347 22 5 3 Output Compare 348 22 5 3 1 Unbuffered Output Compare 348 22 5 3 2 Buffered Output Compare 349 22 5 4 Pulse Width Modulation PWM 349 22 5 4 1 Unbuffered PWM Signal Generation 350 22 5 4 2 Buffered PWM Signal Generation 351 22 5 4 3 PWM Initialization 352 22 6 Interrupts 353 22 7 Low Power Modes 353 22 7 1 Wait Mode 354 22 7 2 Stop Mode 354 22 8 TIM During Break Interr...

Page 22: ...0 V DC Electrical Characteristics 370 23 8 5 0 V Control Timing 372 23 9 3 0 V Control Timing 373 23 10 Output High Voltage Characteristics 374 23 11 Output Low Voltage Characteristics 377 23 12 Typical Supply Currents 380 23 13 ADC Characteristics 382 23 14 5 0 V SPI Characteristics 383 23 15 3 0 V SPI Characteristics 384 23 16 Timer Interface Module Characteristics 387 23 17 Clock Generation Mod...

Page 23: ... Introduction 395 25 3 MC Order Numbers 395 Appendix A MC68HC08GP32 A 1 Contents 397 A 2 Introduction 398 A 3 MCU Block Diagram 398 A 4 Memory Map 400 A 5 Mask Option Registers 401 A 6 Reserved Registers 402 A 7 Monitor ROM 402 A 8 Electrical Specifications 403 A 8 1 Functional Operating Range 403 A 8 2 5 0 V DC Electrical Characteristics 403 A 8 3 3 0 V DC Electrical Characteristics 404 A 8 4 Mem...

Page 24: ...of Contents Technical Data MC68HC908GP32 MC68HC08GP32 Rev 6 22 Table of Contents MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 25: ...Interrupt Recognition Example 77 4 6 Interrupt Processing 78 4 7 Interrupt Status Register 1 INT1 85 4 8 Interrupt Status Register 2 INT2 85 4 9 Interrupt Status Register 3 INT3 86 5 1 ADC Block Diagram 89 5 2 ADC Status and Control Register ADSCR 93 5 3 ADC Data Register ADR 95 5 4 ADC Clock Register ADCLK 95 6 1 Break Module Block Diagram 99 6 2 I O Register Summary 99 6 3 Break Status and Contr...

Page 26: ... 2 COP Control Register COPCTL 145 10 1 CPU Registers 149 10 2 Accumulator A 149 10 3 Index Register H X 150 10 4 Stack Pointer SP 151 10 5 Program Counter PC 151 10 6 Condition Code Register CCR 152 11 1 FLASH Control Register FLCR 166 11 2 FLASH Programming Flowchart 171 11 3 FLASH Block Protect Register FLBPR 172 11 4 FLASH Block Protect Start Address 172 12 1 IRQ Module Block Diagram 177 12 2 ...

Page 27: ...E 218 16 6 Port B Data Register PTB 219 16 7 Data Direction Register B DDRB 220 16 8 Port B I O Circuit 220 16 9 Port C Data Register PTC 222 16 10 Data Direction Register C DDRC 223 16 11 Port C I O Circuit 224 16 12 Port C Input Pullup Enable Register PTCPUE 225 16 13 Port D Data Register PTD 226 16 14 Data Direction Register D DDRD 228 16 15 Port D I O Circuit 229 16 16 Port D Input Pullup Enab...

Page 28: ...285 19 8 Interrupt Entry Timing 289 19 9 Interrupt Recovery Timing 289 19 10 Interrupt Processing 290 19 11 Interrupt Recognition Example 291 19 12 Interrupt Status Register 1 INT1 293 19 13 Interrupt Status Register 2 INT2 293 19 14 Interrupt Status Register 3 INT3 294 19 15 Wait Mode Entry Timing 296 19 16 Wait Recovery from Interrupt or Break 296 19 17 Wait Recovery from Internal Reset 296 19 1...

Page 29: ...PWM Period and Pulse Width 350 22 4 TIM Status and Control Register TSC 356 22 5 TIM Counter Registers High TCNTH 358 22 6 TIM Counter Registers Low TCNTL 358 22 7 TIM Counter Modulo Register High TMODH 359 22 8 TIM Counter Modulo Register Low TMODL 359 22 9 TIM Channel 0 Status and Control Register TSC0 360 22 10 TIM Channel 1 Status and Control Register TSC1 360 22 11 CHxMAX Latency 363 22 12 TI...

Page 30: ...ristics Port PTC4 PTC0 VDD 2 7 Vdc 378 23 11 Typical Low Side Driver Characteristics Ports PTB7 PTB0 PTC6 PTC5 PTD7 PTD0 and PTE1 PTE0 VDD 5 5 Vdc 379 23 12 Typical Low Side Driver Characteristics Ports PTB7 PTB0 PTC6 PTC5 PTD7 PTD0 and PTE1 PTE0 VDD 2 7 Vdc 379 23 13 Typical Operating IDD with All Modules Turned On 40 C to 85 C 380 23 14 Typical Wait Mode IDD with all Modules Disabled 40 C to 85 ...

Page 31: ...ode Map 164 14 1 LVIOUT Bit Indication 193 15 1 Monitor Mode Signal Requirements and Options 199 15 2 Mode Differences 202 15 3 Monitor Baud Rate Selection 203 15 4 READ Read Memory Command 205 15 5 WRITE Write Memory Command 205 15 6 IREAD Indexed Read Command 206 15 7 IWRITE Indexed Write Command 206 15 8 READSP Read Stack Pointer Command 207 15 9 RUN Run User Program Command 207 16 1 Port Contr...

Page 32: ...lection Examples 276 19 1 Signal Name Conventions 279 19 2 PIN Bit Set Timing 283 19 3 Interrupt Sources 292 19 4 SIM Registers 298 20 1 Pin Name Conventions 305 20 2 SPI Interrupts 320 20 3 SPI Configuration 327 20 4 SPI Master Baud Rate Selection 333 21 1 Timebase Rate Selection for OSC1 32 768 kHz 337 22 1 Pin Name Conventions 343 22 2 Prescaler Selection 357 22 3 Mode Edge and Level Selection ...

Page 33: ...llator Pins OSC1 and OSC2 40 1 6 3 External Reset Pin RST 40 1 6 4 External Interrupt Pin IRQ 40 1 6 5 CGM Power Supply Pins VDDA and VSSA 41 1 6 6 External Filter Capacitor Pin CGMXFC 41 1 6 7 ADC Power Supply Reference Pins VDDAD VREFH and VSSAD VREFL 41 1 6 8 Port A Input Output I O Pins PTA7 KBD7 PTA0 KBD0 41 1 6 9 Port B I O Pins PTB7 AD7 PTB0 AD0 41 1 6 10 Port C I O Pins PTC6 PTC0 42 1 6 11...

Page 34: ...re optimized for C compilers Fully upward compatible object code with M6805 M146805 and M68HC05 Families 8 MHz internal bus frequency FLASH program memory security1 On chip programming firmware for use with host personal computer which does not require high voltage for entry In system programming System protection features Optional computer operating properly COP reset Low voltage detection with o...

Page 35: ... breakpoint setting during in circuit debugging Internal pullups on IRQ and RST to reduce customer system cost Clock generator module with on chip 32 kHz crystal compatible PLL phase lock loop Up to 33 general purpose input output I O pins including 26 shared function I O pins Five or seven dedicated I O pins depending on package choice Selectable pullups on inputs only on ports A C and D Selectio...

Page 36: ...odule Specific features of the MC68HC908GP32 in 42 pin SDIP are Port C is only 5 bits PTC0 PTC4 Port D is 8 bits PTD0 PTD7 dual 2 channel TIM modules Specific features of the MC68HC908GP32 in 44 pin QFP are Port C is 7 bits PTC0 PTC6 Port D is 8 bits PTD0 PTD7 dual 2 channel TIM modules 1 3 2 Features of the CPU08 Features of the CPU08 include Enhanced HC05 programming model Extensive loop control...

Page 37: ...ock Diagram Figure 1 1 shows the structure of the MC68HC908GP32 Text in parentheses within a module block indicates the module name Text in parentheses next to a signal indicates the module which uses the signal Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 38: ...COMPUTER OPERATING PROPERLY MODULE PTA7 KBD7 PTA0 KBD0 PTB7 AD7 PTB6 AD6 PTB5 AD5 PTB4 AD4 PTB3 AD3 PTB2 AD2 PTB1 AD1 PTB0 AD0 V DDAD V REFH 8 BIT ANALOG TO DIGITAL CONVERTER MODULE PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 PTD7 T2CH1 PTD6 T2CH0 PTD5 T1CH1 PTD4 T1CH0 PTD3 SPSCK PTD2 MOSI PTD1 MISO PTD0 SS PTE1 RxD PTE0 TxD V SSAD V REFL 2 CHANNEL TIMER INTERFACE MODULE 1 32 kHz OSCILLATOR PHASE LOCKED LO...

Page 39: ... MOSI RST IRQ PTD0 SS PTD1 MISO PTA0 KBD0 PTA1 KBD1 PTA2 KBD2 PTA3 KBD3 PTA4 KBD4 PTA5 KBD5 PTA6 KBD6 PTA7 KBD7 PTB6 AD6 PTB7 AD7 PTB3 AD3 PTB4 AD4 PTB5 AD5 VSSA PLL VDDA PLL VDDAD VREFH ADC VSSAD VREFL ADC CGMXFC PLL OSC2 OSC1 PTC0 PTC1 PTC2 PTC3 PTC4 PTE0 TxD PTE1 RxD PTB2 AD2 Pins not available on 40 pin package Internal connection PTC5 Connected to ground PTC6 Connected to ground PTD6 T2CH0 Un...

Page 40: ...OSI RST IRQ PTD0 SS PTD1 MISO PTA0 KBD0 PTA1 KBD1 PTA2 KBD2 PTA3 KBD3 PTA4 KBD4 PTA5 KBD5 PTA6 KBD6 PTA7 KBD7 PTB6 AD6 PTB7 AD7 PTB3 AD3 PTB4 AD4 PTB5 AD5 VSSA PLL VDDA PLL VDDAD VREFH ADC VSSAD VREFL ADC CGMXFC PLL OSC2 OSC1 PTC0 PTC1 PTC2 PTC3 PTC4 PTE0 TxD PTE1 RxD PTB2 AD2 20 23 PTD6 T2CH0 VDD Pins not available on 42 pin package Internal connection PTC5 Connected to ground PTC6 Connected to g...

Page 41: ... supply bypassing at the MCU as Figure 1 5 shows Place the C1 bypass capacitor as close to the MCU as possible 44 34 43 42 41 40 39 38 37 36 35 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 12 23 RST PTE0 TxD PTE1 RxD IRQ PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 PTD5 T1CH1 PTD4 T1CH0 V DD V SS PTD3 SPSCK PTD2 MOSI PTD1 MISO PTD0 SS PTD6 T2CH0 PTD7 T2CH1 PTB0 AD0 PTB...

Page 42: ...C 1 6 3 External Reset Pin RST A logic 0 on the RST pin forces the MCU to a known startup state RST is bidirectional allowing a reset of the entire system It is driven low when any internal reset source is asserted This pin contains an internal pullup resistor See Section 19 System Integration Module SIM 1 6 4 External Interrupt Pin IRQ IRQ is an asynchronous external interrupt pin This pin contai...

Page 43: ...se pins should be as per the digital supply See Section 5 Analog to Digital Converter ADC VREFH is the high reference supply for the ADC and is internally connected to VDDAD VREFL is the low reference supply for the ADC and is internally connected to VSSAD 1 6 8 Port A Input Output I O Pins PTA7 KBD7 PTA0 KBD0 PTA7 PTA0 are general purpose bidirectional I O port pins Any or all of the port A pins ...

Page 44: ...M Section 20 Serial Peripheral Interface Module SPI and Section 16 Input Output I O Ports PTD6 and PTD7 are only available on 42 SDIP and 44 pin QFP packages These port pins also have selectable pullups when configured for input mode The pullups are disengaged when configured for output mode The pullups are selectable on an individual port bit basis 1 6 12 Port E I O Pins PTE1 RxD PTE0 TxD PTE0 PT...

Page 45: ... of memory space The memory map shown in Figure 2 1 includes 32 256 bytes of user FLASH memory 512 bytes of random access memory RAM 36 bytes of user defined vectors 307 bytes of monitor ROM 2 3 Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset In the memory map Figure 2 1 and in register figures in this document unimplemented locations are shade...

Page 46: ...tatus register SBSR FE01 SIM reset status register SRSR FE02 reserved SUBAR FE03 SIM break flag control register SBFCR FE04 interrupt status register 1 INT1 FE05 interrupt status register 2 INT2 FE06 interrupt status register 3 INT3 FE07 reserved FE08 FLASH control register FLCR FE09 break address register high BRKH FE0A break address register low BRKL FE0B break status and control register BRKSCR...

Page 47: ...R FE03 SIM Break Flag Control Register SBFCR FE04 Interrupt Status Register 1 INT1 FE05 Interrupt Status Register 2 INT2 FE06 Interrupt Status Register 3 INT3 FE07 Reserved FE08 FLASH Control Register FLCR FE09 Break Address Register High BRKH FE0A Break Address Register Low BRKL FE0B Break Status and Control Register BRKSCR FE0C LVI Status Register LVISR FE0D Unimplemented 3 Bytes FE0F Figure 2 1...

Page 48: ...ts FE1F FE20 Monitor ROM 307 Bytes FF52 FF53 Unimplemented 43 Bytes FF7D FF7E FLASH Block Protect Register FLBPR FF7F Unimplemented 93 Bytes FFDB Note FFF6 FFFD reserved for 8 security bytes FFDC FLASH Vectors 36 Bytes FFFF Figure 2 1 Memory Map Continued Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 49: ...egister A DDRA Read DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Write Reset 0 0 0 0 0 0 0 0 0005 Data Direction Register B DDRB Read DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 Write Reset 0 0 0 0 0 0 0 0 0006 Data Direction Register C DDRC Read 0 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 Write Reset 0 0 0 0 0 0 0 0 0007 Data Direction Register D DDRD Read DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDR...

Page 50: ... PTDPUE Read PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0 Write Reset 0 0 0 0 0 0 0 0 0010 SPI Control Register SPCR Read SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIE Write Reset 0 0 1 0 1 0 0 0 0011 SPI Status and Control Register SPSCR Read SPRF ERRIE OVRF MODF SPTE MODFEN SPR1 SPR0 Write Reset 0 0 0 0 1 0 0 0 0012 SPI Data Register SPDR Read R7 R6 R5 R4 R3 R2 R1 R0 Write T7 T6...

Page 51: ...d Rate Register SCBR Read SCP1 SCP0 R SCR2 SCR1 SCR0 Write Reset 0 0 0 0 0 0 0 0 001A Keyboard Status and Control Register INTKBSCR Read 0 0 0 0 KEYF 0 IMASKK MODEK Write ACKK Reset 0 0 0 0 0 0 0 0 001B Keyboard Interrupt Enable Register INTKBIER Read KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 Write Reset 0 0 0 0 0 0 0 0 001C Time Base Module Control Register TBCR Read TBIF TBR2 TBR1 TBR0 0 T...

Page 52: ...15 14 13 12 11 10 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 0024 Timer 1 Counter Modulo Register Low T1MODL Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 0025 Timer 1 Channel 0 Status and Control Register T1SC0 Read CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Write 0 Reset 0 0 0 0 0 0 0 0 0026 Timer 1 Channel 0 Register High T1CH0H Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate...

Page 53: ...it 8 Write Reset 0 0 0 0 0 0 0 0 002D Timer 2 Counter Register Low T2CNTL Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 002E Timer 2 Counter Modulo Register High T2MODH Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 002F Timer 2 Counter Modulo Register Low T2MODL Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 0030 Timer 2 Channel 0 Status and Control Register T...

Page 54: ...Write Reset 0 0 1 0 0 0 0 0 0037 PLL Bandwidth Control Register PBWC Read AUTO LOCK ACQ 0 0 0 0 R Write Reset 0 0 0 0 0 0 0 0 0038 PLL Multiplier Select High Register PMSH Read 0 0 0 0 MUL11 MUL10 MUL9 MUL8 Write Reset 0 0 0 0 0 0 0 0 0039 PLL Multiplier Select Low Register PMSL Read MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0 Write Reset 0 1 0 0 0 0 0 0 003A PLL VCO Range Select Register PMRS Read VR...

Page 55: ...iting a logic 0 clears SBSW FE01 SIM Reset Status Register SRSR Read POR PIN COP ILOP ILAD MODRST LVI 0 Write POR 1 0 0 0 0 0 0 0 FE02 SIM Upper Byte Address Register SUBAR Read R R R R R R R R Write Reset FE03 SIM Break Flag Control Register SBFCR Read BCFE R R R R R R R Write Reset 0 FE04 Interrupt Status Register 1 INT1 Read IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write R R R R R R R R Reset 0 0 0 0 0 0 0 ...

Page 56: ... 0 0 0 0 0 0 0 FE0B Break Status and Control Register BRKSCR Read BRKE BRKA 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 FE0C LVI Status Register LVISR Read LVIOUT 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 FF7E FLASH Block Protect Register FLBPR Read BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Write Reset U U U U U U U U FFFF COP Control Register COPCTL Read Low byte of reset vector Write Writing clears CO...

Page 57: ...igh FFE9 SPI Transmit Vector Low IF9 FFEA SPI Receive Vector High FFEB SPI Receive Vector Low IF8 FFEC TIM2 Overflow Vector High FFED TIM2 Overflow Vector Low IF7 FFEE TIM2 Channel 1 Vector High FFEF TIM2 Channel 1 Vector Low IF6 FFF0 TIM2 Channel 0 Vector High FFF1 TIM2 Channel 0 Vector Low IF5 FFF2 TIM1 Overflow Vector High FFF3 TIM1 Overflow Vector Low IF4 FFF4 TIM1 Channel 1 Vector High FFF5 T...

Page 58: ...Memory Map Technical Data MC68HC908GP32 MC68HC08GP32 Rev 6 56 Memory Map MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 59: ... 3 5 Central Processor Unit CPU 60 3 5 1 Wait Mode 60 3 5 2 Stop Mode 60 3 6 Clock Generator Module CGM 60 3 6 1 Wait Mode 60 3 6 2 Stop Mode 61 3 7 Computer Operating Properly Module COP 61 3 7 1 Wait Mode 61 3 7 2 Stop Mode 61 3 8 External Interrupt Module IRQ 62 3 8 1 Wait Mode 62 3 8 2 Stop Mode 62 3 9 Keyboard Interrupt Module KBI 62 3 9 1 Wait Mode 62 3 9 2 Stop Mode 62 3 10 Low Voltage Inhi...

Page 60: ...g Stop Mode 67 3 2 Introduction The MCU may enter two low power modes wait mode and stop mode They are common to all HC08 MCUs and are entered through instruction execution This section describes how each module acts in the low power modes 3 2 1 Wait Mode The WAIT instruction puts the MCU in a low power standby mode in which the CPU clock is disabled but the bus clock continues to run Power consum...

Page 61: ...quired to bring the MCU out of wait mode power down the ADC by setting ADCH4 ADCH0 bits in the ADC status and control register before executing the WAIT instruction 3 3 2 Stop Mode The ADC module is inactive after the execution of a STOP instruction Any pending conversion is aborted ADC conversions resume when the MCU exits stop mode after an external interrupt Allow one conversion cycle to stabil...

Page 62: ... I bit is set Disables the CPU clock 3 5 2 Stop Mode The STOP instruction Clears the interrupt mask I bit in the condition code register enabling external interrupts After exit from stop mode by external interrupt the I bit remains clear After exit by reset the I bit is set Disables the CPU clock After exiting stop mode the CPU clock begins running after the oscillator stabilization delay 3 6 Cloc...

Page 63: ... PCTL thereby selecting the crystal clock CGMXCLK divided by two as the source of CGMOUT When the MCU recovers from STOP the crystal clock divided by two drives CGMOUT and BCS remains clear If the OSCSTOPEN bit in the CONFIG register is set then the phase locked loop is shut off but the oscillator will continue to operate in stop mode 3 7 Computer Operating Properly Module COP 3 7 1 Wait Mode The ...

Page 64: ...de The IRQ module remains active in stop mode Clearing the IMASK bit in the IRQ status and control register enables IRQ CPU interrupt requests to bring the MCU out of stop mode 3 9 Keyboard Interrupt Module KBI 3 9 1 Wait Mode The keyboard module remains active in wait mode Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out ...

Page 65: ...ace Module SCI 3 11 1 Wait Mode The SCI module remains active in wait mode Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode If SCI module functions are not required during wait mode reduce power consumption by disabling the module before executing the WAIT instruction 3 11 2 Stop Mode The SCI module is inactive in stop mode The STOP instruction does not affe...

Page 66: ...sumes after an external interrupt If stop mode is exited by reset any transfer in progress is aborted and the SPI is reset 3 13 Timer Interface Module TIM1 and TIM2 3 13 1 Wait Mode The TIM remains active in wait mode Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode If TIM functions are not required during wait mode reduce power consumption by stopping the TIM befo...

Page 67: ...n the CONFIG register The timebase module can be used in this mode to generate a periodic wakeup from stop mode If the oscillator has not been enabled to operate in stop mode the timebase module will not be active during stop mode In stop mode the timebase register is not accessible by the CPU If the timebase functions are not required during stop mode reduce the power consumption by stopping the ...

Page 68: ...U interrupt request from the phase locked loop PLL loads the program counter with the contents of FFF8 and FFF9 Keyboard module KBI interrupt A CPU interrupt request from the KBI module loads the program counter with the contents of FFE0 and FFE1 Timer 1 interface module TIM1 interrupt A CPU interrupt request from the TIM1 loads the program counter with the contents of FFF2 and FFF3 TIM1 overflow ...

Page 69: ...FFDC and FFDD TBM interrupt 3 16 Exiting Stop Mode These events restart the system clocks and load the program counter with the reset vector or with an interrupt vector External reset A logic 0 on the RST pin resets the MCU and loads the program counter with the contents of locations FFFE and FFFF External interrupt A high to low transition on an external interrupt pin loads the program counter wi...

Page 70: ...r an oscillator stabilization delay A 12 bit stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external interrupt The short stop recovery bit SSREC in the configuration register controls the oscillator stabilization delay during stop recovery Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles NOTE Use the full stop recov...

Page 71: ...t 74 4 3 4 SIM Reset Status Register 74 4 4 Interrupts 75 4 4 1 Effects 75 4 4 2 Sources 79 4 4 2 1 SWI Instruction 80 4 4 2 2 Break Interrupt 80 4 4 2 3 IRQ Pin 80 4 4 2 4 CGM 80 4 4 2 5 TIM1 80 4 4 2 6 TIM2 81 4 4 2 7 SPI 81 4 4 2 8 SCI 82 4 4 2 9 KBD0 KBD7 Pins 83 4 4 2 10 ADC Analog to Digital Converter 83 4 4 2 11 TBM Timebase Module 83 4 4 3 Interrupt Status Registers 84 4 4 3 1 Interrupt St...

Page 72: ...ogram execution from a user defined memory location 4 3 1 Effects A reset Immediately stops the operation of the instruction being executed Initializes certain control and status bits Loads the program counter with a user defined reset vector address from locations FFFE and FFFF Selects CGMXCLK divided by four as the bus clock 4 3 2 External Reset A logic 0 applied to the RST pin for a time tIRL g...

Page 73: ...Illegal address All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external devices The MCU is held in reset for an additional 32 CGMXCLK cycles after releasing the RST pin Figure 4 1 Internal Reset Timing RST PIN PULLED LOW BY MCU INTERNAL 32 CYCLES 32 CYCLES CGMXCLK RESET Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This P...

Page 74: ...ization delay of 4096 CGMXCLK cycles Drives the RST pin low during the oscillator stabilization delay Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator stabilization delay Sets the POR and LP bits in the SIM reset status register and clears all other bits in the register Figure ...

Page 75: ...LK cycles after the power supply voltage rises to the LVItripr voltage Drives the RST pin low for as long as VDD is below the LVItripr voltage and during the oscillator stabilization delay Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator stabilization delay Sets the LVI bit in ...

Page 76: ... initialized on power up as shown with the POR bit set and all other bits cleared During a POR or any other internal reset the RST pin is pulled low After the pin is released it will be sampled 32 CGMXCLK cycles later If the pin is not above a VIH at that time then the PIN bit in the SRSR may be set in addition to whatever other bits are set NOTE Only a read of the SIM reset status register clears...

Page 77: ...it 1 Last reset caused by monitor mode entry when vector locations FFFE and FFFF are FF after POR while IRQ VDD 0 POR or read of SRSR LVI Low Voltage Inhibit Reset Bit 1 Last reset caused by low power supply voltage 0 POR or read of SRSR 4 4 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event An interrupt does not stop the operation of the...

Page 78: ...f more than one interrupt is pending when an instruction is done the highest priority interrupt is serviced first In the example shown in Figure 4 5 if an interrupt is pending upon exit from the interrupt service routine the pending interrupt is serviced before the LDA instruction is executed CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER LOW BYTE PROGRAM COUNTER HIGH BYTE PROGRAM COUNTER LOW ...

Page 79: ...ntain compatibility with the M6805 Family the H register is not pushed on the stack during interrupt entry If the interrupt service routine modifies the H register or uses the indexed addressing mode save the H register and then restore it prior to exiting the routine CLI LDA INT1 PULH RTI INT2 BACKGROUND FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE ROUTINE F...

Page 80: ...RESET BREAK I BIT SET IRQ INTERRUPT CGM INTERRUPT FETCH NEXT INSTRUCTION UNSTACK CPU REGISTERS STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR EXECUTE INSTRUCTION YES YES I BIT SET INTERRUPT YES OTHER INTERRUPTS NO SWI INSTRUCTION RTI INSTRUCTION Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 81: ...FF5 TIM1 overflow TOF TOIE IF5 5 FFF2 FFF3 TIM2 channel 0 CH0F CH0IE IF6 6 FFF0 FFF1 TIM2 channel 1 CH1F CH1IE IF7 7 FFEE FFEF TIM2 overflow TOF TOIE IF8 8 FFEC FFED SPI receiver full SPRF SPRIE IF9 9 FFEA FFEB SPI overflow OVRF ERRIE SPI mode fault MODF ERRIE SPI transmitter empty SPTE SPTIE IF10 10 FFE8 FFE9 SCI receiver overrun OR ORIE IF11 11 FFE6 FFE7 SCI noise fag NF NEIE SCI framing error F...

Page 82: ...e PLL flag PLLF is set The PLL interrupt enable bit PLLIE enables PLLF CPU interrupt requests LOCK is in the PLL bandwidth control register PLLF is in the PLL control register 4 4 2 5 TIM1 TIM1 CPU interrupt sources TIM1 overflow flag TOF The TOF bit is set when the TIM1 counter reaches the modulo value programmed in the TIM1 counter modulo registers The TIM1 overflow interrupt enable bit TOIE ena...

Page 83: ...rs from the shift register to the receive data register The SPI receiver interrupt enable bit SPRIE enables SPRF CPU interrupt requests SPRF is in the SPI status and control register and SPRIE is in the SPI control register SPI transmitter empty SPTE The SPTE bit is set every time a byte transfers from the transmit data register to the shift register The SPI transmit interrupt enable bit SPTIE ena...

Page 84: ...ion complete interrupt enable bit TCIE enables transmitter CPU interrupt requests TC is in SCI status register 1 TCIE is in SCI control register 2 SCI receiver full bit SCRF SCRF is set when the receive shift register transfers a character to the SCI data register The SCI receive interrupt enable bit SCRIE enables receiver CPU interrupts SCRF is in SCI status register 1 SCRIE is in SCI control reg...

Page 85: ...upt enable bit PEIE enables PE to generate SCI error CPU interrupt requests PE is in SCI status register 1 PEIE is in SCI control register 3 4 4 2 9 KBD0 KBD7 Pins A logic 0 on a keyboard interrupt pin latches an external interrupt request 4 4 2 10 ADC Analog to Digital Converter When the AIEN bit is set the ADC module is capable of generating a CPU interrupt after each ADC conversion The COCO bit...

Page 86: ... registers can be useful for debugging Table 4 2 Interrupt Source Flags Interrupt Source Interrupt Status Register Flag Reset SWI instruction IRQ pin IF1 CGM PLL IF2 TIM1 channel 0 IF3 TIM1 channel 1 IF4 TIM1 overflow IF5 TIM2 channel 0 IF6 TIM2 channel 1 IF7 TIM2 overflow IF8 SPI receive IF9 SPI transmit IF10 SCI error IF11 SCI receive IF12 SCI transmit IF13 Keyboard IF14 ADC conversion complete ...

Page 87: ... 14 7 These flags indicate the presence of interrupt requests from the sources shown in Table 4 2 1 Interrupt request present 0 No interrupt request present Address FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 4 7 Interrupt Status Register 1 INT1 Address FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read IF14 IF13 IF12 IF11 IF10 IF9 IF8...

Page 88: ...nterrupt request from the source shown in Table 4 2 1 Interrupt request present 0 No interrupt request present Bits 7 2 Always read 0 Address FE06 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 IF16 IF15 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 4 9 Interrupt Status Register 3 INT3 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www fr...

Page 89: ...sion 90 5 4 5 Accuracy and Precision 91 5 5 Interrupts 91 5 6 Low Power Modes 91 5 6 1 Wait Mode 91 5 6 2 Stop Mode 91 5 7 I O Signals 91 5 7 1 ADC Analog Power Pin VDDAD ADC Voltage Reference High Pin VREFH 92 5 7 2 ADC Analog Ground Pin VSSAD ADC Voltage Reference Low Pin VREFL 92 5 7 3 ADC Voltage In VADIN 92 5 8 I O Registers 92 5 8 1 ADC Status and Control Register 93 5 8 2 ADC Data Register ...

Page 90: ...nversion complete interrupt Selectable ADC clock 5 4 Functional Description The ADC provides eight pins for sampling external sources at pins PTB7 AD7 PTB0 AD0 An analog multiplexer allows the single ADC converter to select one of eight ADC channels as ADC voltage in VADIN VADIN is converted by the successive approximation register based analog to digital converter When the conversion is completed...

Page 91: ...g ADC channels port pins are controlled by the port I O logic and can be used as general purpose I O Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC Read of a port pin in use by the ADC will return a logic 0 INTERNAL DATA BUS READ DDRBx WRITE DDRBx RESET WRITE PTBx READ PTBx PTBx DDRBx PTBx INTERRUPT LOGIC CHANNEL SELECT ADC CLOCK GENERATOR C...

Page 92: ... noise immunity 5 4 3 Conversion Time Conversion starts after a write to the ADSCR One conversion will take between 16 and 17 ADC clock cycles The ADIVx and ADICLK bits should be set to provide a 1 MHz ADC clock frequency 5 4 4 Conversion In continuous conversion mode the ADC data register will be filled with new data after each conversion Data from the previous conversion will be overwritten whet...

Page 93: ...5 6 1 Wait Mode The ADC continues normal operation during wait mode Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode If the ADC is not required to bring the MCU out of wait mode power down the ADC by setting ADCH4 ADCH0 bits in the ADC status and control register before executing the WAIT instruction 5 6 2 Stop Mode The ADC module is inactive after the execution of...

Page 94: ...rs as close as possible to the package 5 7 2 ADC Analog Ground Pin VSSAD ADC Voltage Reference Low Pin VREFL The ADC analog portion uses VSSAD as its ground pin Connect the VSSAD pin to the same voltage potential as VSS NOTE Route VSSAD cleanly to avoid any offset errors 5 7 3 ADC Voltage In VADIN VADIN is the input voltage signal from one of the eight ADC channels to the ADC module 5 8 I O Regist...

Page 95: ...EN 0 0 Conversion not completed AIEN 0 CPU interrupt AIEN 1 AIEN ADC Interrupt Enable Bit When this bit is set an interrupt is generated at the end of an ADC conversion The interrupt signal is cleared when the data register is read or the status control register is written Reset clears the AIEN bit 1 ADC interrupt enabled 0 ADC interrupt disabled ADCO ADC Continuous Conversion Bit When set the ADC...

Page 96: ... the MCU when the ADC is not being used NOTE Recovery from the disabled state requires one conversion cycle to stabilize The voltage levels supplied from internal reference nodes as specified in Table 5 1 are used to verify the operation of the ADC converter both in production test and for user applications Table 5 1 Mux Channel Select ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select 0 0 0 0 0 PTB0 AD0 ...

Page 97: ...IV0 form a 3 bit field which selects the divide ratio used by the ADC to generate the internal ADC clock Table 5 2 shows the available clock configurations The ADC clock should be set to approximately 1 MHz Address 003D Bit 7 6 5 4 3 2 1 Bit 0 Read AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 5 3 ADC Data Register ADR Address 003E Bit 7 6 5 4 3 2 1 Bit 0 Read AD...

Page 98: ...ock source for the ADC If CGMXCLK is less than 1 MHz use the PLL generated bus clock as the clock source As long as the internal ADC clock is at approximately 1 MHz correct operation can be guaranteed 1 Internal bus clock 0 External clock CGMXCLK Table 5 2 ADC Clock Divide Ratio ADIV2 ADIV1 ADIV0 ADC Clock Rate 0 0 0 ADC input clock 1 0 0 1 ADC input clock 2 0 1 0 ADC input clock 4 0 1 1 ADC input...

Page 99: ...uring Break Interrupts 100 6 5 Low Power Modes 100 6 5 1 Wait Mode 100 6 5 2 Stop Mode 101 6 6 Break Module Registers 101 6 6 1 Break Status and Control Register 101 6 6 2 Break Address Registers 102 6 6 3 Break Status Register 103 6 6 4 Break Flag Control Register 104 6 2 Introduction This section describes the break module The break module can generate a break interrupt that stops normal program...

Page 100: ...rent CPU instruction The program counter vectors to FFFC and FFFD FEFC and FEFD in monitor mode The following events can cause a break interrupt to occur A CPU generated address the address in the program counter matches the contents of the break address registers Software writes a logic 1 to the BRKA bit in the break status and control register When a CPU generated address matches the contents of...

Page 101: ... Note Reset 0 FE03 SIM Break Flag Control Register SBFCR Read BCFE R R R R R R R Write Reset 0 FE09 Break Address Register High BRKH Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 FE0A Break Address Register Low BRKL Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 FE0B Break Status and Control Register BRKSCR Read BRKE BRKA 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Note Writ...

Page 102: ...ss register match occurs on the last cycle of a CPU instruction the break interrupt begins immediately 6 4 3 TIM1 and TIM2 During Break Interrupts A break interrupt stops the timer counters 6 4 4 COP During Break Interrupts The COP is disabled during a break interrupt when VTST is present on the RST pin 6 5 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby...

Page 103: ...lag control register SBFCR 6 6 1 Break Status and Control Register The break status and control register BRKSCR contains break module enable and status bits BRKE Break Enable Bit This read write bit enables breaks on break address register matches Clear BRKE by writing a logic 0 to bit 7 Reset clears the BRKE bit 1 Breaks enabled on 16 bit address match 0 Breaks disabled on 16 bit address match Ad...

Page 104: ...break address match 6 6 2 Break Address Registers The break address registers BRKH and BRKL contain the high and low bytes of the desired breakpoint address Reset clears the break address registers Address FE09 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 Figure 6 4 Break Address Register High BRKH Address FE0A Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 ...

Page 105: ...interrupt routine The user can modify the return address on the stack by subtracting 1 from it The following code is an example This code works if the H register was stacked in the break interrupt routine Execute this code at the end of the break interrupt routine Address FE00 Bit 7 6 5 4 3 2 1 Bit 0 Read R R R R R R SBSW R Write Note Reset 0 Note Writing a logic 0 clears SBSW R Reserved Figure 6 ...

Page 106: ...ite bit enables software to clear status bits by accessing status registers while the MCU is in a break state To clear status bits during the break state the BCFE bit must be set 1 Status bits clearable during break 0 Status bits not clearable during break Address FE03 Bit 7 6 5 4 3 2 1 Bit 0 Read BCFE R R R R R R R Write Reset 0 R Reserved Figure 6 7 SIM Break Flag Control Register SBFCR Freescal...

Page 107: ...l Connections 118 7 5 I O Signals 119 7 5 1 Crystal Amplifier Input Pin OSC1 119 7 5 2 Crystal Amplifier Output Pin OSC2 119 7 5 3 External Filter Capacitor Pin CGMXFC 120 7 5 4 PLL Analog Power Pin VDDA 120 7 5 5 PLL Analog Ground Pin VSSA 120 7 5 6 Oscillator Enable Signal SIMOSCEN 120 7 5 7 Oscillator Stop Mode Enable Bit OSCSTOPENB 120 7 5 8 Crystal Output Frequency Signal CGMXCLK 121 7 5 9 CG...

Page 108: ...or module The CGMC generates the crystal clock signal CGMXCLK which operates at the frequency of the crystal The CGMC also generates the base clock signal CGMOUT which is based on either the crystal clock divided by two or the phase locked loop PLL clock CGMVCLK divided by two In user mode CGMOUT is the clock from which the SIM derives the system clocks including the bus clock which is at a freque...

Page 109: ...ck detector CPU interrupt on entry or exit from locked condition Configuration register bit to allow oscillator operation during stop mode 7 4 Functional Description The CGMC consists of three major submodules Crystal oscillator circuit The crystal oscillator circuit generates the constant crystal frequency clock CGMXCLK Phase locked loop PLL The PLL generates the programmable VCO frequency clock ...

Page 110: ...L ANALOG 2 CGMRCLK OSC2 OSC1 SELECT CIRCUIT VDDA CGMXFC VSSA LOCK AUTO ACQ VPR1 VPR0 PLLIE PLLF MUL11 MUL0 REFERENCE DIVIDER VRS7 VRS0 PRE1 PRE0 OSCSTOPENB FROM CONFIG TO SIM TIMTB15A ADC PHASE LOCKED LOOP PLL A B S WHEN S 1 CGMOUT B SIMDIV2 FROM SIM TO SIM TO SIM RDS3 RDS0 R L 2E N 2P INTERRUPT CONTROL LOCK DETECTOR AUTOMATIC MODE CONTROL FREQUENCY DIVIDER FREQUENCY DIVIDER Freescale Semiconducto...

Page 111: ...e precise timing for operation The duty cycle of CGMXCLK is not guaranteed to be 50 and depends on external factors including the crystal and related external components An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit Connect the external clock to the OSC1 pin and let the OSC2 pin float 7 4 2 Phase Locked Loop Circuit PLL The PLL is a frequency generator ...

Page 112: ...back through a programmable prescale divider and a programmable modulo divider The prescaler divides the VCO clock by a power of two factor P and the modulo divider reduces the VCO clock by a factor N The dividers output is the VCO feedback clock CGMVDV running at a frequency fVDV fVCLK N 2P See 7 4 6 Programming the PLL for more information The phase detector then compares the VCO feedback clock ...

Page 113: ...it is set 7 4 5 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically Automatic mode is recommended for most users In automatic bandwidth control mode AUTO 1 the lock detector automatically switches between acquisition and tracking modes Automatic bandwidth control mode also is used to determine when the VCO clock...

Page 114: ...formation The LOCK bit is a read only indicator of the locked state of the PLL The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance See 7 9 Acquisition Lock Time Specifications for more information CPU interrupts can occur if enabled PLLIE 1 when the PLL s lock condition changes toggling the LOCK bit See 7 6 1 ...

Page 115: ... 7 4 6 Programming the PLL The following procedure shows how to program the PLL NOTE The round function in the following equations means that the real number should be rounded to the nearest integer number 1 Choose the desired bus frequency fBUSDES 2 Calculate the desired VCO frequency four times the desired bus frequency 3 Choose a practical PLL crystal reference frequency fRCLK and the reference...

Page 116: ...e determined using equation in 2 above When the tolerance on the bus frequency is tight choose fRCLK to an integer divisor of fBUSDES and R 1 If fRCLK cannot meet this requirement use the following equation to solve for R with practical choices of fRCLK and choose the fRCLK that gives the lowest R 4 Select a VCO frequency multiplier N Reduce N R to the lowest possible R 5 If N is Nmax use P 0 If N...

Page 117: ...um and maximum frequencies attainable by the PLL For proper operation 10 Verify the choice of P R N E and L by comparing fVCLK to fVRS and fVCLKDES For proper operation fVCLK must be within the application s tolerance of fVCLKDES and fVRS must be as close as possible to fVCLK NOTE Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU Frequency Range E 0 fVCLK 9 830 400...

Page 118: ...am the binary coded equivalent of L e In the PLL reference divider select register PMDS program the binary coded equivalent of R NOTE The values for P E N L and R can only be programmed when the PLL is off PLLON 0 Table 7 1 provides numeric examples numbers are in hexadecimal notation Table 7 1 Numeric Example fBUS fRCLK R N P E L 2 0 MHz 32 768 kHz 1 F5 0 0 D1 2 4576 MHz 32 768 kHz 1 12C 0 1 80 2...

Page 119: ...MVCLK cycles to change from one clock source to the other During this time CGMOUT is held in stasis The output of the transition control circuit is then divided by two to correct the duty cycle Therefore the bus clock frequency which is one half of the base clock frequency is one fourth the frequency of the selected clock CGMXCLK or CGMVCLK The BCS bit in the PLL control register PCTL selects whic...

Page 120: ...The oscillator configuration uses five components Crystal X1 Fixed capacitor C1 Tuning capacitor C2 can also be a fixed capacitor Feedback resistor RB Series resistor RS The series resistor RS is included in the diagram to follow strict Pierce oscillator guidelines Refer to the crystal manufacturer s data for more information regarding values for C1 and C2 Figure 7 2 also shows the external compon...

Page 121: ...s an input to the crystal oscillator amplifier 7 5 2 Crystal Amplifier Output Pin OSC2 The OSC2 pin is the output of the crystal oscillator inverting amplifier C1 C2 SIMOSCEN CGMXCLK RB X1 RS CBYP Note Filter network in box can be replaced with a 0 47µF capacitor but will degrade stability OSCSTOPENB FROM CONFIG 10 kΩ 0 01 µF 0 033 µF VSSA 0 1 µF OSC1 OSC2 CGMXFC VDDA VDD Freescale Semiconductor I...

Page 122: ... as close as possible to the package 7 5 5 PLL Analog Ground Pin VSSA VSSA is a ground pin used by the analog portions of the PLL Connect the VSSA pin to the same voltage potential as the VSS pin NOTE Route VSSA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package 7 5 6 Oscillator Enable Signal SIMOSCEN The SIMOSCEN signal comes from the system integ...

Page 123: ... the CGMC This signal goes to the SIM which generates the MCU clocks CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency CGMOUT is software programmable to be either the oscillator output CGMXCLK divided by two or the VCO clock CGMVCLK divided by two 7 5 10 CGMC CPU Interrupt CGMINT CGMINT is the interrupt signal generated by the PLL lock detector 7 6 CGMC Registers These re...

Page 124: ...8 Write Reset 0 0 0 0 0 0 0 0 0039 PLL Multiplier Select Low Register PMSL Read MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0 Write Reset 0 1 0 0 0 0 0 0 003A PLL VCO Range Select Register PMRS Read VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0 Write Reset 0 1 0 0 0 0 0 0 003B PLL Reference Divider Select Register PMDS Read 0 0 0 0 RDS3 RDS2 RDS1 RDS0 Write Reset 0 0 0 0 0 0 0 1 Unimplemented R Reserved NOTES...

Page 125: ... interrupts enabled 0 PLL interrupts disabled PLLF PLL Interrupt Flag Bit This read only bit is set whenever the LOCK bit toggles PLLF generates an interrupt request if the PLLIE bit also is set PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register PBWC is clear Clear the PLLF bit by reading the PLL control register Reset clears the PLLF bit 1 Change in lock conditio...

Page 126: ...g the transition CGMOUT is held in stasis See 7 4 8 Base Clock Selector Circuit Reset clears the BCS bit 1 CGMVCLK divided by two drives CGMOUT 0 CGMXCLK divided by two drives CGMOUT NOTE PLLON and BCS have built in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off Therefore PLLON cannot be cleared when BCS is se...

Page 127: ... 6 2 PLL Bandwidth Control Register The PLL bandwidth control register PBWC Selects automatic or manual software controlled bandwidth control mode Indicates when the PLL is locked In automatic bandwidth control mode indicates when the PLL is in acquisition or tracking mode In manual operation forces the PLL into acquisition or tracking mode Table 7 2 PRE1 and PRE0 Programming PRE1 and PRE0 P Presc...

Page 128: ...ys be written a 0 Reset clears the LOCK bit 1 VCO frequency correct or locked 0 VCO frequency incorrect or unlocked ACQ Acquisition Mode Bit When the AUTO bit is set ACQ is a read only bit that indicates whether the PLL is in acquisition mode or tracking mode When the AUTO bit is clear ACQ is a read write bit that controls whether the PLL is in acquisition or tracking mode In automatic bandwidth c...

Page 129: ...gramming the PLL A value of 0000 in the multiplier select registers configures the modulo feedback divider the same as a value of 0001 Reset initializes the registers to 0040 for a default multiply value of 64 NOTE The multiplier select bits have built in protection such that they cannot be written when the PLL is on PLLON 1 Bit7 Bit4 Unimplemented Bits These bits have no function and always read ...

Page 130: ... Programming the PLL MUL7 MUL0 cannot be written when the PLLON bit in the PCTL is set A value of 0000 in the multiplier select registers configures the modulo feedback divider the same as a value of 0001 Reset initializes the register to 40 for a default multiply value of 64 NOTE The multiplier select bits have built in protection such that they cannot be written when the PLL is on PLLON 1 Addres...

Page 131: ... A value of 00 in the VCO range select register disables the PLL and clears the BCS bit in the PLL control register PCTL See 7 4 8 Base Clock Selector Circuit and 7 4 7 Special Programming Exceptions Reset initializes the register to 40 for a default range multiply value of 64 NOTE The VCO range select bits have built in protection such that they cannot be written when the PLL is on PLLON 1 and su...

Page 132: ... set A value of 00 in the reference divider select register configures the reference divider the same as a value of 01 See 7 4 7 Special Programming Exceptions Reset initializes the register to 01 for a default divide value of 1 NOTE The reference divider select bits have built in protection such that they cannot be written when the PLL is on PLLON 1 NOTE The default divide value of 1 is recommend...

Page 133: ... should be taken If the application is not frequency sensitive interrupts should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations NOTE Software can select the CGMVCLK divided by two as the CGMOUT source even if the PLL is not locked LOCK 0 Therefore software should make sure the PLL is locked before setting the BCS bit 7 8...

Page 134: ...phase locked loop is shut off but the oscillator will continue to operate in stop mode 7 8 3 CGMC During Break Interrupts The system integration module SIM controls whether status bits in other modules can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state See 19 8 3 SIM Break Flag Control Registe...

Page 135: ...ess of the size of the step input For example consider a system with a 5 percent acquisition time tolerance If a command instructs the system to change from 0 Hz to 1 MHz the acquisition time is the time taken for the frequency to reach 1 MHz 50 kHz Fifty kHz 5 of the 1 MHz step input If the system is operating at 1 MHz and suffers a 100 kHz noise hit the acquisition time is the time taken to retu...

Page 136: ...ubtracting charge from capacitors in this network Therefore the rate at which the voltage changes for a given frequency error thus change in charge is proportional to the capacitance The size of the capacitor also is related to the stability of the PLL If the capacitor is too small the PLL cannot make small enough adjustments to the voltage and the system cannot lock If the capacitor is too large ...

Page 137: ...lter network is critical to the stability and reaction time of the PLL The PLL is also dependent on reference frequency and supply voltage Either of the filter networks in Figure 7 10 is recommended when using a 32 768kHz reference crystal Figure 7 10 a is used for applications requiring better stability Figure 7 10 b is used in low cost applications where stability is not critical Figure 7 10 PLL...

Page 138: ...Module CGMC Technical Data MC68HC908GP32 MC68HC08GP32 Rev 6 136 Clock Generator Module CGMC MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 139: ...ng properly module COP Low voltage inhibit LVI module control and voltage trip point selection Enable disable the oscillator OSC during stop mode 8 3 Functional Description The configuration registers are used in the initialization of various options The configuration registers can be written once after each reset All of the configuration register bits are cleared during reset Since the various op...

Page 140: ...etting the OSCSTOPENB bit allows the oscillator to operate continuously even during stop mode This is useful for driving the timebase module to allow it to generate periodic wakeup while in stop mode See 3 6 Clock Generator Module CGM subsection 3 6 2 Stop Mode 1 Oscillator enabled to operate during stop mode 0 Oscillator disabled during stop mode default Address 001E Bit 7 6 5 4 3 2 1 Bit 0 Read ...

Page 141: ...rate during stop mode Reset clears LVISTOP See 3 6 2 Stop Mode 1 LVI enabled during stop mode 0 LVI disabled during stop mode LVIRSTD LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module See Section 14 Low Voltage Inhibit LVI 1 LVI module resets disabled 0 LVI module resets enabled LVIPWRD LVI Power Disable Bit LVIPWRD disables the LVI module See Section 14 Low Voltage Inhib...

Page 142: ...eset and long stop recovery both 4096 CGMXCLK cycles gives a delay longer than the enable time for the LVI There is no period where the MCU is not protected from a low power condition However when using the short stop recovery configuration option the 32 CGMXCLK delay is less than the LVI s turn on time and there exists a period in startup where the LVI is not protecting the MCU STOP STOP Instruct...

Page 143: ...43 9 4 2 STOP Instruction 143 9 4 3 COPCTL Write 144 9 4 4 Power On Reset 144 9 4 5 Internal Reset 144 9 4 6 Reset Vector Fetch 144 9 4 7 COPD COP Disable 144 9 4 8 COPRS COP Rate Select 144 9 5 COP Control Register 145 9 6 Interrupts 145 9 7 Monitor Mode 145 9 8 Low Power Modes 145 9 8 1 Wait Mode 146 9 8 2 Stop Mode 146 9 9 COP Module During Break Mode 146 Freescale Semiconductor I Freescale Sem...

Page 144: ...e disabled through the COPD bit in the CONFIG register 9 3 Functional Description Figure 9 1 shows the structure of the COP module Figure 9 1 COP Block Diagram COPCTL WRITE CGMXCLK RESET VECTOR FETCH RESET CIRCUIT RESET STATUS REGISTER INTERNAL RESET SOURCES 12 BIT COP PRESCALER CLEAR ALL STAGES 6 BIT COP COUNTER COP DISABLE RESET COPCTL WRITE CLEAR COP MODULE COPEN FROM SIM COP COUNTER COP CLOCK ...

Page 145: ...ntering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status register RSR In monitor mode the COP is disabled if the RST pin or the IRQ is held at VTST During the break state VTST on the RST pin disables the COP NOTE Place COP clearing instructions in the main ...

Page 146: ...p 9 4 5 Internal Reset An internal reset clears the COP prescaler and the COP counter 9 4 6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus A reset vector fetch clears the COP prescaler 9 4 7 COPD COP Disable The COPD signal reflects the state of the COP disable bit COPD in the configuration register See Section 8 Configuration Register CONFIG 9 4 8 C...

Page 147: ...7 Monitor Mode When monitor mode is entered with VTST on the IRQ pin the COP is disabled as long as VTST remains on the IRQ pin or the RST pin When monitor mode is entered by having blank reset vectors and not having VTST on the IRQ pin the COP is automatically disabled until a POR occurs 9 8 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes Address ...

Page 148: ...or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode To prevent inadvertently turning off the COP with a STOP instruction a configuration option is available that disables the STOP instruction When the STOP bit in the configuration register has the STOP instruction is disabled execution of a STOP instruction results in an illegal opcode reset 9 9 COP M...

Page 149: ...rithmetic Logic Unit ALU 154 10 6 Low Power Modes 154 10 6 1 Wait Mode 154 10 6 2 Stop Mode 155 10 7 CPU During Break Interrupts 155 10 8 Instruction Set Summary 156 10 9 Opcode Map 163 10 2 Introduction The M68HC08 CPU central processor unit is an enhanced and fully object code compatible version of the M68HC05 CPU The CPU08 Reference Manual Motorola document order number CPU08RM AD contains a de...

Page 150: ...mory space 16 addressing modes Memory to memory data moves without using accumulator Fast 8 bit by 8 bit multiply and 16 bit by 8 bit divide instructions Enhanced binary coded decimal BCD data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes Low power stop and wait modes 10 4 CPU Registers Figure 10 1 shows the five CPU regist...

Page 151: ...ults of arithmetic logic operations ACCUMULATOR A INDEX REGISTER H X STACK POINTER SP PROGRAM COUNTER PC CONDITION CODE REGISTER CCR CARRY BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF CARRY FLAG TWO S COMPLEMENT OVERFLOW FLAG V 1 1 H I N Z C H X 0 0 0 0 7 15 15 15 7 0 Bit 7 6 5 4 3 2 1 Bit 0 Read Write Reset Unaffected by reset Figure 10 2 Accumulator A Freescale Semiconductor I Freesca...

Page 152: ...he next location on the stack During a reset the stack pointer is preset to 00FF The reset stack pointer RSP instruction sets the least significant byte to FF and does not affect the most significant byte The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack In the stack pointer 8 bit offset and 16 bit offset addressing modes the stack pointe...

Page 153: ...tial memory location every time an instruction or operand is fetched Jump branch and interrupt operations load the program counter with an address other than that of the next sequential location During reset the program counter is loaded with the reset vector address located at FFFE and FFFF The vector address is the address of the first instruction to be executed after exiting the reset state Bit...

Page 154: ...T BGE BLE and BLT use the overflow flag 1 Overflow 0 No overflow H Half Carry Flag The CPU sets the half carry flag when a carry occurs between accumulator bits 3 and 4 during an add without carry ADD or add with carry ADC operation The half carry flag is required for binary coded decimal BCD arithmetic operations The DAA instruction uses the states of the H and C flags to determine the appropriat...

Page 155: ...nd unstack H using the PSHH and PULH instructions After the I bit is cleared the highest priority interrupt request is serviced first A return from interrupt RTI instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack After any reset the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction CLI N Negative flag The C...

Page 156: ...ic and logic operations defined by the instruction set Refer to the CPU08 Reference Manual Motorola document order number CPU08RM AD for a description of the instructions and addressing modes and more detail about the architecture of the CPU 10 6 Low Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes 10 6 1 Wait Mode The WAIT instruction Clears the interr...

Page 157: ... Break Interrupts If a break module is present on the MCU the CPU starts a break interrupt by Loading the instruction register with the SWI instruction Loading the program counter with FFFC FFFD or with FEFC FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress If the break address register match occurs on the last cycle of a CPU instruction the break ...

Page 158: ...l ee ff ff ff ee ff 2 3 4 4 3 2 4 5 AIS opr Add Immediate Value Signed to SP SP SP 16 M IMM A7 ii 2 AIX opr Add Immediate Value Signed to H X H X H X 16 M IMM AF ii 2 AND opr AND opr AND opr AND opr X AND opr X AND X AND opr SP AND opr SP Logical AND A A M 0 IMM DIR EXT IX2 IX1 IX SP1 SP2 A4 B4 C4 D4 E4 F4 9EE4 9ED4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ASL opr ASLA ASLX ASL opr X ASL X AS...

Page 159: ... 3 BIH rel Branch if IRQ Pin High PC PC 2 rel IRQ 1 REL 2F rr 3 BIL rel Branch if IRQ Pin Low PC PC 2 rel IRQ 0 REL 2E rr 3 BIT opr BIT opr BIT opr BIT opr X BIT opr X BIT X BIT opr SP BIT opr SP Bit Test A M 0 IMM DIR EXT IX2 IX1 IX SP1 SP2 A5 B5 C5 D5 E5 F5 9EE5 9ED5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 BLE opr Branch if Less Than or Equal To Signed Operands PC PC 2 rel Z N V 1 REL 93 r...

Page 160: ...5 DIR b6 DIR b7 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 BSR rel Branch to Subroutine PC PC 2 push PCL SP SP 1 push PCH SP SP 1 PC PC rel REL AD rr 4 CBEQ opr rel CBEQA opr rel CBEQX opr rel CBEQ opr X rel CBEQ X rel CBEQ opr SP rel Compare and Branch if Equal PC PC 3 rel A M 00 PC PC 3 rel A M 00 PC PC 3 rel X M 00 PC PC 3 rel A M 00 PC PC 2 rel A M 00 PC PC 4 rel A M 00 DI...

Page 161: ...just A A 10 U INH 72 2 DBNZ opr rel DBNZA rel DBNZX rel DBNZ opr X rel DBNZ X rel DBNZ opr SP rel Decrement and Branch if Not Zero A A 1 or M M 1 or X X 1 PC PC 3 rel result 0 PC PC 2 rel result 0 PC PC 2 rel result 0 PC PC 3 rel result 0 PC PC 2 rel result 0 PC PC 4 rel result 0 DIR INH INH IX1 IX SP1 3B 4B 5B 6B 7B 9E6B dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 DEC opr DECA DECX DEC opr X DEC X DEC...

Page 162: ...r LDHX opr Load H X from M H X M M 1 0 IMM DIR 45 55 ii jj dd 3 4 LDX opr LDX opr LDX opr LDX opr X LDX opr X LDX X LDX opr SP LDX opr SP Load X from M X M 0 IMM DIR EXT IX2 IX1 IX SP1 SP2 AE BE CE DE EE FE 9EEE 9EDE ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 LSL opr LSLA LSLX LSL opr X LSL X LSL opr SP Logical Shift Left Same as ASL DIR INH INH IX1 IX SP1 38 48 58 68 78 9E68 dd ff ff 4 1 1 4 3...

Page 163: ...SP 1 INH 89 2 PULA Pull A from Stack SP SP 1 Pull A INH 86 2 PULH Pull H from Stack SP SP 1 Pull H INH 8A 2 PULX Pull X from Stack SP SP 1 Pull X INH 88 2 ROL opr ROLA ROLX ROL opr X ROL X ROL opr SP Rotate Left through Carry DIR INH INH IX1 IX SP1 39 49 59 69 79 9E69 dd ff ff 4 1 1 4 3 5 ROR opr RORA RORX ROR opr X ROR X ROR opr SP Rotate Right through Carry DIR INH INH IX1 IX SP1 36 46 56 66 76 ...

Page 164: ...X opr X STX opr X STX X STX opr SP STX opr SP Store X in M M X 0 DIR EXT IX2 IX1 IX SP1 SP2 BF CF DF EF FF 9EEF 9EDF dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 SUB opr SUB opr SUB opr SUB opr X SUB opr X SUB X SUB opr SP SUB opr SP Subtract A A M IMM DIR EXT IX2 IX1 IX SP1 SP2 A0 B0 C0 D0 E0 F0 9EE0 9ED0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 SWI Software Interrupt PC PC 1 Push PCL SP SP 1 Pu...

Page 165: ... addressing mode EXT Extended addressing mode SP2 Stack pointer 16 bit offset addressing mode ff Offset byte in indexed 8 bit offset addressing SP Stack pointer H Half carry bit U Undefined H Index register high byte V Overflow bit hh ll High and low bytes of operand address in extended addressing X Index register low byte I Interrupt mask Z Zero bit ii Immediate operand byte Logical AND IMD Immed...

Page 166: ...LA 1 INH 1 LSLX 1 INH 4 LSL 2 IX1 5 LSL 3 SP1 3 LSL 1 IX 2 PULX 1 INH 1 CLC 1 INH 2 EOR 2 IMM 3 EOR 2 DIR 4 EOR 3 EXT 4 EOR 3 IX2 5 EOR 4 SP2 3 EOR 2 IX1 4 EOR 3 SP1 2 EOR 1 IX 9 5 BRCLR4 3 DIR 4 BCLR4 2 DIR 3 BHCS 2 REL 4 ROL 2 DIR 1 ROLA 1 INH 1 ROLX 1 INH 4 ROL 2 IX1 5 ROL 3 SP1 3 ROL 1 IX 2 PSHX 1 INH 1 SEC 1 INH 2 ADC 2 IMM 3 ADC 2 DIR 4 ADC 3 EXT 4 ADC 3 IX2 5 ADC 4 SP2 3 ADC 2 IX1 4 ADC 3 S...

Page 167: ... the operation of the embedded FLASH memory This memory can be read programmed and erased from a single external supply The program erase and read operations are enabled through the use of an internal charge pump 11 3 Functional Description The FLASH memory is an array of 32 256 bytes with an additional 36 bytes of user vectors and one byte of block protection An erased bit reads as logic 1 and a ...

Page 168: ... of the FLASH contents 1 11 4 FLASH Control Register The FLASH control register FLCR controls FLASH program and erase operations HVEN High Voltage Enable Bit This read write bit enables the charge pump to drive high voltages for program and erase operations in the array HVEN can only be set if either PGM 1 or ERASE 1 and the proper sequence for program or erase is followed 1 High voltage enabled t...

Page 169: ...e bit configures the memory for program operation PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time 1 Program operation selected 0 Program operation unselected 11 5 FLASH Page Erase Operation Use this step by step procedure to erase a page 128 bytes of FLASH memory to read as logic 1 1 Set the ERASE bit and clear the MASS bit in the FLASH c...

Page 170: ...dress within the FLASH memory address range 4 Wait for a time tnvs min 10µs 5 Set the HVEN bit 6 Wait for a time tMErase min 4ms 7 Clear the ERASE bit 8 Wait for a time tnvhl min 100µs 9 Clear the HVEN bit 10 After a time trcv min 1µs the memory can be accessed again in read mode When in Monitor mode with security sequence failed see 15 5 Security write to the FLASH block protect register instead ...

Page 171: ...e desired 4 Wait for a time tnvs min 10µs 5 Set the HVEN bit 6 Wait for a time tpgs min 5µs 7 Write data to the FLASH address to be programmed See note 8 Wait for a time tPROG min 30µs 9 Repeat step 7 and 8 until all the bytes within the row are programmed 10 Clear the PGM bit See note 11 Wait for a time tnvh min 5µs 12 Clear the HVEN bit 13 After time trcv min 1µs the memory can be accessed in re...

Page 172: ... and ends at the bottom of the FLASH memory FFFF When the memory is protected the HVEN bit cannot be set in either ERASE or PROGRAM operations NOTE In performing a program or erase operation the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit When the FLBPR is program with all 0 s the entire memory is protected from being programmed an...

Page 173: ...it Wait for a time tnvh Clear HVEN bit Wait for a time trcv Completed programming this row Y N End of programming The time between each FLASH address change step 7 to step 7 or must not exceed the maximum programming time tPROG max the time between the last FLASH address programmed to clearing PGM bit step 7 to step 10 NOTE 1 2 3 4 5 6 7 8 10 11 12 13 Algorithm for programming a row 64 bytes of FL...

Page 174: ...ng the start address of the FLASH memory for block protection The FLASH is protected from this start address to the end of FLASH memory at FFFF With this mechanism the protect start address can be XX00 and XX80 128 bytes page boundaries within the FLASH memory Figure 11 4 FLASH Block Protect Start Address Address FF7E Bit 7 6 5 4 3 2 1 Bit 0 Read BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Write Reset...

Page 175: ...ut there will not be any memory activity since the CPU is inactive The STOP instruction should not be executed while performing a program or erase operation on the FLASH otherwise the operation will discontinue and the FLASH will be on Standby Mode NOTE Standby Mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumpt...

Page 176: ...LASH Memory Technical Data MC68HC908GP32 MC68HC08GP32 Rev 6 174 FLASH Memory MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 177: ... 179 12 7 IRQ Status and Control Register 179 12 2 Introduction The IRQ external interrupt module provides a maskable interrupt input 12 3 Features Features of the IRQ module include A dedicated external interrupt pin IRQ IRQ interrupt control bits Hysteresis buffer Programmable edge only or edge and level interrupt sensitivity Automatic interrupt acknowledge Internal pullup resistor Freescale Sem...

Page 178: ...s software configurable to be either falling edge or falling edge and low level triggered The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin When an interrupt pin is edge triggered only the interrupt remains set until a vector fetch software clear or reset occurs When an interrupt pin is both falling edge and low level triggered the interrupt remains set until both of th...

Page 179: ...IGH INTERRUPT TO MODE SELECT LOGIC REQUEST VDD MODE VOLTAGE DETECT IRQF TO CPU FOR BIL BIH INSTRUCTIONS VECTOR FETCH DECODER INTERNAL ADDRESS BUS RESET VDD INTERNAL PULLUP DEVICE ACK IRQ SYNCHRONIZER Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 001D IRQ Status and Control Register INTSCR Read 0 0 0 0 IRQF 0 IMASK MODE Write ACK Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 12 2 IRQ I O Register Summary...

Page 180: ...ansitions on the IRQ pin A falling edge that occurs after writing to the ACK bit another interrupt request If the IRQ mask bit IMASK is clear the CPU loads the program counter with the vector address at locations FFFA and FFFB Return of the IRQ pin to logic 1 As long as the IRQ pin is at logic 0 IRQ remains active The vector fetch or software clear and the return of the IRQ pin to logic 1 may occu...

Page 181: ...CFE bit If a latch is cleared during the break state it remains cleared when the MCU exits the break state To protect CPU interrupt flags during the break state write a logic 0 to the BCFE bit With BCFE at logic 0 its default state writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ interrupt flags 12 7 IRQ Status and Control Register The I...

Page 182: ...1 to this read write bit disables IRQ interrupt requests Reset clears IMASK 1 IRQ interrupt requests disabled 0 IRQ interrupt requests enabled MODE IRQ Edge Level Select Bit This read write bit controls the triggering sensitivity of the IRQ pin Reset clears MODE 1 IRQ interrupt requests on falling edges and low levels 0 IRQ interrupt requests on falling edges only Address 001D Bit 7 6 5 4 3 2 1 Bi...

Page 183: ...p Mode 186 13 7 Keyboard Module During Break Interrupts 186 13 8 I O Registers 187 13 8 1 Keyboard Status and Control Register 187 13 8 2 Keyboard Interrupt Enable Register 188 13 2 Introduction The keyboard interrupt module KBI provides eight independently maskable external interrupts which are accessible via PTA0 PTA7 When a port pin is enabled for keyboard interrupt function an internal pullup ...

Page 184: ...up device A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request A keyboard interrupt is latched when one or more keyboard pins goes low after all were high The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt If the keyboard interrupt is edge sensitive only a falling edge on a keyboard pin does not la...

Page 185: ...P ENABLE KBD7 KBD0 TO PULLUP ENABLE SYNCHRONIZER KEYF Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 001A Keyboard Status and Control Register INTKBSCR Read 0 0 0 0 KEYF 0 IMASKK MODEK Write ACKK Reset 0 0 0 0 0 0 0 0 001B Keyboard Interrupt Enable Register INTKBIER Read KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 13 2 I O Register Summary Freescale...

Page 186: ... bit IMASKK is clear the CPU loads the program counter with the vector address at locations FFE0 and FFE1 Return of all enabled keyboard interrupt pins to logic 1 As long as any enabled keyboard interrupt pin is at logic 0 the keyboard interrupt remains set The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order If the MODEK bit is...

Page 187: ...tus and control register 2 Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register 3 Write to the ACKK bit in the keyboard status and control register to clear any false interrupts 4 Clear the IMASKK bit An interrupt signal on an edge triggered pin can be acknowledged immediately after enabling the pin An interrupt signal on an edge and level triggered i...

Page 188: ...Interrupts The system integration module SIM controls whether the keyboard interrupt latch can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state To allow software to clear the keyboard interrupt latch during a break interrupt write a logic 1 to the BCFE bit If a latch is cleared during the break ...

Page 189: ...es keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity Bits 7 4 Not used These read only bits always read as logic 0s KEYF Keyboard Flag Bit This read only bit is set when a keyboard interrupt is pending Reset clears the KEYF bit 1 Keyboard interrupt pending 0 No keyboard interrupt pending Address 001A Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 ...

Page 190: ...Reset clears MODEK 1 Keyboard interrupt requests on falling edges and low levels 0 Keyboard interrupt requests on falling edges only 13 8 2 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard interrupt pin KBIE7 KBIE0 Keyboard Interrupt Enable Bits Each of these read write bits enables the corresponding keyboard int...

Page 191: ...192 14 5 LVI Status Register 193 14 6 LVI Interrupts 194 14 7 Low Power Modes 194 14 7 1 Wait Mode 194 14 7 2 Stop Mode 194 14 2 Introduction This section describes the low voltage inhibit LVI module which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage VTRIPF 14 3 Features Features of the LVI module include Programmable LVI r...

Page 192: ...after each power on reset If the VDD supply is below the 5 V mode trip voltage but above the 3 V mode trip voltage when POR is released the part will operate because VTRIPF defaults to 3 V mode after a POR So in a 5 V system care must be taken to ensure that VDD is above the 5 V mode trip voltage after POR is released NOTE If the user requires 5 V mode and sets the LVI5OR3 bit after a power on res...

Page 193: ...T bit In the configuration register the LVIPWRD bit must be at logic 0 to enable the LVI module and the LVIRSTD bit must be at logic 1 to disable LVI resets LOW VDD DETECTOR LVIPWRD STOP INSTRUCTION LVISTOP LVI RESET LVIOUT VDD LVITrip 0 VDD LVITrip 1 FROM CONFIG FROM CONFIG1 VDD FROM CONFIG1 LVIRSTD LVI5OR3 FROM CONFIG1 Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 FE0C LVI Status Register LVISR Rea...

Page 194: ...aintain a reset condition until VDD rises above the rising trip point voltage VTRIPR This prevents a condition in which the MCU is continually entering and exiting reset if VDD is approximately equal to VTRIPF VTRIPR is greater than VTRIPF by the hysteresis voltage VHYS 14 4 4 LVI Trip Selection The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5 V or 3 V prot...

Page 195: ...nly flag becomes set when the VDD voltage falls below the VTRIPF trip voltage See Table 14 1 Reset clears the LVIOUT bit Address FE0C Bit 7 6 5 4 3 2 1 Bit 0 Read LVIOUT 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 14 3 LVI Status Register LVISR Table 14 1 LVIOUT Bit Indication VDD LVIOUT VDD VTRIPR 0 VDD VTRIPF 1 VTRIPF VDD VTRIPR Previous value Freescale Semiconductor I Freesca...

Page 196: ...14 7 1 Wait Mode If enabled the LVI module remains active in wait mode If enabled to generate resets the LVI module can generate a reset and bring the MCU out of wait mode 14 7 2 Stop Mode If enabled in stop mode LVISTOP set the LVI module remains active in stop mode If enabled to generate resets the LVI module can generate a reset and bring the MCU out of stop mode Freescale Semiconductor I Frees...

Page 197: ...mmands 203 15 5 Security 208 15 2 Introduction This section describes the monitor ROM MON and the monitor mode entry methods The monitor ROM allows complete testing of the MCU through a single wire interface with a host computer Monitor mode entry can be achieved without use of the higher test voltage VTST as long as vector addresses FFFE and FFFF are blank thus reducing the hardware requirements ...

Page 198: ...tain FF Standard monitor mode entry if high voltage VTST is applied to IRQ 15 4 Functional Description The monitor ROM receives and executes commands from a host computer Figure 15 1 shows an example circuit used to enter monitor mode and communicate with a host computer via a standard RS 232 interface Simple monitor commands can access any memory address In monitor mode the MCU can execute code d...

Page 199: ...SAD VSSA VDDAD D C C C D D 6 30 pF 6 30 pF 32 768 kHz XTAL 10 M Ω SW2 SW1 SW4 SW3 SEE NOTE 2 SEE NOTES 2 SEE NOTE 2 SEE NOTE 3 Notes 1 For monitor mode entry when IRQ VTST SW1 Position A Bus clock CGMXCLK 4 or CGMVCLK 4 SW1 Position B Bus clock CGMXCLK 2 2 SW2 SW3 and SW4 Position C Enter monitor mode using external oscillator SW2 SW3 and SW4 Position D Enter monitor mode using external XTAL and i...

Page 200: ...Mode Table 15 1 shows the pin conditions for entering monitor mode As specified in the table monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met 1 If FFFE and FFFF does not contain FF programmed state The external clock is 4 9152 MHz with PTC3 low or 9 8304 MHz with PTC3 high IRQ VTST PLL off 2 If FFFE and FFFF c...

Page 201: ...RQ V TST PTC3 determines frequency divider X 1 DNA V DD V DD FF blank OFF X X X 9 8304 MHz 4 9152 MHz 2 4576 MHz Disabled 1 0 9600 External frequency always divided by 4 X 1 DNA GND V DD FF blank ON X X X 32 768 kHz 4 9152 MHz 2 4576 MHz Disabled 1 0 9600 PLL enabled BCS set in monitor code X 1 DNA V DD or GND V TST FF blank OFF X X X X Enabled X X Enters user mode will encounter an illegal addres...

Page 202: ...COP module is disabled in monitor mode based on these conditions If monitor mode was entered as a result of the reset vector being blank above condition set 2 or 3 the COP is always disabled regardless of the state of IRQ or RST If monitor mode was entered with VTST on IRQ condition set 1 then the COP is disabled as long as VTST is applied to either IRQ or RST The second condition states that as l...

Page 203: ...ive a command NOTE The PTA7 pin must remain at logic 0 for 24 bus cycles after the RST pin goes high to enter monitor mode properly In monitor mode the MCU uses different vectors for reset SWI software interrupt and break interrupt than those for user mode The alternate vectors are in the FE page instead of the FF page and allow code execution from the internal monitor firmware instead of user cod...

Page 204: ...e monitor receives a break signal it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal Figure 15 4 Break Transaction Table 15 2 Mode Differences Modes Functions Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User FFFE FFFF FFFC FFFD FFFC FFFD Monitor FEFE FEFF FEFC FEFD FEFC FEFD BIT 5 START BIT BIT 1 N...

Page 205: ... entry require that the reset vector is blank Table 15 3 lists external frequencies required to achieve a standard baud rate of 9600 BPS Other standard baud rates can be accomplished using proportionally higher or lower frequency generators If using a crystal as the clock source be aware of the upper frequency limit that the internal clock module can handle See 23 8 5 0 V Control Timing and 23 9 3...

Page 206: ... byte of the command NOTE Wait one bit time after each echo before sending the next byte Figure 15 5 Read Transaction Figure 15 6 Write Transaction READ READ ECHO FROM HOST ADDRESS HIGH ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA RETURN 1 3 2 1 1 4 4 Notes 2 Data return delay 2 bit times 3 Cancel command delay 11 bit times 4 Wait 1 bit time before sending next byte 4 4 1 Echo delay 2 bit times WRITE...

Page 207: ...ontents of specified address Opcode 4A Command Sequence Table 15 5 WRITE Write Memory Command Description Write byte to memory Operand 2 byte address in high byte low byte order low byte followed by data byte Data Returned None Opcode 49 Command Sequence READ READ ECHO SENT TO MONITOR ADDRESS HIGH ADDRESS HIGH ADDRESS LOW DATA RETURN ADDRESS LOW WRITE WRITE ECHO FROM HOST ADDRESS HIGH ADDRESS HIGH...

Page 208: ... order Data Returned Returns contents of next two addresses Opcode 1A Command Sequence Table 15 7 IWRITE Indexed Write Command Description Write to last address accessed 1 Operand Single data byte Data Returned None Opcode 19 Command Sequence IREAD IREAD ECHO FROM HOST DATA RETURN DATA IWRITE IWRITE ECHO FROM HOST DATA DATA Freescale Semiconductor I Freescale Semiconductor Inc For More Information...

Page 209: ...on Reads stack pointer Operand None Data Returned Returns incremented stack pointer value SP 1 in high byte low byte order Opcode 0C Command Sequence Table 15 9 RUN Run User Program Command Description Executes PULH and RTI instructions Operand None Data Returned None Opcode 28 Command Sequence READSP READSP ECHO FROM HOST SP RETURN SP HIGH LOW RUN RUN ECHO FROM HOST Freescale Semiconductor I Free...

Page 210: ...ytes at locations FFF6 FFFD Locations FFF6 FFFD contain user defined data NOTE Do not leave locations FFF6 FFFD blank For security reasons program locations FFF6 FFFD even if they are not used for vectors During monitor mode entry the MCU waits after the power on reset for the host to send the eight security bytes on pin PTA0 If the received bytes match those at locations FFF6 FFFD the host bypass...

Page 211: ...it a break character until after the host sends the eight security bytes To determine whether the security code entered is correct check to see if bit 6 of RAM address 40 is set If it is then the correct security code has been entered and FLASH can be accessed If the security sequence fails the device should be reset by a power on reset and brought up in monitor mode to attempt another entry After...

Page 212: ...LASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM The mass erase operation clears the security code locations so that all eight security bytes become FF blank Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 213: ... 219 16 4 1 Port B Data Register 219 16 4 2 Data Direction Register B 220 16 5 Port C 222 16 5 1 Port C Data Register 222 16 5 2 Data Direction Register C 223 16 5 3 Port C Input Pullup Enable Register 225 16 6 Port D 226 16 6 1 Port D Data Register 226 16 6 2 Data Direction Register D 228 16 6 3 Port D Input Pullup Enable Register 230 16 7 Port E 230 16 7 1 Port E Data Register 231 16 7 2 Data Di...

Page 214: ...ermination reduces excess current consumption and the possibility of electrostatic damage Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 0000 Port A Data Register PTA Read PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Write Reset Unaffected by reset 0001 Port B Data Register PTB Read PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 Write Reset Unaffected by reset 0002 Port C Data Register PTC Read 0 PTC6 PTC5 PTC4 P...

Page 215: ... reset 000C Data Direction Register E DDRE Read 0 0 0 0 0 0 DDRE1 DDRE0 Write Reset 0 0 0 0 0 0 0 0 000D Port A Input Pullup Enable Register PTAPUE Read PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Write Reset 0 0 0 0 0 0 0 0 000E Port C Input Pullup Enable Register PTCPUE Read 0 PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0 Write Reset 0 0 0 0 0 0 0 0 000F Port D Inpu...

Page 216: ...ADCH0 PTB0 AD0 1 DDRB1 PTB1 AD1 2 DDRB2 PTB2 AD2 3 DDRB3 PTB3 AD3 4 DDRB4 PTB4 AD4 5 DDRB5 PTB5 AD5 6 DDRB6 PTB6 AD6 7 DDRB7 PTB7 AD7 C 0 DDRC0 PTC0 1 DDRC1 PTC1 2 DDRC2 PTC2 3 DDRC3 PTC3 4 DDRC4 PTC4 5 DDRC5 PTC5 6 DDRC6 PTC6 D 0 DDRD0 SPI SPE PTD0 SS 1 DDRD1 PTD1 MISO 2 DDRD2 PTD2 MOSI 3 DDRD3 PTD3 SPSCK 4 DDRD4 TIM1 ELS0B ELS0A PTD4 T1CH0 5 DDRD5 ELS1B ELS1A PTD5 T1CH1 6 DDRD6 TIM2 ELS0B ELS0A ...

Page 217: ...programmable Data direction of each port A pin is under the control of the corresponding bit in data direction register A Reset has no effect on port A data KBD7 KBD0 Keyboard Inputs The keyboard interrupt enable bits KBIE7 KBIE0 in the keyboard interrupt control register KBICR enable the port A pins as external interrupt pins See Section 13 Keyboard Interrupt Module KBI Address 0000 Bit 7 6 5 4 3...

Page 218: ...l port A data direction Reset clears DDRA7 DDRA0 configuring all port A pins as inputs 1 Corresponding port A pin configured as output 0 Corresponding port A pin configured as input NOTE Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1 Figure 16 4 shows the port A I O logic Address 0004 Bit 7 6 5 4 3 2 1 Bit 0 Read DDRA...

Page 219: ...4 WRITE DDRA 0004 RESET WRITE PTA 0000 READ PTA 0000 PTAx DDRAx PTAx INTERNAL DATA BUS VDD PTAPUEx INTERNAL PULLUP DEVICE Table 16 2 Port A Pin Functions PTAPUE Bit DDRA Bit PTA Bit I O Pin Mode Accesses to DDRA Accesses to PTA Read Write Read Write 1 0 X 1 Input VDD 4 DDRA7 DDRA0 Pin PTA7 PTA0 3 0 0 X Input Hi Z 2 DDRA7 DDRA0 Pin PTA7 PTA0 3 X 1 X Output DDRA7 DDRA0 PTA7 PTA0 PTA7 PTA0 NOTES 1 X ...

Page 220: ...ically disabled when a port bit s DDRA is configured for output mode PTAPUE7 PTAPUE0 Port A Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit 1 Corresponding port A pin configured to have internal pullup 0 Corresponding port A pin has internal pullup disconnected Address 000D Bit 7 6 5 4 3 2 1 Bit 0 Read PTAPUE7 PTAPUE6 PTAPUE5 PTA...

Page 221: ...er module The channel select bits in the ADC status and control register define which port B pin will be used as an ADC input and overrides any control from the port I O logic by forcing that pin as the input to the analog circuitry NOTE Care must be taken when reading port B while applying analog voltages to AD7 AD0 pins If the appropriate ADC channel is not enabled excessive current drain may oc...

Page 222: ...ort B pins as inputs 1 Corresponding port B pin configured as output 0 Corresponding port B pin configured as input NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1 Figure 16 8 shows the port B I O logic Figure 16 8 Port B I O Circuit Address 0005 Bit 7 6 5 4 3 2 1 Bit 0 Read DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDR...

Page 223: ...s of the state of its data direction bit Table 16 3 summarizes the operation of the port B pins Table 16 3 Port B Pin Functions DDRB Bit PTB Bit I O Pin Mode Accesses to DDRB Accesses to PTB Read Write Read Write 0 X 1 Input Hi Z 2 DDRB7 DDRB0 Pin PTB7 PTB0 3 1 X Output DDRB7 DDRB0 PTB7 PTB0 PTB7 PTB0 Notes 1 X Don t care 2 Hi Z High impedance 3 Writing affects data register but does not affect in...

Page 224: ...of PTC are not available in a 40 pin dual in line package and 42 pin shrink dual in line package PTC6 PTC0 Port C Data Bits These read write bits are software programmable Data direction of each port C pin is under the control of the corresponding bit in data direction register C Reset has no effect on port C data Address 0002 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 Write...

Page 225: ...nfigured as output 0 Corresponding port C pin configured as input NOTE Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1 Figure 16 11 shows the port C I O logic NOTE For those devices packaged in a 40 pin dual in line package and 42 pin shrink dual in line package PTC5 and PTC6 are connected to ground internally DDRC5 an...

Page 226: ...RITE DDRC 0006 RESET WRITE PTC 0002 READ PTC 0002 PTCx DDRCx PTCx INTERNAL DATA BUS VDD PTCPUEx INTERNAL PULLUP DEVICE Table 16 4 Port C Pin Functions PTCPUE Bit DDRC Bit PTC Bit I O Pin Mode Accesses to DDRC Accesses to PTC Read Write Read Write 1 0 X 1 Input VDD 4 DDRC6 DDRC0 Pin PTC6 PTC0 3 0 0 X Input Hi Z 2 DDRC6 DDRC0 Pin PTC6 PTC0 3 X 1 X Output DDRC6 DDRC0 PTC6 PTC0 PTC6 PTC0 Notes 1 X Don...

Page 227: ...mically disabled when a port bit s DDRC is configured for output mode PTCPUE6 PTCPUE0 Port C Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit 1 Corresponding port C pin configured to have internal pullup 0 Corresponding port C pin internal pullup disconnected Address 000E Bit 7 6 5 4 3 2 1 Bit 0 Read 0 PTCPUE6 PTCPUE5 PTCPUE4 PTCP...

Page 228: ...d write bits are software programmable Data direction of each port D pin is under the control of the corresponding bit in data direction register D Reset has no effect on port D data T2CH1 and T2CH0 Timer 2 Channel I O Bits The PTD7 T2CH1 PTD6 T2CH0 pins are the TIM2 input capture output compare pins The edge level select bits ELSxB ELSxA determine whether the PTD7 T2CH1 PTD6 T2CH0 pins are timer ...

Page 229: ...n is available for general purpose I O MISO Master In Slave Out The PTD1 MISO pin is the master in slave out terminal of the SPI module When the SPI enable bit SPE is clear the SPI module is disabled and the PTD0 SS pin is available for general purpose I O Data direction register D DDRD does not affect the data direction of port D pins that are being used by the SPI module However the DDRD bits al...

Page 230: ...1 Corresponding port D pin configured as output 0 Corresponding port D pin configured as input NOTE Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1 Figure 16 15 shows the port D I O logic NOTE For those devices packaged in a 40 pin dual in line package PTD6 and PTD7 are not connected DDRD6 and DDRD7 should be set to a ...

Page 231: ...7 WRITE DDRD 0007 RESET WRITE PTD 0003 READ PTD 0003 PTDx DDRDx PTDx INTERNAL DATA BUS VDD PTDPUEx INTERNAL PULLUP DEVICE Table 16 5 Port D Pin Functions PTDPUE Bit DDRD Bit PTD Bit I O Pin Mode Accesses to DDRD Accesses to PTD Read Write Read Write 1 0 X 1 Input VDD 4 DDRD7 DDRD0 Pin PTD7 PTD0 3 0 0 X Input Hi Z 2 DDRD7 DDRD0 Pin PTD7 PTD0 3 X 1 X Output DDRD7 DDRD0 PTD7 PTD0 PTD7 PTD0 Notes 1 X ...

Page 232: ...e PTDPUE7 PTDPUE0 Port D Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit 1 Corresponding port D pin configured to have internal pullup 0 Corresponding port D pin has internal pullup disconnected 16 7 Port E Port E is a 2 bit special function port that shares two of its pins with the serial communications interface SCI module Addr...

Page 233: ... pins See Table 16 6 RxD SCI Receive Data Input The PTE1 RxD pin is the receive data input for the SCI module When the enable SCI bit ENSCI is clear the SCI module is disabled and the PTE1 RxD pin is available for general purpose I O See Section 18 Serial Communications Interface Module SCI TxD SCI Transmit Data Output The PTE0 TxD pin is the transmit data output for the SCI module When the enable...

Page 234: ...ntrol port E data direction Reset clears DDRE1 and DDRE0 configuring all port E pins as inputs 1 Corresponding port E pin configured as output 0 Corresponding port E pin configured as input NOTE Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1 Figure 16 19 shows the port E I O logic Address 000C Bit 7 6 5 4 3 2 1 Bit 0 ...

Page 235: ...on bit Table 16 6 summarizes the operation of the port E pins READ DDRE 000C WRITE DDRE 000C RESET WRITE PTE 0008 READ PTE 0008 PTEx DDREx PTEx INTERNAL DATA BUS Table 16 6 Port E Pin Functions DDRE Bit PTE Bit I O Pin Mode Accesses to DDRE Accesses to PTE Read Write Read Write 0 X 1 Input Hi Z 2 DDRE1 DDRE0 Pin PTE1 PTE0 3 1 X Output DDRE1 DDRE0 PTE1 PTE0 PTE1 PTE0 Notes 1 X Don t care 2 Hi Z Hig...

Page 236: ...t I O Ports Technical Data MC68HC908GP32 MC68HC08GP32 Rev 6 234 Input Output I O Ports MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 237: ...k pointer must point only to RAM locations Within page zero are 192 bytes of RAM Because the location of the stack RAM is programmable all page zero RAM locations can be used for I O control and user data or code When the stack pointer is moved from its reset location at 00FF out of page zero direct addressing mode instructions can efficiently access all page zero RAM locations Page zero RAM there...

Page 238: ...tack to store the return address The stack pointer decrements during pushes and increments during pulls NOTE Be careful when using nested subroutines The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 239: ...6 18 5 2 4 Idle Characters 246 18 5 2 5 Inversion of Transmitted Output 247 18 5 2 6 Transmitter Interrupts 247 18 5 3 Receiver 248 18 5 3 1 Character Length 248 18 5 3 2 Character Reception 248 18 5 3 3 Data Sampling 250 18 5 3 4 Framing Errors 252 18 5 3 5 Baud Rate Tolerance 252 18 5 3 6 Receiver Wakeup 255 18 5 3 7 Receiver Interrupts 256 18 5 3 8 Error Interrupts 256 18 6 Low Power Modes 257 ...

Page 240: ...onous communications with peripheral devices and other MCUs NOTE References to DMA direct memory access and associated functions are only valid if the MCU has a DMA module This MCU does not have the DMA function Any DMA related register bits should be left in their reset state for normal MCU operation 18 3 Features Features of the SCI module include Full duplex operation Standard mark space non re...

Page 241: ...on with eight interrupt flags Transmitter empty Transmission complete Receiver full Idle receiver input Receiver overrun Noise error Framing error Parity error Receiver framing error detection Hardware parity checking 1 16 bit time noise detection Configuration register bit SCIBDSRC to allow selection of baud rate clock source Freescale Semiconductor I Freescale Semiconductor Inc For More Informat...

Page 242: ...e 18 1 shows the structure of the SCI module The SCI allows full duplex asynchronous NRZ serial communication among the MCU and remote devices including other MCUs The transmitter and receiver of the SCI operate independently although they use the same baud rate generator During normal operation the CPU monitors the status of the SCI writes the data to be transmitted and processes received data Th...

Page 243: ...SCIDATA REGISTER TRANSMIT SHIFT REGISTER NEIE M WAKE ILTY FLAG CONTROL TRANSMIT CONTROL RECEIVE CONTROL DATA SELECTION CONTROL WAKEUP PTY PEN REGISTER DMA INTERRUPT CONTROL TRANSMITTER INTERRUPT CONTROL RECEIVER INTERRUPT CONTROL ERROR INTERRUPT CONTROL CONTROL DMARE ENSCI LOOPS ENSCI PTE1 RxD PTE0 TxD INTERNAL BUS TXINV LOOPS 4 16 PRE SCALER BAUD DIVIDER CGMXCLK BUSCLOCK A B SL X SCIBDSRC FROM SL...

Page 244: ...d R8 T8 DMARE DMATE ORIE NEIE FEIE PEIE Write Reset U U 0 0 0 0 0 0 0016 SCI Status Register 1 SCS1 Read SCTE TC SCRF IDLE OR NF FE PE Write Reset 1 1 0 0 0 0 0 0 0017 SCI Status Register 2 SCS2 Read BKF RPF Write Reset 0 0 0 0 0 0 0 0 0018 SCI Data Register SCDR Read R7 R6 R5 R4 R3 R2 R1 R0 Write T7 T6 T5 T4 T3 T2 T1 T0 Reset Unaffected by reset 0019 SCI Baud Rate Register SCBR Read SCP1 SCP0 R S...

Page 245: ...structure of the SCI transmitter The baud rate clock source for the SCI can be selected via the configuration bit SCIBDSRC Source selection values are shown in Figure 18 4 BIT 5 START BIT BIT 0 BIT 1 NEXT STOP BIT START BIT 8 BIT DATA FORMAT BIT M IN SCC1 CLEAR START BIT BIT 0 NEXT STOP BIT START BIT 9 BIT DATA FORMAT BIT M IN SCC1 SET BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 2 BIT 3 BI...

Page 246: ... SCI DATA REGISTER LOAD FROM SCDR SHIFT ENABLE PREAMBLE ALL 1s BREAK ALL 0s TRANSMITTER CONTROL LOGIC SHIFT REGISTER DMATE TC SCTIE TCIE SCTE TRANSMITTER CPU INTERRUPT REQUEST TRANSMITTER DMA SERVICE REQUEST M ENSCI LOOPS TE PTE0 TxD TXINV INTERNAL BUS 4 PRE SCALER SCP1 SCP0 SCR2 SCR1 SCR0 BAUD DIVIDER 16 SCTIE CGMXCLK BUS CLOCK A B SL X SL 0 X A SL 1 X B SCIBDSRC FROM CONFIG2 Freescale Semiconduc...

Page 247: ...1 and then writing to the SCDR 4 Repeat step 3 for each subsequent transmission At the start of a transmission transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s After the preamble shifts out control logic transfers the SCDR data into the transmit shift register A logic 0 start bit automatically goes into the least significant bit position of the ...

Page 248: ... is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be Receiving a break character has these effects on SCI registers Sets the framing error bit FE in SCS1 Sets the SCI receiver full bit SCRF in SCS1 Clears the SCI data register SCDR Clears the R8 bit in SCC3 Sets the break flag bit BKF in SCS2 May set the overrun OR noise flag NF parity error PE or reception in...

Page 249: ... start and stop bits are inverted when TXINV is at logic 1 See 18 9 1 SCI Control Register 1 18 5 2 6 Transmitter Interrupts These conditions can generate CPU interrupt requests from the SCI transmitter SCI transmitter empty SCTE The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register SCTE can generate a transmitter CPU interrupt request Setting the ...

Page 250: ...bit bit 7 18 5 3 2 Character Reception During an SCI reception the receive shift register shifts characters in from the PTE1 RxD pin The SCI data register SCDR is the read only buffer between the internal data bus and the receive shift register After a complete character shifts into the receive shift register the data portion of the character transfers to the SCDR The SCI receiver full bit SCRF in...

Page 251: ...DMARE SCRF OR ORIE NF NEIE FE FEIE PE PEIE DMARE SCRIE SCRF ILIE IDLE WAKEUP LOGIC PARITY CHECKING MSB ERROR CPU INTERRUPT REQUEST DMA SERVICE REQUEST CPU INTERRUPT REQUEST SCI DATA REGISTER R8 DMARE ORIE NEIE FEIE PEIE SCRIE ILIE RWU SCRF IDLE OR NF FE PE PTE1 RxD INTERNAL BUS PRE SCALER BAUD DIVIDER 4 16 SCP1 SCP0 SCR2 SCR1 SCR0 SCRIE DMARE CGMXCLK BUS CLOCK A B SL X SCIBDSRC FROM SL 0 X A SL 1 ...

Page 252: ...amples at RT8 RT9 and RT10 returns a valid logic 1 and the majority of the next RT8 RT9 and RT10 samples returns a valid logic 0 To locate the start bit data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s When the falling edge of a possible start bit occurs the RT clock begins to count to 16 Figure 18 6 Receiver Data Sampling RT CLOCK RESET RT1 RT1 RT1 RT1 RT1 ...

Page 253: ...uccessful the RT clock is reset and a new search for a start bit begins To determine the value of a data bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 Table 18 3 summarizes the results of the data bit samples Table 18 2 Start Bit Verification RT3 RT5 and RT7 Samples Start Bit Verification Noise Flag 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No 0 111 N...

Page 254: ...uld be in an incoming character it sets the framing error bit FE in SCS1 A break character also sets the FE bit because a break character has no stop bit The FE bit is set at the same time that the SCRF bit is set 18 5 3 5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate Accumulated bit time misalignment can cause one of the three stop...

Page 255: ... for the stop bit data samples at RT8 RT9 and RT10 Figure 18 7 Slow Data For an 8 bit character data sampling of the stop bit takes the receiver 9 bit times 16 RT cycles 10 RT cycles 154 RT cycles With the misaligned character shown in Figure 18 7 the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times 16 RT cycles 3 RT cycles 147 RT cycles The maxim...

Page 256: ... RT10 instead of RT16 but is still there for the stop bit data samples at RT8 RT9 and RT10 Figure 18 8 Fast Data For an 8 bit character data sampling of the stop bit takes the receiver 9 bit times 16 RT cycles 10 RT cycles 154 RT cycles With the misaligned character shown in Figure 18 8 the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times 16 RT c...

Page 257: ...abled Depending on the state of the WAKE bit in SCC1 either of two conditions on the PTE1 RxD pin can bring the receiver out of the standby state Address mark An address mark is a logic 1 in the most significant bit position of a received character When the WAKE bit is set an address mark wakes the receiver from the standby state by clearing the RWU bit The address mark also sets the SCI receiver ...

Page 258: ...receiver CPU interrupts Idle input IDLE The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in from the PTE1 RxD pin The idle line interrupt enable bit ILIE in SCC2 enables the IDLE bit to generate CPU interrupt requests 18 5 3 8 Error Interrupts The following receiver error flags in SCS1 can generate CPU interrupt requests Receiver overrun OR The OR bit indicates that the re...

Page 259: ...e execution of a WAIT instruction In wait mode the SCI module registers are not accessible by the CPU Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode If SCI module functions are not required during wait mode reduce power consumption by disabling the module before executing the WAIT instruction Refer to Section 3 Low Power Modes for information on exiting wa...

Page 260: ...status bits have a 2 step read write clearing procedure If software does the first step on such a bit before the break the bit cannot change during the break state as long as BCFE is at logic 0 After the break doing the second step clears the status bit 18 8 I O Signals Port E shares two of its pins with the SCI module The two SCI I O pins are PTE0 TxD Transmit data PTE1 RxD Receive data 18 8 1 PT...

Page 261: ...ntrol register 3 SCC3 SCI status register 1 SCS1 SCI status register 2 SCS2 SCI data register SCDR SCI baud rate register SCBR 18 9 1 SCI Control Register 1 SCI control register 1 Enables loop mode operation Enables the SCI Controls output polarity Controls character length Controls SCI wakeup method Controls idle character detection Enables parity function Controls parity type Freescale Semicondu...

Page 262: ...I and the SCI baud rate generator Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts Reset clears the ENSCI bit 1 SCI enabled 0 SCI disabled TXINV Transmit Inversion Bit This read write bit reverses the polarity of transmitted data Reset clears the TXINV bit 1 Transmitter output inverted 0 Transmitter output not inverted NOTE Setting the TXINV bit...

Page 263: ...e Bit This read write bit determines when the SCI starts counting logic 1s as idle character bits The counting begins either after the start bit or after the stop bit If the count begins after the start bit then a string of logic 1s preceding the stop bit may cause false recognition of an idle character Beginning the count after the stop bit avoids false idle character recognition but requires pro...

Page 264: ...following CPU interrupt requests Enables the SCTE bit to generate transmitter CPU interrupt requests Enables the TC bit to generate transmitter CPU interrupt requests Enables the SCRF bit to generate receiver CPU interrupt requests Enables the IDLE bit to generate receiver CPU interrupt requests Table 18 5 Character Format Selection Control Bits Character Format M PEN and PTY Start Bits Data Bits ...

Page 265: ...it 1 TC enabled to generate CPU interrupt requests 0 TC not enabled to generate CPU interrupt requests SCRIE SCI Receive Interrupt Enable Bit This read write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests Reset clears the SCRIE bit 1 SCRF enabled to generate CPU interrupt 0 SCRF not enabled to generate CPU interrupt ILIE Idle Line Interrupt Enable Bit This read write bit ...

Page 266: ...he TE bit is not allowed when the enable SCI bit ENSCI is clear ENSCI is in SCI control register 1 RE Receiver Enable Bit Setting this read write bit enables the receiver Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits Reset clears the RE bit 1 Receiver enabled 0 Receiver disabled NOTE Writing to the RE bit is not allowed when the enable SCI bit ENSCI is ...

Page 267: ...ng transmitted NOTE Do not toggle the SBK bit immediately after setting the SCTE bit Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble 18 9 3 SCI Control Register 3 SCI control register 3 Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted Enables these interrupts Receiver overrun interrupts Noise error interrupts...

Page 268: ...smit shift register Reset has no effect on the T8 bit DMARE DMA Receive Enable Bit CAUTION The DMA module is not included on this MCU Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance 1 DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit SCI receiver CPU interrupt requests enabled 0 DMA not enabled to service SCI receiver DMA service reques...

Page 269: ...interrupt requests from NE bit enabled 0 SCI error CPU interrupt requests from NE bit disabled FEIE Receiver Framing Error Interrupt Enable Bit This read write bit enables SCI error CPU interrupt requests generated by the framing error bit FE Reset clears FEIE 1 SCI error CPU interrupt requests from FE bit enabled 0 SCI error CPU interrupt requests from FE bit disabled PEIE Receiver Parity Error I...

Page 270: ...is set when the SCDR transfers a character to the transmit shift register SCTE can generate an SCI transmitter CPU interrupt request When the SCTIE bit in SCC2 is set SCTE generates an SCI transmitter CPU interrupt request In normal operation clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR Reset sets the SCTE bit 1 SCDR data transferred to transmit shift register 0 SCDR d...

Page 271: ...eceiver CPU interrupt request When the SCRIE bit in SCC2 is set SCRF generates a CPU interrupt request In normal operation clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR Reset clears SCRF 1 Received data available in SCDR 0 Data not available in SCDR IDLE Receiver Idle Bit This clearable read only bit is set when 10 or 11 consecutive logic 1s appear on the receiver inpu...

Page 272: ... not set when SCS1 was read Byte 2 caused the overrun and is lost The next flag clearing sequence reads byte 3 in the SCDR instead of byte 2 In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun the flag clearing routine can check the OR bit in a second read of SCS1 after reading the data register NF Receiver Noise Flag Bit Th...

Page 273: ...h PE set and then reading the SCDR Reset clears the PE bit 1 Parity error detected 0 No parity error detected BYTE 1 NORMAL FLAG CLEARING SEQUENCE READ SCS1 SCRF 1 READ SCDR BYTE 1 SCRF 1 SCRF 1 BYTE 2 BYTE 3 BYTE 4 OR 0 READ SCS1 SCRF 1 OR 0 READ SCDR BYTE 2 SCRF 0 READ SCS1 SCRF 1 OR 0 SCRF 1 SCRF 0 READ SCDR BYTE 3 SCRF 0 BYTE 1 READ SCS1 SCRF 1 READ SCDR BYTE 1 SCRF 1 SCRF 1 BYTE 2 BYTE 3 BYTE...

Page 274: ...r on the PTE1 RxD pin followed by another break character Reset clears the BKF bit 1 Break character detected 0 No break character detected RPF Reception in Progress Flag Bit This read only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit search RPF does not generate an interrupt request RPF is reset after the receiver detects false start bits usually from...

Page 275: ...gister R7 T7 R0 T0 Receive Transmit Data Bits Reading the SCDR accesses the read only received data bits R7 R0 Writing to the SCDR writes the data to be transmitted T7 T0 Reset has no effect on the SCDR NOTE Do not use read modify write instructions on the SCI data register Address 0018 Bit 7 6 5 4 3 2 1 Bit 0 Read R7 R6 R5 R4 R3 R2 R1 R0 Write T7 T6 T5 T4 T3 T2 T1 T0 Reset Unaffected by reset Fig...

Page 276: ...divisor as shown in Table 18 6 Reset clears SCP1 and SCP0 SCR2 SCR0 SCI Baud Rate Select Bits These read write bits select the SCI baud rate divisor as shown in Table 18 7 Reset clears SCR2 SCR0 Address 0019 Bit 7 6 5 4 3 2 1 Bit 0 Read SCP1 SCP0 R SCR2 SCR1 SCR0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 18 16 SCI Baud Rate Register SCBR Table 18 6 SCI Baud Rate Prescaling SCP1 a...

Page 277: ...t in CONFIG2 register PD prescaler divisor BD baud rate divisor Table 18 8 shows the SCI baud rates that can be generated with a 4 9152 MHz bus clock when fBUS is selected as SCI clock source Table 18 7 SCI Baud Rate Selection SCR2 SCR1 and SCR0 Baud Rate Divisor BD 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate SCI clock source 64 PD BD Freescale Semiconductor I Freescale Semicond...

Page 278: ... 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25 600 01 3 001 2 12 800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19 200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 11 13 010 4 1477 11 13 011 8 739 11 13 100 ...

Page 279: ...perating Properly COP Reset 286 19 4 2 3 Illegal Opcode Reset 286 19 4 2 4 Illegal Address Reset 286 19 4 2 5 Low Voltage Inhibit LVI Reset 287 19 4 2 6 Monitor Mode Entry Module Reset MODRST 287 19 5 SIM Counter 287 19 5 1 SIM Counter During Power On Reset 287 19 5 2 SIM Counter During Stop Mode Recovery 288 19 5 3 SIM Counter and Reset States 288 19 6 Exception Control 288 19 6 1 Interrupts 288 ...

Page 280: ... is a summary of the SIM input output I O registers The SIM is a system state controller that coordinates CPU and exception timing The SIM is responsible for Bus clock generation and control for CPU and peripherals Stop wait reset break entry and recovery Internal clock control Master reset control including power on reset POR and COP timeout Interrupt control Acknowledge timing Arbitration contro...

Page 281: ... CPU ILLEGAL ADDRESS FROM ADDRESS MAP DECODERS COP FROM COP MODULE INTERRUPT SOURCES CPU INTERFACE RESET CONTROL SIM COUNTER COP CLOCK CGMXCLK FROM CGM 2 VDD INTERNAL PULLUP DEVICE Table 19 1 Signal Name Conventions Signal Name Description CGMXCLK Buffered version of OSC1 from clock generator module CGM CGMVCLK PLL output CGMOUT PLL based or OSC1 based clock output from CGM module Bus clock CGMOUT...

Page 282: ...d R R R R R R R R Write Reset FE03 SIM Break Flag Control Register SBFCR Read BCFE R R R R R R R Write Reset 0 FE04 Interrupt Status Register 1 INT1 Read IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 FE05 Interrupt Status Register 2 INT2 Read IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 FE06 Interrupt Status Register 3 INT3 Read 0 0 0 0...

Page 283: ... CGM Clock Signals 19 3 1 Bus Timing In user mode the internal bus frequency is either the crystal oscillator output CGMXCLK divided by four or the PLL output CGMVCLK divided by four 19 3 2 Clock Startup from POR or LVI Reset When the power on reset module or the low voltage inhibit module generates a reset the clocks to the CPU and peripherals are inactive 2 BUS CLOCK GENERATORS SIM SIM COUNTER M...

Page 284: ...es Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode Some modules can be programmed to be active in wait mode 19 4 Reset and System Initialization The MCU has these reset sources Power on reset module POR External reset pin RST Computer operating properly module COP Low voltage inhibit module LVI Illegal opcode Illegal address All of these res...

Page 285: ...tus register SRSR is set as long as RST is held low for a minimum of 67 CGMXCLK cycles assuming that neither the POR nor the LVI was the source of the reset See Table 19 2 for details Figure 19 4 shows the relative timing Figure 19 4 External Reset Timing Table 19 2 PIN Bit Set Timing Reset Type Number of Cycles Required to Set PIN POR LVI 4163 4096 64 3 All others 67 64 3 RST IAB PC VECT H VECT L...

Page 286: ...or POR resets the SIM cycles through 4096 32 CGMXCLK cycles during which the SIM forces the RST pin low The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 19 5 Figure 19 5 Internal Reset Timing The COP reset is asynchronous to the bus clock Figure 19 6 Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals an...

Page 287: ...o allow the reset vector sequence to occur At power on these events occur A POR pulse is generated The internal reset signal is asserted The SIM enables CGMOUT Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow stabilization of the oscillator The RST pin is driven low during the oscillator stabilization time The POR bit of the SIM reset status register SRSR i...

Page 288: ...onal logic conditioned with the high voltage signal on the RST or the IRQ pin This prevents the COP from becoming disabled as a result of external noise During a break state VTST on the RST pin disables the COP module 19 4 2 3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions An illegal instruction sets the ILOP bit in the SIM reset status register SRSR and c...

Page 289: ...here the reset vectors are blank FF See 15 4 1 Entering Monitor Mode When MODRST gets asserted an internal reset occurs The SIM actively pulls down the RST pin for all internal reset sources 19 5 SIM Counter The SIM counter is used by the power on reset module POR and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus IBUS clocks The SIM counter also s...

Page 290: ...with SSREC cleared 19 5 3 SIM Counter and Reset States External reset has no effect on the SIM counter See 19 7 2 Stop Mode for details The SIM counter is free running after all reset states See 19 4 2 Active Resets from Internal Sources for counter control and internal reset recovery sequences 19 6 Exception Control Normal sequential program execution can be changed in three different ways Interr...

Page 291: ...etch Once an interrupt is latched by the SIM no other interrupt can take precedence regardless of priority until the latched interrupt is serviced or the I bit is cleared See Figure 19 10 Figure 19 8 Interrupt Entry Timing Figure 19 9 Interrupt Recovery Timing MODULE IDB R W INTERRUPT DUMMY SP SP 1 SP 2 SP 3 SP 4 VECT H VECT L START ADDR IAB DUMMY PC 1 7 0 PC 1 15 8 X A CCR V DATA H V DATA L OPCOD...

Page 292: ...S AS MANY INTERRUPTS I BIT SET FROM RESET BREAK I BIT SET IRQ INTERRUPT SWI INSTRUCTION RTI INSTRUCTION FETCH NEXT INSTRUCTION UNSTACK CPU REGISTERS STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR EXECUTE INSTRUCTION YES YES AS EXIST ON CHIP INTERRUPT Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 293: ...ure 19 11 demonstrates what happens when two interrupts are pending If an interrupt is pending upon exit from the original interrupt service routine the pending interrupt is serviced before the LDA instruction is executed Figure 19 11 Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions However in the case of the INT1 RTI prefetch this is a redundan...

Page 294: ...le interrupt sources Table 19 3 summarizes the interrupt sources and the interrupt status register flags that they set The interrupt status registers can be useful for debugging Table 19 3 Interrupt Sources Priority Interrupt Source Interrupt Status Register Flag Highest Reset SWI instruction IRQ pin IF1 PLL IF2 TIM1 channel 0 IF3 TIM1 channel 1 IF4 TIM1 overflow IF5 TIM2 channel 0 IF6 TIM2 channe...

Page 295: ...gs 14 7 These flags indicate the presence of interrupt requests from the sources shown in Table 19 3 1 Interrupt request present 0 No interrupt request present Address FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 R Reserved Figure 19 12 Interrupt Status Register 1 INT1 Address FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read IF14 IF13 IF12 IF11 IF10 IF...

Page 296: ... Break Interrupts The break module can stop normal program flow at a software programmable break point by asserting its break interrupt output See Section 22 Timer Interface Module TIM The SIM puts the CPU into the break state by forcing it to the SWI vector location Refer to the break interrupt subsection of each module to see how each module is affected by the break state Address FE06 Bit 7 6 5 ...

Page 297: ...ccomplished prior to entering break mode Upon leaving break mode execution of the second step will clear the flag as normal 19 7 Low Power Modes Executing the WAIT or STOP instruction puts the MCU in a low power consumption mode for standby situations The SIM holds the CPU in a non clocked state The operation of each of these modes is described in the following subsections Both STOP and WAIT clear...

Page 298: ... Entry Timing Figure 19 16 and Figure 19 17 show the timing for WAIT recovery Figure 19 16 Wait Recovery from Interrupt or Break Figure 19 17 Wait Recovery from Internal Reset WAIT ADDR 1 SAME SAME IAB IDB PREVIOUS DATA NEXT OPCODE SAME WAIT ADDR SAME R W Note Previous data can be operand data or the WAIT opcode depending on the last instruction 6E0C 6E0B 00FF 00FE 00FD 00FC A6 A6 01 0B 6E A6 IAB ...

Page 299: ...for applications using canned oscillators that do not require long startup times from stop mode NOTE External crystal applications should use the full stop recovery time by clearing the SSREC bit A break interrupt during stop mode sets the SIM break stop wait bit SBSW in the SIM break status register SBSR The SIM counter is held in reset from the execution of the STOP instruction until the beginni...

Page 300: ... contains a flag to indicate that a break caused an exit from stop mode or wait mode CGMXCLK INT BREAK IAB STOP 2 STOP 2 SP SP 1 SP 2 SP 3 STOP 1 STOP RECOVERY PERIOD Table 19 4 SIM Registers Address Register Access Mode FE00 SBSR User FE01 SRSR User FE03 SBFCR User Address FE00 Bit 7 6 5 4 3 2 1 Bit 0 Read R R R R R R SBSW R Write Note Reset 0 R Reserved Note Writing a logic 0 clears SBSW Figure ...

Page 301: ...ress on the stack by subtracting one from it The following code is an example of this Writing 0 to the SBSW bit clears it This code works if the H register has been pushed onto the stack in the break service routine software This code should be executed at the end of the break service routine software HIBYTE EQU 5 LOBYTE EQU 6 If not SBSW do RTI BRCLR SBSW SBSR RETURN See if wait mode or stop mode...

Page 302: ...ernal Reset Bit 1 Last reset caused by external reset pin RST 0 POR or read of SRSR COP Computer Operating Properly Reset Bit 1 Last reset caused by COP counter 0 POR or read of SRSR ILOP Illegal Opcode Reset Bit 1 Last reset caused by an illegal opcode 0 POR or read of SRSR ILAD Illegal Address Reset Bit opcode fetches only 1 Last reset caused by an opcode fetch from an illegal address 0 POR or r...

Page 303: ...trol register contains a bit that enables software to clear status bits while the MCU is in a break state BCFE Break Clear Flag Enable Bit This read write bit enables software to clear status bits by accessing status registers while the MCU is in a break state To clear status bits during the break state the BCFE bit must be set 1 Status bits clearable during break 0 Status bits not clearable durin...

Page 304: ... Module SIM Technical Data MC68HC908GP32 MC68HC08GP32 Rev 6 302 System Integration Module SIM MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 305: ...Polarity Controls 309 20 6 2 Transmission Format When CPHA 0 310 20 6 3 Transmission Format When CPHA 1 312 20 6 4 Transmission Initiation Latency 313 20 7 Queuing Transmission Data 315 20 8 Error Conditions 316 20 8 1 Overflow Error 316 20 8 2 Mode Fault Error 318 20 9 Interrupts 320 20 10 Resetting the SPI 322 20 11 Low Power Modes 323 20 11 1 Wait Mode 323 20 11 2 Stop Mode 323 20 12 SPI During...

Page 306: ...PI module include Full duplex operation Master and slave modes Double buffered operation with separate transmit and receive registers Four master mode frequencies maximum bus frequency 2 Maximum slave mode frequency bus frequency Serial clock with programmable polarity and phase Two separately enabled interrupts SPRF SPI receiver full SPTE SPI transmitter empty Mode fault error flag with CPU inter...

Page 307: ...marizes the SPI I O registers and Figure 20 2 shows the structure of the SPI module Table 20 1 Pin Name Conventions SPI Generic Pin Names MISO MOSI SS SPSCK CGND Full SPI Pin Names SPI PTD1 MISO PTD2 MOSI PTD0 SS PTD3 SPSCK VSS Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 0010 SPI Control Register SPCR Read SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIE Write Reset 0 0 1 0 1 0 0 0 0011 SPI Status and C...

Page 308: ...hen an internal pullup device may be enabled for that port bit See 16 5 3 Port C Input Pullup Enable Register TRANSMITTER CPU INTERRUPT REQUEST RESERVED RECEIVER ERROR CPU INTERRUPT REQUEST 7 6 5 4 3 2 1 0 SPR1 SPMSTR TRANSMIT DATA REGISTER SHIFT REGISTER SPR0 CGMOUT 2 CLOCK SELECT 2 CLOCK DIVIDER 8 32 128 CLOCK LOGIC CPHA CPOL SPI SPRIE DMAS SPE SPWOM SPRF SPTE OVRF RESERVED M S PIN CONTROL LOGIC...

Page 309: ...PI See 20 14 1 SPI Control Register Only a master SPI module can initiate transmissions Software begins the transmission from a master SPI module by writing to the transmit data register If the shift register is empty the byte immediately transfers to the shift register setting the SPI transmitter empty bit SPTE The byte begins shifting out on the MOSI pin under the control of the serial clock See...

Page 310: ...CK pin is the input for the serial clock from the master MCU Before a data transmission occurs the SS pin of the slave SPI must be at logic 0 SS must remain low until the transmission is complete See 20 8 2 Mode Fault Error In a slave SPI module data enters the shift register under the control of the serial clock from the master SPI module After a byte enters the shift register of a slave SPI it t...

Page 311: ... 6 Transmission Formats NOTE SPSCK must be in the proper idle state before the slave is enabled to prevent SPSCK from appearing as a clock edge 20 6 Transmission Formats During an SPI transmission data is simultaneously transmitted shifted out serially and received shifted in serially A serial clock synchronizes shifting and sampling on the two serial data lines A slave select line allows selectio...

Page 312: ...ter or slave timing diagram since the serial clock SPSCK master in slave out MISO and master out slave in MOSI pins are directly connected between the master and the slave The MISO signal is the output from the slave and the MOSI signal is the output from the master The SS line is the slave select input to the slave The slave SPI drives its MISO output only when its slave select input SS is at log...

Page 313: ...rom the transmit data register Therefore the SPI data register of the slave must be loaded with transmit data before the falling edge of SS Any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB MSB 1 2 3 4 5 6 7 8 SPSCK C...

Page 314: ...ut only when its slave select input SS is at logic 0 so that only the selected slave drives to the master The SS pin of the master is not shown but is assumed to be inactive The SS pin of the master must be high or must be reconfigured as general purpose I O not affecting the SPI See 20 8 2 Mode Fault Error When CPHA 1 the master begins driving its MOSI pin on the first SPSCK edge Therefore the sl...

Page 315: ... the initial state of the SPSCK signal When CPHA 0 the SPSCK signal remains inactive for the first half of the first SPSCK cycle When CPHA 1 the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its active level The SPI clock rate selected by SPR1 SPR0 affects the delay from the write to SPDR and the start of the SPI transmission See Figure 20 7 The internal SPI clock in...

Page 316: ...ST LATEST SPSCK INTERNAL CLOCK 2 EARLIEST LATEST 2 POSSIBLE START POINTS SPSCK INTERNAL CLOCK 8 8 POSSIBLE START POINTS EARLIEST LATEST SPSCK INTERNAL CLOCK 32 32 POSSIBLE START POINTS EARLIEST LATEST SPSCK INTERNAL CLOCK 128 128 POSSIBLE START POINTS WRITE TO SPDR WRITE TO SPDR WRITE TO SPDR BUS CLOCK BIT 5 3 BUS CLOCK BUS CLOCK BUS CLOCK INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN Freesca...

Page 317: ...ue contained in the shift register is the next data word to be transmitted BIT 3 MOSI SPSCK SPTE WRITE TO SPDR 1 CPU WRITES BYTE 2 TO SPDR QUEUEING BYTE 2 CPU WRITES BYTE 1 TO SPDR CLEARING SPTE BIT BYTE 1 TRANSFERS FROM TRANSMIT DATA 3 1 2 2 3 5 REGISTER TO SHIFT REGISTER SETTING SPTE BIT SPRF READ SPSCR MSB BIT 6 BIT 5 BIT 4 BIT 2 BIT 1 LSBMSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSBMSB BIT 6 BYT...

Page 318: ...rror MODF The MODF bit indicates that the voltage on the slave select pin SS is inconsistent with the mode of the SPI MODF is in the SPI status and control register 20 8 1 Overflow Error The overflow flag OVRF becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs The bit 1 capture strobe occurs i...

Page 319: ...e no more SPRF interrupts can be generated until this OVRF is serviced it is not obvious that bytes are being lost as more transmissions are completed To prevent this either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit Figure 20 10 illust...

Page 320: ...time For the MODF flag to be set the mode fault error enable bit MODFEN must be set Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared READ READ OVRF SPRF BYTE 1 BYTE 2 BYTE 3 BYTE 4 1 BYTE 1 SETS SPRF BIT CPU READS SPSCR WITH SPRF BIT SET CPU READS BYTE 1 IN SPDR CPU READS SPSCR AGAIN BYTE 2 SETS SPRF BIT CPU READS SPSCR WITH SPRF...

Page 321: ... prevent bus contention with another master SPI after a mode fault error clear all SPI bits of the data direction register of the shared I O port before enabling the SPI When configured as a slave SPMSTR 0 the MODF flag is set if SS goes high during a transmission When CPHA 0 a transmission begins when SS goes low and ends once the incoming SPSCK goes back to its idle level following the shift of ...

Page 322: ...oltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state Also the slave SPI ignores all incoming SPSCK clocks even if it was already in the middle of a transmission To clear the MODF flag read the SPSCR with the MODF bit set and then write to the SPCR register This entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared 20 9 Inter...

Page 323: ...it SPRIE enables the SPRF bit to generate receiver CPU interrupt requests regardless of the state of the SPE bit See Figure 20 11 The error interrupt enable bit ERRIE enables both the MODF and OVRF bits to generate a receiver error CPU interrupt request The mode fault enable bit MODFEN can prevent the MODF flag from being set so that only the OVRF bit is enabled by the ERRIE bit to generate receiv...

Page 324: ...quest 20 10 Resetting the SPI Any system reset completely resets the SPI Partial resets occur whenever the SPI enable bit SPE is low Whenever SPE is low the following occurs The SPTE flag is set Any transmission currently in progress is aborted The shift register is cleared The SPI state counter is cleared making it ready for a new complete transmission All the SPI port logic is defaulted back to ...

Page 325: ...e SPI module registers are not accessible by the CPU Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode If SPI module functions are not required during wait mode reduce power consumption by disabling the SPI module before executing the WAIT instruction To exit wait mode when an overflow condition occurs enable the OVRF bit to generate CPU interrupt requests by...

Page 326: ...ead and write I O registers during the break state without affecting status bits Some status bits have a 2 step read write clearing procedure If software does the first step on such a bit before the break the bit cannot change during the break state as long as BCFE is at logic 0 After the break doing the second step clears the status bit Since the SPTE bit cannot be cleared during a break with the...

Page 327: ...and transmits data from its MOSI pin Slave output data on the MISO pin is enabled only when the SPI is configured as a slave The SPI is configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0 To support a multiple slave system a logic 1 on the SS pin puts the MISO pin in a high impedance state When enabled the SPI controls data direction of the MISO pin regardless of the ...

Page 328: ...f a transmission See 20 6 Transmission Formats Since it is used to indicate the start of a transmission the SS must be toggled high and low between each byte transmitted for the CPHA 0 format However it can remain low between transmissions for the CPHA 1 format See Figure 20 12 Figure 20 12 CPHA SS Timing When an SPI is configured as a slave the SS pin is always configured as an input It cannot be...

Page 329: ...in to the SPI regardless of the state of the data direction register of the shared I O port The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the port data register See Table 20 3 20 13 5 CGND Clock Ground CGND is the ground return for the serial clock pin SPSCK and the ground for the port output buffers It is internally connected to VSS as ...

Page 330: ...gures the SPSCK MOSI and MISO pins as open drain outputs Enables the SPI module SPRIE SPI Receiver Interrupt Enable Bit This read write bit enables CPU interrupt requests generated by the SPRF bit The SPRF bit is set when a byte transfers from the shift register to the receive data register Reset clears the SPRIE bit 1 SPRF CPU interrupt requests enabled 0 SPRF CPU interrupt requests disabled Addr...

Page 331: ...alues Reset clears the CPOL bit CPHA Clock Phase Bit This read write bit controls the timing relationship between the serial clock and SPI data See Figure 20 4 and Figure 20 6 To transmit data between SPI modules the SPI modules must have identical CPHA values When CPHA 0 the SS pin of the slave SPI module must be set to logic 1 between bytes See Figure 20 12 Reset sets the CPHA bit SPWOM SPI Wire...

Page 332: ... control register contains flags to signal these conditions Receive data register full Failure to clear SPRF bit before next byte is received overflow error Inconsistent logic level on SS pin mode fault error Transmit data register empty The SPI status and control register also contains bits that perform these functions Enable error interrupts Enable mode fault error detection Select master SPI ba...

Page 333: ...t requests OVRF Overflow Bit This clearable read only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register In an overflow condition the byte already in the receive data register is unaffected and the byte that shifted in last is lost Clear the OVRF bit by reading the SPI status and control register with OVRF set and then re...

Page 334: ... the MODFEN does not clear the MODF flag If the SPI is enabled as a master and the MODFEN bit is low then the SS pin is available as a general purpose I O If the MODFEN bit is set then this pin is not available as a general purpose I O When the SPI is enabled as a slave the SS pin is not available as a general purpose I O regardless of the value of MODFEN See 20 13 4 SS Slave Select If the MODFEN ...

Page 335: ... reads data from the receive data register The transmit data and receive data registers are separate registers that can contain different values See Figure 20 2 R7 R0 T7 T0 Receive Transmit Data Bits NOTE Do not use read modify write instructions on the SPI data register since the register read is not the same as the register written Table 20 4 SPI Master Baud Rate Selection SPR1 and SPR0 Baud Rat...

Page 336: ... Module SPI Technical Data MC68HC908GP32 MC68HC08GP32 Rev 6 334 Serial Peripheral Interface Module SPI MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 337: ...imebase module TBM The TBM will generate periodic interrupts at user selectable rates using a counter clocked by the external crystal clock This TBM version uses 15 divider stages eight of which are user selectable 21 3 Features Features of the TBM module include Software programmable 1 Hz 4 Hz 16 Hz 256 Hz 512 Hz 1024 Hz 2048 Hz and 4096 Hz periodic interrupt using external 32 768 kHz crystal Use...

Page 338: ...by TBR2 TBR0 the TBIF bit gets set If the TBIE bit is set an interrupt request is sent to the CPU The TBIF flag is cleared by writing a 1 to the TACK bit The first time the TBIF flag is set after enabling the timebase module the interrupt is generated at approximately half of the overflow period Subsequent events occur at the exact period Figure 21 1 Timebase Block Diagram 2 SEL 0 0 0 0 0 1 0 1 0 ...

Page 339: ... Rate Selection These read write bits are used to select the rate of timebase interrupts as shown in Table 21 1 Address 001C Bit 7 6 5 4 3 2 1 Bit 0 Read TBIF TBR2 TBR1 TBR0 0 TBIE TBON R Write TACK Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 21 2 Timebase Control Register TBCR Table 21 1 Timebase Rate Selection for OSC1 32 768 kHz TBR2 TBR1 TBR0 Divider Timebase Interrupt Rate Hz ms 0 0...

Page 340: ...sabled TBON Timebase Enabled This read write bit enables the timebase Timebase may be turned off to reduce power consumption when its function is not necessary The counter can be initialized by clearing and then setting this bit Reset clears the TBON bit 1 Timebase enabled 0 Timebase disabled and the counter initialized to 0s 21 6 Interrupts The timebase module can interrupt the CPU on a regular b...

Page 341: ...p Mode The timebase module may remain active after execution of the STOP instruction if the oscillator has been enabled to operate during stop mode through the OSCSTOPEN bit in the CONFIG register The timebase module can be used in this mode to generate a periodic wakeup from stop mode If the oscillator has not been enabled to operate in stop mode the timebase module will not be active during STOP...

Page 342: ... Module TBM Technical Data MC68HC908GP32 MC68HC08GP32 Rev 6 340 Timebase Module TBM MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 343: ...5 4 Pulse Width Modulation PWM 349 22 5 4 1 Unbuffered PWM Signal Generation 350 22 5 4 2 Buffered PWM Signal Generation 351 22 5 4 3 PWM Initialization 352 22 6 Interrupts 353 22 7 Low Power Modes 353 22 7 1 Wait Mode 354 22 7 2 Stop Mode 354 22 8 TIM During Break Interrupts 354 22 9 I O Signals 355 22 10 I O Registers 355 22 10 1 TIM Status and Control Register 356 22 10 2 TIM Counter Registers ...

Page 344: ... modules which are denoted as TIM1 and TIM2 22 3 Features Features of the TIM include Two input capture output compare channels Rising edge falling edge or any edge input capture trigger Set clear or toggle output compare action Buffered and unbuffered pulse width modulation PWM signal generation Programmable TIM clock input with 7 frequency internal bus clock prescaler selection Free running or m...

Page 345: ...scription Figure 22 1 shows the structure of the TIM The central component of the TIM is the 16 bit TIM counter that can operate as a free running counter or a modulo up counter The TIM counter provides the timing reference for the input capture and output compare functions The TIM counter modulo registers TMODH TMODL control the modulo value of the TIM counter Software can read the TIM counter va...

Page 346: ...SC and T2SC MS1A CH0F PRESCALER PRESCALER SELECT INTERNAL 16 BIT COMPARATOR PS2 PS1 PS0 16 BIT COMPARATOR 16 BIT LATCH TCH0H TCH0L TOF TOIE 16 BIT COMPARATOR 16 BIT LATCH TCH1H TCH1L CHANNEL 0 CHANNEL 1 TMODH TMODL TRST TSTOP TOV0 CH0IE TOV1 CH1IE CH1MAX CH0MAX 16 BIT COUNTER INTERNAL BUS BUS CLOCK T 1 2 CH0 T 1 2 CH1 INTERRUPT LOGIC PORT LOGIC INTERRUPT LOGIC INTERRUPT LOGIC PORT LOGIC ELS0A ELS0...

Page 347: ... 1 1 1 1 1 1 1 0024 Timer 1 Counter Modulo Register Low T1MODL Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 0025 Timer 1 Channel 0 Status and Control Register T1SC0 Read CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Write 0 Reset 0 0 0 0 0 0 0 0 0026 Timer 1 Channel 0 Register High T1CH0H Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset 0027 Timer 1 Channel 0 Reg...

Page 348: ...ounter Register Low T2CNTL Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 002E Timer 2 Counter Modulo Register High T2MODH Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 002F Timer 2 Counter Modulo Register Low T2MODL Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 1 1 1 1 1 1 1 1 0030 Timer 2 Channel 0 Status and Control Register T2SC0 Read CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0...

Page 349: ...the TIM channel registers TCHxH TCHxL The polarity of the active edge is programmable Input captures can generate TIM CPU interrupt requests 0032 Timer 2 Channel 0 Register Low T2CH0L Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset 0033 Timer 2 Channel 1 Status and Control Register T2SC1 Read CH1F CH1IE 0 MS1A ELS1B ELS1A TOV1 CH1MAX Write 0 Reset 0 0 0 0 0 0 0 0 0034 Timer 2 Ch...

Page 350: ... counter reaches the new value prevents any compare during that counter overflow period Also using a TIM overflow interrupt routine to write a new smaller output compare value may cause the compare to be missed The TIM may pass the new value before it is written Use the following methods to synchronize unbuffered changes in the output compare value on channel x When changing to a smaller value ena...

Page 351: ... general purpose I O pin NOTE In buffered output compare operation do not write new output compare values to the currently active channel registers User software should track the currently active channel to prevent writing a new value to the active channel Writing to the active channel registers is the same as generating unbuffered output compares 22 5 4 Pulse Width Modulation PWM By using the tog...

Page 352: ...Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 22 5 4 Pulse Width Modulation PWM The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers An unsynchronized write to the TIM channel registers to change a pulse width value could cause ...

Page 353: ...ion and removes the ability of the channel to self correct in the event of software error or noise Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new much larger value 22 5 4 2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin The TIM channel registers o...

Page 354: ...write the value for the required pulse width 4 In TIM channel x status and control register TSCx a Write 0 1 for unbuffered output compare or PWM signals or 1 0 for buffered output compare or PWM signals to the mode select bits MSxB MSxA See Table 22 3 b Write 1 to the toggle on overflow bit TOVx c Write 1 0 to clear output on compare or 1 1 to set output on compare to the edge level select bits E...

Page 355: ... Channel Status and Control Registers 22 6 Interrupts The following TIM sources can generate interrupt requests TIM overflow flag TOF The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers The TIM overflow interrupt enable bit TOIE enables TIM overflow CPU interrupt requests TOF and TOIE are in the TIM status and control register TIM channel...

Page 356: ...ntrols whether status bits in other modules can be cleared during the break state The BCFE bit in the SIM break flag control register SBFCR enables software to clear status bits during the break state See 19 8 3 SIM Break Flag Control Register To allow software to clear status bits during a break interrupt write a logic 1 to the BCFE bit If a status bit is cleared during the break state it remains...

Page 357: ...ed as buffered output compare or buffered PWM pins 22 10 I O Registers NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number For example TSC may generically refer to both T1SC AND T2SC These I O registers control and monitor operation of the TIM TIM status and control register TSC TIM counter registers TCNTH TCNTL TIM counter modulo registers T...

Page 358: ...learing sequence is complete then writing logic 0 to TOF has no effect Therefore a TOF interrupt request cannot be lost due to inadvertent clearing of TOF Reset clears the TOF bit Writing a logic 1 to TOF has no effect 1 TIM counter has reached modulo value 0 TIM counter has not reached modulo value TOIE TIM Overflow Interrupt Enable Bit This read write bit enables TIM overflow interrupts when the...

Page 359: ...00 TRST is cleared automatically after the TIM counter is reset and always reads as logic 0 Reset clears the TRST bit 1 Prescaler and TIM counter cleared 0 No effect NOTE Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of 0000 PS 2 0 Prescaler Select Bits These read write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 22 2 sh...

Page 360: ... clears the TIM counter registers NOTE If you read TCNTH during a break interrupt be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt Otherwise TCNTL retains the value latched during the break Address T1CNTH 0021 and T2CNTH 002C Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 22 5 TIM Counter Registers High TCNTH ...

Page 361: ...F bit and overflow interrupts until the low byte TMODL is written Reset sets the TIM counter modulo registers NOTE Reset the TIM counter before writing to the TIM counter modulo registers Address T1MODH 0023 and T2MODH 002E Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset 1 1 1 1 1 1 1 1 Figure 22 7 TIM Counter Modulo Register High TMODH Address T1MODL 0024 and T2MODL 002F Bi...

Page 362: ...input capture trigger Selects output toggling on TIM overflow Selects 0 and 100 PWM duty cycle Selects buffered or unbuffered output compare PWM operation Address T1SC0 0025 and T2SC0 0030 Bit 7 6 5 4 3 2 1 Bit 0 Read CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Write 0 Reset 0 0 0 0 0 0 0 0 Figure 22 9 TIM Channel 0 Status and Control Register TSC0 Address T1SC1 0028 and T2SC1 0033 Bit 7 6 5 4 3 ...

Page 363: ...apture or output compare on channel x 0 No input capture or output compare on channel x CHxIE Channel x Interrupt Enable Bit This read write bit enables TIM CPU interrupt service requests on channel x Reset clears the CHxIE bit 1 Channel x CPU interrupt requests enabled 0 Channel x CPU interrupt requests disabled MSxB Mode Select Bit B This read write bit selects buffered output compare PWM operat...

Page 364: ...t compare occurs When ELSxB and ELSxA are both clear channel x is not connected to port D and pin PTDx TCHx is available as a general purpose I O pin Table 22 3 shows how ELSxB and ELSxA work Reset clears the ELSxB and ELSxA bits Table 22 3 Mode Edge and Level Selection MSxB MSxA ELSxB ELSxA Mode Configuration X0 00 Output preset Pin under port control initial output level high X1 00 Pin under por...

Page 365: ...nnel x output compare if both occur at the same time CHxMAX Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1 setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100 As Figure 22 11 shows the CHxMAX bit takes effect in the cycle after it is set or cleared The output stays at the 100 duty cycle level until the cycle after CHxMAX is cleared Figure 22...

Page 366: ...ite Reset Indeterminate after reset Figure 22 12 TIM Channel 0 Register High TCH0H Address T1CH0L 0027 and T2CH0L 0032 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset Indeterminate after reset Figure 22 13 TIM Channel 0 Register Low TCH0L Address T1CH1H 0029 and T2CH1H 0034 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Reset Indeterminate after reset Figure 22 1...

Page 367: ...Control Timing 372 23 9 3 0 V Control Timing 373 23 10 Output High Voltage Characteristics 374 23 11 Output Low Voltage Characteristics 377 23 12 Typical Supply Currents 380 23 13 ADC Characteristics 382 23 14 5 0 V SPI Characteristics 383 23 15 3 0 V SPI Characteristics 384 23 16 Timer Interface Module Characteristics 387 23 17 Clock Generation Module Characteristics 387 23 17 1 CGM Component Spe...

Page 368: ...utions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit For proper operation it is recommended that VIn and VOut be constrained to the range VSS VIn or VOut VDD Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level for example either VSS or VDD Characteristic 1 1 Voltages referenced to...

Page 369: ...nce 40 pin PDIP 42 pin SDIP 44 pin QFP θJA 60 60 95 C W I O pin power dissipation PI O User determined W Power dissipation 1 1 Power dissipation is a function of temperature PD PD IDD VDD PI O K TJ 273 C W Constant 2 2 K is a constant unique to the device K can be determined for a known TA and measured PD With this value of K PD and TJ can be determined for any value of TA K PD TA 273 C PD 2 θJA W...

Page 370: ... Maximum combined IOL for port PTD4 PTD7 port A port B Maximum total IOL for all port pins VOL VOL VOL IOL1 IOL2 IOLT 0 4 1 5 1 0 50 50 100 V V V mA mA mA Input high voltage All ports IRQ RST OSC1 VIH 0 7 VDD VDD V Input low voltage All ports IRQ RST OSC1 VIL VSS 0 2 VDD V VDD supply current Run 3 Wait 4 Stop 5 25 C 25 C with TBM enabled 6 25 C with LVI and TBM enabled 6 40 C to 85 C with TBM enab...

Page 371: ...y affects run IDD Measured with all modules enabled 4 Wait IDD measured using external square wave clock source fOSC 32 8 MHz All inputs 0 2 V from rail No dc loads Less than 100 pF on all outputs CL 20 pF on OSC2 All ports configured as inputs OSC2 capacitance linearly affects wait IDD Measured with PLL and LVI enabled 5 Stop IDD is measured with OSC1 VSS 6 Stop IDD with TBM enabled is measured u...

Page 372: ...Maximum combined IOL for port PTD4 PTD7 port A port B Maximum total IOL for all port pins VOL VOL VOL IOL1 IOL2 IOLT 0 3 1 0 0 8 30 30 60 V V V mA mA mA Input high voltage All ports IRQ RST OSC1 VIH 0 7 VDD VDD V Input low voltage All ports IRQ RST OSC1 VIL VSS 0 3 VDD V VDD supply current Run 3 Wait 4 Stop 5 25 C 25 C with TBM enabled 6 25 C with LVI and TBM enabled 6 40 C to 85 C with TBM enable...

Page 373: ...ts OSC2 capacitance linearly affects run IDD Measured with all modules enabled 4 Wait IDD measured using external square wave clock source fOSC 16 4 MHz All inputs 0 2 V from rail No dc loads Less than 100 pF on all outputs CL 20 pF on OSC2 All ports configured as inputs OSC2 capacitance linearly affects wait IDD Measured with PLL and LVI enabled 5 Stop IDD is measured with OSC1 VSS 6 Stop IDD wit...

Page 374: ...ck period 1 fOP tCYC 122 ns RST input pulse width low 5 5 Minimum pulse width reset is guaranteed to be recognized It is possible for a smaller pulse width to cause a reset tIRL 50 ns IRQ interrupt pulse width low 6 edge triggered 6 Minimum pulse width is for guaranteed interrupt It is possible for a smaller pulse width to be recognized tILIH 50 ns IRQ interrupt pulse period tILIL Note 8 tCYC 16 b...

Page 375: ...ernal clock period 1 fOP tCYC 244 ns RST input pulse width low 5 5 Minimum pulse width reset is guaranteed to be recognized It is possible for a smaller pulse width to cause a reset tIRL 125 ns IRQ interrupt pulse width low 6 edge triggered 6 Minimum pulse width is for guaranteed interrupt It is possible for a smaller pulse width to be recognized tILIH 125 ns IRQ interrupt pulse period tILIL Note ...

Page 376: ...ure 23 2 Typical High Side Driver Characteristics Port PTA7 PTA0 VDD 2 7 Vdc 35 30 25 20 15 10 5 0 40 0 25 I OH mA 40 VOH V 3 3 4 3 6 3 8 4 0 4 2 3 2 85 VOH VDD 0 8 V IOH 2 0 mA VOH VDD 1 5 V IOH 10 0 mA 25 20 15 10 5 0 40 0 25 I OH mA 1 3 1 7 1 9 2 1 2 3 2 5 1 5 85 VOH V VOH VDD 0 3 V IOH 0 6 mA VOH VDD 1 0 V IOH 4 0 mA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On...

Page 377: ...4 PTC0 VDD 4 5 Vdc Figure 23 4 Typical High Side Driver Characteristics Port PTC4 PTC0 VDD 2 7 Vdc 35 30 25 20 15 10 5 0 40 0 25 I OH mA 40 VOH V 3 3 4 3 6 3 8 4 0 4 2 3 2 85 VOH VDD 0 8 V IOH 10 0 mA 25 20 15 10 5 0 40 0 25 I OH mA 1 3 1 7 1 9 2 1 2 3 2 5 1 5 85 VOH V VOH VDD 0 5 V IOH 4 0 mA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www free...

Page 378: ...Driver Characteristics Ports PTB7 PTB0 PTC6 PTC5 PTD7 PTD0 and PTE1 PTE0 VDD 2 7 Vdc 70 60 50 40 30 20 10 0 40 0 25 I OH mA 90 VOH V 3 3 4 3 6 3 8 4 0 4 2 3 2 85 80 4 6 4 4 VOH VDD 0 8 V IOH 2 0 mA VOH VDD 1 5 V IOH 10 0 mA 25 20 15 10 5 0 40 0 25 I OH mA 1 3 1 7 1 9 2 1 2 3 2 5 1 5 85 VOH V VOH VDD 0 3 V IOH 0 6 mA VOH VDD 1 0 V IOH 4 0 mA Freescale Semiconductor I Freescale Semiconductor Inc For...

Page 379: ...TA0 VDD 5 5 Vdc Figure 23 8 Typical Low Side Driver Characteristics Port PTA7 PTA0 VDD 2 7 Vdc 5 10 15 20 25 30 35 40 0 25 I OL mA 0 VOL V 0 0 4 0 6 0 8 1 0 1 2 0 2 85 1 4 1 6 VOL 0 4 V IOL 1 6 mA VOL 1 5 V IOL 10 0 mA 2 4 6 8 10 12 14 40 0 25 I OL mA 0 VOL V 0 4 0 6 0 8 1 0 1 2 0 2 85 1 4 1 6 VOL 0 3 V IOL 0 5 mA VOL 1 0 V IOL 6 0 mA Freescale Semiconductor I Freescale Semiconductor Inc For More ...

Page 380: ...Vdc Figure 23 10 Typical Low Side Driver Characteristics Port PTC4 PTC0 VDD 2 7 Vdc 10 20 30 40 50 60 I OL mA 0 VOL V 0 4 0 6 0 8 1 0 1 2 1 4 1 6 40 0 25 85 VOL 1 0 V IOL 15 mA 5 10 15 20 25 30 40 0 25 I OL mA 0 VOL V 0 4 0 6 0 8 1 0 1 2 0 2 85 1 4 1 6 VOL 0 8 V IOL 10 mA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 381: ... 23 12 Typical Low Side Driver Characteristics Ports PTB7 PTB0 PTC6 PTC5 PTD7 PTD0 and PTE1 PTE0 VDD 2 7 Vdc 5 10 15 20 25 30 35 40 0 25 I OL mA 0 VOL V 0 0 4 0 6 0 8 1 0 1 2 0 2 85 1 4 1 6 VOL 0 4 V IOL 1 6 mA VOL 1 5 V IOL 10 0 mA 2 4 6 8 10 12 14 40 0 25 I OL mA 0 VOL V 0 2 0 4 0 6 0 8 1 0 0 85 1 2 1 6 1 4 VOL 0 3 V IOL 0 5 mA VOL 1 0 V IOL 6 0 mA Freescale Semiconductor I Freescale Semiconduct...

Page 382: ...ll Modules Turned On 40 C to 85 C Figure 23 14 Typical Wait Mode IDD with all Modules Disabled 40 C to 85 C 0 2 4 6 8 10 12 0 1 2 3 4 5 6 7 8 9 5 5 V 3 6 V fBUS MHz I DD mA 14 16 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 0 1 2 3 4 5 6 7 8 5 5 V 3 6 V I DD mA fBUS MHz Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 383: ...Electrical Specifications 381 Figure 23 15 Typical Stop Mode IDD with all Modules Disabled 40 C to 85 C 1 1 05 1 10 1 15 1 20 1 25 1 30 0 1 2 3 4 5 6 7 8 9 5 5 V 3 6 V fBUS MHz I DD µ A 1 35 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 384: ...ime tADPU 16 tAIC cycles Conversion time tADC 16 17 tAIC cycles Sample time 2 tADS 5 tAIC cycles Zero input reading 3 ZADI 00 01 Hex VIN VREFL Full scale reading 3 FADI FE FF Hex VIN VREFH Input capacitance CADI 20 8 pF Not tested Input leakage 4 Port B 1 µA Notes 1 VDD 5 0 Vdc 10 VSS 0 Vdc VDDAD 5 0 Vdc 10 VSSAD 0 Vdc VREFH 5 0 Vdc 10 VREFL 0 2 Source impedances greater than 10 kΩ adversely affec...

Page 385: ... Clock SPSCK high time Master Slave tSCKH M tSCKH S tCYC 25 1 2 tCYC 25 64 tCYC ns ns 5 Clock SPSCK low time Master Slave tSCKL M tSCKL S tCYC 25 1 2 tCYC 25 64 tCYC ns ns 6 Data setup time inputs Master Slave tSU M tSU S 30 30 ns ns 7 Data hold time inputs Master Slave tH M tH S 30 30 ns ns 8 Access time slave 3 CPHA 0 CPHA 1 3 Time to data active from high impedance state tA CP0 tA CP1 0 0 40 40...

Page 386: ...high time Master Slave tSCKH M tSCKH S tCYC 35 1 2 tCYC 35 64 tCYC ns ns 5 Clock SPSCK low time Master Slave tSCKL M tSCKL S tCYC 35 1 2 tCYC 35 64 tCYC ns ns 6 Data setup time inputs Master Slave tSU M tSU S 40 40 ns ns 7 Data hold time inputs Master Slave tH M tH S 40 40 ns ns 8 Access time slave 3 CPHA 0 CPHA 1 3 Time to data active from high impedance state tA CP0 tA CP1 0 0 50 50 ns ns 9 Disa...

Page 387: ...PUT NOTE 4 5 5 1 4 BITS 6 1 LSB IN MASTER MSB OUT BITS 6 1 MASTER LSB OUT 11 10 11 7 6 NOTE Note This last clock edge is generated internally but is not seen at the SPSCK pin SS PIN OF MASTER HELD HIGH MSB IN SS INPUT SPSCK OUTPUT SPSCK OUTPUT MISO INPUT MOSI OUTPUT NOTE 4 5 5 1 4 BITS 6 1 LSB IN MASTER MSB OUT BITS 6 1 MASTER LSB OUT 10 11 10 7 6 a SPI Master Timing CPHA 0 b SPI Master Timing CPH...

Page 388: ...6 1 8 6 10 5 11 NOTE SLAVE LSB OUT 9 3 LSB IN 2 7 BITS 6 1 MSB OUT Note Not defined but normally LSB of character previously transmitted SLAVE SS INPUT SPSCK INPUT SPSCK INPUT MISO OUTPUT MOSI INPUT 4 5 5 1 4 MSB IN BITS 6 1 8 6 10 NOTE SLAVE LSB OUT 9 3 LSB IN 2 7 BITS 6 1 MSB OUT 10 a SPI Slave Timing CPHA 0 b SPI Slave Timing CPHA 1 11 11 CPOL 0 CPOL 1 CPOL 0 CPOL 1 Freescale Semiconductor I Fr...

Page 389: ...pulse width tTIH tTIL 1 tCYC Characteristic Symbol Min Typ Max Unit External clock 1 1 When using crystals between 30kHz and 100kHz use fundamental mode crystals only fXCLK 30k 32 768k 1 5M Hz Crystal load capacitance 2 2 Consult crystal manufacturer s data CL pF Crystal fixed capacitance 2 C1 2 CL 20 pF Crystal tuning capacitance 2 C2 2 CL 50 pF Feedback bias resistor RB 10 MΩ Series resistor RS ...

Page 390: ...nge multiplier L 1 255 VCO power of two range multiplier 2E 1 4 VCO multiply factor N 1 4095 VCO prescale multiplier 2P 1 1 8 Reference divider factor R 1 1 15 VCO operating frequency fVCLK 38 4 k 40 0 M Hz Bus operating frequency 1 fBUS 8 2 MHz Bus frequency medium voltage 2 fBUS 4 1 MHz Manual acquisition time tLock 50 ms Automatic lock time tLock 50 ms PLL jitter 3 3 Deviation of average bus fr...

Page 391: ... hold time tpgs 5 µs FLASH program time tPROG 30 40 µs FLASH return to read time trcv 4 4 trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump by clearing HVEN to logic 0 1 µs FLASH cumulative program HV period tHV 5 5 tHV is defined as the cumulative high voltage programming time to the same row before next erase tHV must satisfy this co...

Page 392: ...cifications Technical Data MC68HC908GP32 MC68HC08GP32 Rev 6 390 Electrical Specifications MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 393: ...In Line Package PDIP 392 24 4 42 Pin Shrink Dual in Line Package SDIP 392 24 5 44 Pin Plastic Quad Flat Pack QFP 393 24 2 Introduction This section gives the dimensions for 40 pin plastic dual in line package case 711 03 42 pin shrink dual in line package case 858 01 44 pin plastic quad flat pack case 824A 01 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Produc...

Page 394: ...ING PLANE AND EACH OTHER 2 DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL 3 DIMENSION B DOES NOT INCLUDE MOLD FLASH 1 0 0 A 42 22 1 21 B SEATING PLANE T S A M 0 25 0 010 T S B M 0 25 0 010 T L H M J 42 PL D 42 PL F G N K C NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 2 CONTROLLING DIMENSION INCH 3 DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL 4 DIMENSIONS A AND B DO NOT INCL...

Page 395: ...E D DIMENSION AT MAXIMUM MATERIAL CONDITION DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT L 33 34 23 22 44 1 11 12 DETAIL A D A A S A B M 0 20 0 008 D S C S A B M 0 20 0 008 D S H 0 05 0 002 A B S B S A B M 0 20 0 008 D S C S A B M 0 20 0 008 D S H 0 05 0 002 A B V L B C SEATING PLANE M M E H G C H DATUM PLANE DETAIL C 0 01 0 004 M H DATUM PLANE T R K Q W X DETAIL C DIM MIN MAX MIN MAX ...

Page 396: ...cifications Technical Data MC68HC908GP32 MC68HC08GP32 Rev 6 394 Mechanical Specifications MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 397: ...5 2 Introduction This section contains ordering numbers for the MC68HC908GP32 25 3 MC Order Numbers Table 25 1 MC Order Numbers MC order number Operating temperature range Package MC68HC908GP32CP 40 C to 85 C 40 pin PDIP MC68HC908GP32CB 40 C to 85 C 42 pin SDIP MC68HC908GP32CFB 40 C to 85 C 44 pin QFP Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to ...

Page 398: ...Information Technical Data MC68HC908GP32 MC68HC08GP32 Rev 6 396 Ordering Information MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 399: ... A 5 Mask Option Registers 401 A 6 Reserved Registers 402 A 7 Monitor ROM 402 A 8 Electrical Specifications 403 A 8 1 Functional Operating Range 403 A 8 2 5 0 V DC Electrical Characteristics 403 A 8 3 3 0 V DC Electrical Characteristics 404 A 8 4 Memory Characteristics 405 A 9 ROM MC Order Numbers 406 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to ...

Page 400: ... vectors FFDC FFFF 36 bytes ROM 36 bytes FLASH Registers at 001E and 001F Mask option registers defined by mask read only 001E MOR2 001F MOR1 Configuration registers write once after reset 001E CONFIG2 001F CONFIG1 Registers at FE08 and FF7E Not used locations are reserved FLASH related registers FE08 FLCR FF7E FLBPR Bit 2 at FE01 Not used bit is reserved MODRST monitor mode entry by blank reset v...

Page 401: ... PTB5 AD5 PTB4 AD4 PTB3 AD3 PTB2 AD2 PTB1 AD1 PTB0 AD0 V DDAD V REFH 8 BIT ANALOG TO DIGITAL CONVERTER MODULE PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 PTD7 T2CH1 PTD6 T2CH0 PTD5 T1CH1 PTD4 T1CH0 PTD3 SPSCK PTD2 MOSI PTD1 MISO PTD0 SS PTE1 RxD PTE0 TxD V SSAD V REFL 2 CHANNEL TIMER INTERFACE MODULE 1 32 kHz OSCILLATOR PHASE LOCKED LOOP SERIAL COMMUNICATIONS INTERFACE MODULE DATA BUS SWITCH MODULE POWER O...

Page 402: ...ented 32 192 Bytes 7FFF 8000 ROM 32 256 Bytes FDFF FE00 SIM Break Status Register SBSR FE01 SIM Reset Status Register SRSR FE02 Reserved SUBAR FE03 SIM Break Flag Control Register SBFCR FE09 Interrupt Status Register 1 INT1 FE0A Interrupt Status Register 2 INT2 FE0B Interrupt Status Register 3 INT3 FE07 Reserved FE08 Reserved FE09 Break Address Register High BRKH FE0A Break Address Register Low BR...

Page 403: ... are called configuration registers CONFIG2 and CONFIG1 FE0C LVI Status Register LVISR FE0D Unimplemented 3 Bytes FE0F FE10 Unimplemented 16 Bytes Reserved for Compatibility with Monitor Code for A Family Parts FE1F FE20 Monitor ROM 307 Bytes FF52 FF53 Unimplemented 43 Bytes FF7D FF7E Reserved FF7F Unimplemented 93 Bytes FFDB Note FFF6 FFFD reserved for 8 security bytes FFDC ROM Vectors 36 Bytes F...

Page 404: ... The monitor program monitor ROM FE20 FF52 on the MC68HC08GP32 is for device testing only The monitor mode entry by blank reset vector bit MODRST bit bit 2 at FE01 is not used in the ROM device the reset vector will always contain data in the MC68HC08GP32 Address 001E Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 OSC STOPENB SCIBD SRC Write Reset Mask defined Figure A 3 Mask Option Register 2 MOR2 Addr...

Page 405: ... source fOSC 32 8 MHz All inputs 0 2V from rail No dc loads Less than 100 pF on all outputs CL 20 pF on OSC2 All ports configured as inputs OSC2 capacitance linearly affects run IDD Measured with all modules enabled 4 Wait IDD measured using external square wave clock source fOSC 32 8 MHz All inputs 0 2 V from rail No dc loads Less than 100 pF on all outputs CL 20 pF on OSC2 All ports configured a...

Page 406: ...les enabled 4 Wait IDD measured using external square wave clock source fOSC 16 4 MHz All inputs 0 2 V from rail No dc loads Less than 100 pF on all outputs CL 20 pF on OSC2 All ports configured as inputs OSC2 capacitance linearly affects wait IDD Measured with PLL and LVI enabled 5 Stop IDD is measured with OSC1 VSS 6 Stop IDD with TBM enabled is measured using an external square wave clock sourc...

Page 407: ...5 5 0 1 2 3 4 5 6 7 8 9 I DD mA fBUS MHz 5 5 V 3 3 V 0 0 2 0 4 0 6 0 8 1 0 1 2 1 2 3 4 5 6 7 8 9 fBUS MHz I DD µ A 1 4 1 6 5 5 V 3 3 V Characteristic Symbol Min Max Unit RAM data retention voltage VRDR 1 3 V Notes Since MC68HC08GP32 is a ROM device FLASH memory electrical characteristics do not apply Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to w...

Page 408: ...der Numbers MC order number Operating temperature range Package MC68HC08GP32CB 40 C to 85 C 42 pin SDIP MC68HC08GP32VB 40 C to 105 C MC68HC08GP32MB 1 1 Temperature grade M is available for 5V operating voltage only 40 C to 125 C MC68HC08GP32CFB 40 C to 85 C 44 pin QFP MC68HC08GP32VFB 40 C to 105 C MC68HC08GP32MFB 1 40 C to 125 C Notes Freescale Semiconductor I Freescale Semiconductor Inc For More ...

Page 409: ...Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 410: ...cations and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or ot...

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