10
MC68360 USER’S MANUAL ERRATA
MOTOROLA
6. Error in sentence.
On page 7-40, Section 7.6.4.4.3 The last sentence in the first paragraph. " If DREQX is
negated long enough for the IDMA to win the bus, cycles will continue as long as DREQx is
asserted and no higher priority bus master or interrupt occurs." This sentence should be
replaced with. " If DREQX is asserted long enough for the IDMA to win the bus, cycles will
continue as long as DREQx is asserted and no higher priority bus master requests the bus
or interrupt occurs."
7. Missing paragraph in IDMA.
On page 7-41, section 7.6.4.4.3. The following paragraph should be added after point 6.
7. If the IDMA is being used in auto-buffer or buffer-chaining mode, the DREQ signal
will not be sampled at the S3 sampling time. It will be sampled after the RISC CP
has reconfigured the IDMA with the information contained in the next buffer de-
scriptor. Thus, you should continually assert DREQ until you receive a DACK when
using buffer chaining mode or auto-buffer mode.
Also on page 7-43 the following paragraph should be added after point 3.
4. You may not use cycle steal mode if you are using buffer-chaining or auto-buffer
mode.
8. Error in example
On page 7-55, the third step in the buffer chaining example was printed incorrectly. The
correct step is as follows.
3. FCR1 = $89. Destination function code is 1000; Source function code is 1001.
9. Error in SDMA Bus Arbitration and Bus Transfers
On page 7-57, the first sentence of the last paragraph should read ‘…but the SDMA always
reads words (16 bits).’
10. Error in Programming the SI RAM Entries.
On page 7-72, section 7.8.4.5, the bit order of SSEL1-SSEL4 is not represented correctly.
The correct representation is as follows:
Bit 13 -> SSEL4
Bit 12 -> SSEL3
Bit 11 -> SSEL2
Bit 10 -> SSEL1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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