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68000 Motherboard User’s Manual

Rev. A

Page 27 of 54

Figure 11: Clock Frequency Divider Overview

7.6

External Run Control

Inputs are provided within the stack connector interface to command the system’s /HALT
and /RESET signals.  These are the HALT_CMD and RESET_CMD inputs, appearing at
A1CON160/162,  pins  22  and  24  respectively.    When  left  open,  these  inputs  do  not
interfere with the operation of these signals.  However, asserting the inputs as logic high
commands the corresponding control signal to be asserted.  These inputs provide a means
of externally controlling the Halt and Reset signal states of the system.

Following  power-up,  the  68000  processor  must  be  held  in  reset  with  both  /HALT  and
/RESET lines asserted for a minimum of 100ms.  This functionality may be provided by
the on-board Discrete Voltage Supervisor.  For a subsequent reset after power-up, a pulse
of a minimum of 10 clock cycles must be applied to both /HALT and /RESET together to
accomplish the processor reset.  For further detail, see reference number 56 in the ‘AC
Electrical Specifications’ section of the Motorola 68000 User’s Manual.

7.7

Reset Pulse Generator

The Reset Pulse Generator’s function is simple.  It generates a pulse of at least one clock
cycle when the processor reset signal, /RESET, is released.  It provides both positive and
negative polarity pulses on RST_PULSE and /RST_PULSE lines respectively, which are
made  available  on  positions  25  and  26  of  A1CON160/162.    Only  the  /RST_PULSE
signal is used by the MB68k-100 circuitry.  Internally, this reset pulse is used to latch on-
board peripheral write registers to their initial, start-up values.  These registers catch the
value of the LSB data bus, which has pull-down resistors that dominate during reset.  The
on-board registers, therefore, start with a zero value.

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Summary of Contents for MB68k-100

Page 1: ...Rev A Grant K c 2011 ...

Page 2: ...ion 23 7 1 2 Active Reversed Connection Protection 23 7 1 3 Discrete Voltage Supervisor 23 7 2 The 68000 Microprocessor 24 7 3 The Pintercept Headers 24 7 4 Indicators 24 7 5 The System Clock 25 7 6 External Run Control 27 7 7 Reset Pulse Generator 27 7 8 The Start Vector Selector SVS 28 7 9 Address Space Mapping 29 7 10 Data Strobed Flow Logic 30 7 11 Bus Cycle Termination 30 7 11 1 Bus Terminati...

Page 3: ...rface Connectors 39 7 15 2 Mounting Holes 41 7 16 Quick Jumper Reference 43 8 THE SOFTER SIDE 46 8 1 Software Development Tools 46 8 1 1 m68k elf 46 8 1 2 EASy68K 47 8 2 MB68k 100 Software Examples 47 8 3 Software Notes on the MB68k 100 50 9 GETTING STARTED 51 10 TROUBLESHOOTING 52 11 DESIGN ERRATA AND COMMENTARY 52 12 PROJECT DOCUMENT COMPENDIUM 54 13 DOCUMENT REVISION HISTORY 54 ...

Page 4: ...nology were stiflingly simple and fraught with debilitating resource limitations and programming bottlenecks In contrast the more contemporary end of this spectrum presents the highly integrated and massively sophisticated architectures of more recent years where the designer grapples with hundreds of pages of product documentation and hundreds of tiny pins to connect But along this gradient of mi...

Page 5: ...e past as the processor s User s Manual cover art asserts The first generation sports a 32 bit architecture masquerading in 16 bit hardware Although later descendants expanded to true 32 bit form the 68000 s 32 bit data and address registers are siphoned to the outside world through a 16 bit data bus and 24 bit address bus These copious data and address register banks each with eight 32 bit regist...

Page 6: ... Channel MOS technology the pull up device in each gate s output stage is a heavily doped depletion mode field effect transistor FET This FET initially operates largely as a current source rather than a simple resistor allowing for a faster 0 to 1 transition This capability in turn translates to faster overall operation And this technology with its 3 5µm feature size also allowed a higher number o...

Page 7: ...ion of each circuit section Among the sections are microcode and nanocode ROMs control logic and situated along the bottom the data Arithmetic Logic Unit and two address Arithmetic Logic Units The power and grace of the 68000 leaves a deep impression on the evolution of computer and microprocessor technology And in doing so it leaves an impression on those with interest in detailed hardware and so...

Page 8: ...ese binary digits physically correspond to the voltages present on the signals within the computer The digit 1 is typically represented by a high voltage while 0 is a low voltage A succession of numbers over time in a digital system appears as a signal waveform on the wire with a separate parallel wire for each digit s place All data stored and processed in a computer can be thought of as numbers ...

Page 9: ...ess is a number that uniquely specifies the device with which the processor requests to communicate Each device available to the processor has its own unique address The processor also sets the Read Write R W signal The state of this signal indicates whether the operation being prepared is to be a Read or a Write These terms are defined in the sense of the processor the Read reads data from the ad...

Page 10: ... Through these steps the input data is transferred to the light bar output Figure 3 Data Flow Diagrams Write The devices within the computer are organized under the control of the microprocessor The processor addresses the device required for the current operation completes the data transaction with that device and then continues to the next operation The sequence of operations that the microproce...

Page 11: ...on the registers keep immediate track of the algorithm being executed A register may be thought of as memory for a single general purpose variable held within the processor In practice many microprocessor instructions that make up a typical program involve performing arithmetic and comparison operations on register data as well as moving data between those registers and devices of the Data Bus suc...

Page 12: ...omment 00 2E7C 00004000 MOVEA L ONBD_BANK0 ONBD_BANK0_SZ A7 supervisor stack at top of on board SRAM 06 207C 00003C00 MOVEA L ONBD_BANK0 ONBD_BANK0_SZ ONBD_SUPSTCK_SZ A0 0C 4E60 MOVE L A0 USP user stack next in on board SRAM 0E 46FC 0000 MOVE W 0000 SR enter user mode and set up interrupt mask for level 0 12 13FC 00FE 000A0000 MOVE B FE ONBD_INTEN enable interrupts in hardware ...

Page 13: ...l User s Documentation seen here Full Process Documentation Extensive Access to Design Information Rich Example Software with Commenting Versatile On Board Configurability Facilities for Signal Interception and Test Points Power Conditioning Supply Voltage Supervisory Function Indicators for Halt Reset Run and Power Multiple Selectable Clock Sources Run Control with External Power Up and Push Butt...

Page 14: ...alled with 7805 7 2 VDC Supply Voltage minimum Voltage Regulation VR120 installed with PT5101 9 2 VDC Voltage Regulation bypassed 5 3 VDC Voltage Regulation 7805 power limit 12 VDC Supply Voltage maximum Voltage Regulation PT5101 Input Voltage Limit 38 VDC Operating Temperature Lower limit by ICs Upper limit by Power Input Circuitry Temperature 0 30 C Footprint 12 x 10 in all limits listed here ar...

Page 15: ...ow And the arteries of this flow are the computer s networks of buses all managed by its control logic The complex design of a computer system naturally breaks down into a collection of modules each serving a straightforward and simple function Here that breakdown is explored SVS Stack Connector Pintercept Pintercept 68000 Glue Logic Strobe Logic Wait State Stack Connector Reset Pulse Auto DTACK O...

Page 16: ...tion codes that define the operation of the system from ROM Meanwhile the Address Bus performs the crucial task of specifying which device is involved in the data transfer that is taking place on the Data Bus These transfers are controlled by another group of signals collectively known as the Control Bus Though not parallel in function like the groups of lines in the Data and Address Buses these i...

Page 17: ... appropriate signaling to enable the selected device 4 Also in parallel the Data Strobed Flow Logic issues the appropriate Read and Write enable signals for the devices on the data bus according to the direction of required data flow 5 The selected device responds to participate in the bus transaction For a Read operation the device places the requested data onto the Data Bus For a Write operation...

Page 18: ...000 DIP Pin Diagram 6 3 Bus Architecture of the 68000 The 16 bit 68000 data bus is comprised of two conjoined 8 bit data buses They are referred to as the upper and lower data buses or informally the hi and lo The upper bus carries the most significant byte data D8 15 and the lower carries the least significant byte D0 D7 Since the 68000 uses a big endian byte ordering convention lower addresses a...

Page 19: ...oprocessors of the 1970 s operated more slowly than the peripheral and memory devices with which they typically interfaced so these processors simply initiated a read or write operation at one phase in the bus cycle and unconditionally completed that operation at a later phase in the cycle This imposed an external limit on the processor speed in that the bus device must have completed its operatio...

Page 20: ...CK is tested to close the cycle However because the write data and control signals remain valid for a clock cycle after termination of the bus cycle the time available to the bus device without special DTACK timing provisions is also one and a half clock cycle periods Because the 68000 bus architecture uses the DTACK termination signal to close the bus cycle the speed of the devices on the bus pla...

Page 21: ...Cycle Here the Address Bus AS UDS LDS and R W signals are generated by the processor to control bus The Data Bus and DTACK signals then are generated in response by the external hardware The Data Bus supplies the data to be read into the processor and DTACK signals completion of the cycle Figure 9 Regular Bus Write Cycle Here again the Address Bus AS UDS LDS and R W signals are generated by the pr...

Page 22: ...ess enable signal for the 6800 bus logic to begin the 6800 bus cycle This cycle closes automatically with the advance of the E clock 7 Circuit Description The subsequent sections provide additional detail to the function and operation of the MB68k 100 motherboard s subcircuits Refer to section 12 for references to additional documentation 7 1 Power Input To start the MB68k 100 motherboard requires...

Page 23: ...r polarity a side effect of the FET s operation is that it introduces a slight voltage drop on the positive supply line as a function of input voltage and current At 5VDC the FET resistance is approximately 300m of inline resistance A bypass jumper A1JP120 allows the FET to be circumvented 7 1 3 Discrete Voltage Supervisor The Discrete Voltage Supervisor is designed to provide reset control of the...

Page 24: ...ffers a bus cycle compatibility mode with 6800 peripheral devices bus arbitration prioritized interrupts execution state visibility through FCn outputs and run control The PCB supports the DIP 64 component package which accommodates devices with clock speeds from 4 to 20MHz 7 3 The Pintercept Headers The processor is flanked by two 0 1 pitch 2x32 pin headers These are the Pintercept headers with r...

Page 25: ...requency See Figure 11 for an overview diagram Its clock source may be selected as either of the crystal oscillator modules or the discrete component oscillator The Divider Source Selector A1JP111 selects the clock source for this divider See Table 10 below Its divisor may be selected in the range of even numbers 2 through 18 as specified by the Clock Divisor Selector A1JP110 See Table 9 below The...

Page 26: ...5 6 8 7 8 10 9 10 12 11 12 14 13 14 16 15 16 18 17 18 Table 10 Divider Source Selector A1JP111 Divider Source Jumper Position OSCHCLK OSC110 1 2 OSCFCLK OSC111 3 4 Discrete Crystal Oscillator XCLK_RAW 5 6 Table 11 System Clock Source Selector A1JP112 Clock Source Jumper Position OSCHCLK OSC110 1 2 OSCFCLK OSC111 3 4 Discrete Crystal Oscillator XCLK_RAW 5 6 Symmetric Discrete Crystal Oscillator HXC...

Page 27: ...crete Voltage Supervisor For a subsequent reset after power up a pulse of a minimum of 10 clock cycles must be applied to both HALT and RESET together to accomplish the processor reset For further detail see reference number 56 in the AC Electrical Specifications section of the Motorola 68000 User s Manual 7 7 Reset Pulse Generator The Reset Pulse Generator s function is simple It generates a puls...

Page 28: ... assigning the start vector address values The values read for the initial stack pointer and program counter vectors are specified according to the jumper configuration Eight address bits corresponding to address lines A16 A23 are specified on the Start Vector Address Selector jumper A1JP180 Other bytes read as zero This jumper selectable range includes the Block Address making the memory device u...

Page 29: ...0 specify the address block The eight address blocks each occupy 1MB of memory space spanning addresses x00000 xFFFFF These address blocks correspond to chip select lines CS0 CS7 Also several on board devices are included in the design These may be mapped to a Block Address as selected by the On Board Block Address Selector A1JP280 See the section 7 12 On Board Peripherals for further detail It is...

Page 30: ...tion of the 68000 the market was dominated by processors that anticipated the timely response of devices on the bus as part of the bus cycle This meant that the system as a whole was tightly coupled to the speed of the slowest bus device To avoid limitations on processor speed by slow bus devices the 68000 instead uses what is termed Asynchronous Bus Control This bus control scheme uses acknowledg...

Page 31: ...o request Autovectoring During the Interrupt Acknowledge Cycle the processor requests the interrupt vector number to indicate which interrupt service to execute for the pending interrupt event For this the Interrupt Acknowledge Cycle is terminated by DTACK However termination of this bus cycle via VPA commands the processor to use its Autovectoring feature instead where the interrupt vector number...

Page 32: ...is greater than the period provided by the processor before DTACK is tested to close the bus cycle This period is one and a half processor clock periods for both read and write cycles Each wait state provides one clock period of delay in the bus cycle For further detail on the bus cycle see Bus Control Signal Timing in section 6 4 7 12 On Board Peripherals Several on board peripherals are included...

Page 33: ...bit Reset 00 The Interrupt Enable Register is an 8 bit register that controls the availability of the On Board Interrupt Logic to trigger interrupts Bit 0 of this register is a global mask set to 1 to disable all 7 levels of interrupt sources Bits 1 7 are individual controls for each of the 7 interrupt levels organized respectively With its bit set to 1 the corresponding interrupt level is availab...

Page 34: ...Entropy Generator Addr ONBD_BASE C0000 Clock Synchronization Register bit 3 Size 1 bit The Hardware Entropy Generator circuit provides a bit whose state is the result of measuring an avalanche process of a reverse biased diode This bit appears as bit 3 of the Clock Synchronization Register The intent is that the avalanche process has an unpredictable behavior over time and that this can be used as...

Page 35: ...components in bench test The selection of any particular avalanche diode was the key driver impacting the entropy generator s performance Of course generating randomness is a cryptic art and in no way should this entropy source be considered cryptologically secure or even critically reliable Example output of the Hardware Entropy Generator is given below in Table 17 per the high speed sampling pro...

Page 36: ...111000011111100000000000000000001111111111000011111100001111 11000011111111111111111111111110000000000111100000011110000001111000000000000000 00000000001111111111000011111100001111110000000000111111111111111111111111111111 11100000011110000001111000000111111111111111111111111111110000111111000011111100 00111111111111111111111111111111111111111000000111100000011111111111111111111111 111111111111111...

Page 37: ...for total current The latch initializes to zero at start up 7 13 Interrupt Logic On board interrupt enable and latching logic is provided in hardware for use with the 68000 s Autovectoring functionality This logic operates with an independent channel for each of the seven interrupt levels Each channel has an enable bit in the Interrupt Enable Register These bits are 1 7 for interrupt levels 1 7 Bi...

Page 38: ...oard Banks support EPROM SRAM devices according to jumper settings per the configuration outlined in Table 18 below EPROM device support ranges from 2732 4kB x 2 devices through to 27512 64kB x 2 devices Note that the 2732 device is shifted in the socket with the device s pin 1 positioned in pin 3 of the socket With all but the 27512 address wrap around aliasing occurs due to ignored address lines...

Page 39: ...h connector are connections to negative ensuring that the negative contact is made first in case of a hot insertion This practice however is not intended Table 19 Stack Connector CON160 CON162 Pin Map Name Description Pin Pin Name Description GND Supply Negative 1 2 GND Supply Negative VCC Supply Positive 3 4 VCC Supply Positive M68K_AS 68000 Address Strobe 5 6 M68K_UDS 68000 Upper Data Strobe M68...

Page 40: ...ddress 4 Select 45 46 CS5 Block Address 5 Select CS6 Block Address 6 Select 47 48 CS7 Block Address 7 Select ADDR_DEC_EN Input to actively disable the On Board Block Address Decoder 49 50 STACKEVEN50 Unused STACKEVEN51 Unused 51 52 STACKEVEN52 Unused STACKEVEN53 Unused 53 54 STACKEVEN54 Unused STACKEVEN55 Unused 55 56 STACKEVEN56 Unused STACKEVEN57 Unused 57 58 STACKEVEN58 Unused STACKEVEN59 Unuse...

Page 41: ...KODD45 Unused with test point 45 46 STACKODD46 Unused with test point STACKODD47 Unused with test point 47 48 STACKODD48 Unused with test point STACKODD49 Unused with test point 49 50 STACKODD50 Unused with test point STACKODD51 Unused with test point 51 52 STACKODD52 Unused with test point STACKODD53 Unused 53 54 STACKODD54 Unused STACKODD55 Unused 55 56 STACKODD56 Unused STACKODD57 Unused 57 58 ...

Page 42: ...tem Type Item Detail Manufacturer Manu P N Distributor Dist P N Standoff PC 104 4 40 600 M F Hex Nylon Keystone Electronics 4799 Digi Key 4799K ND Standoff PC 104 4 40 600 M F Hex Brass Keystone Electronics 8799 Digi Key 8799K ND Hardware Nut 4 40 0 062 thick 0 184 width Brass Tyco Electronics 5205821 2 Digi Key A35230 ND ...

Page 43: ...ut from Discrete Crystal Clock XCLK_RAW A1JP112 System Clock Source Selector Selects the system clock source Pos 1 Half size clock module OSC110 OSCHCLK Pos 2 Full size clock module OSC111 OSCFCLK Pos 3 Raw output from Discrete Crystal Clock XCLK_RAW Pos 4 Symmetric Discrete Crystal Oscillator HXCLK_OUT Pos 5 Symmetric Divided Clock CLKDIVOUT Pos 6 Stack Connector CLKIN Input CLKIN A1JP120 Reversa...

Page 44: ...clude Block Address 2 CS2 Pos 4 Include Block Address 3 CS3 Pos 5 Include Block Address 4 CS4 Pos 6 Include Block Address 5 CS5 Pos 7 Include Block Address 6 CS6 Pos 8 Include Block Address 7 CS7 A1JP260 DTACK Source Selector Selects M68k DTACK control source Pos 1 Automatic acknowledgement from Automatic DTACK Feedback Pos 2 External DTACK from Stack Connector Pos 3 Automatic acknowledgement with...

Page 45: ...of clock cycles until Bus Error timeout Pos 1 Timeout of 32 clock cycles Pos 2 Timeout of 64 clock cycles Pos 3 Timeout of 128 clock cycles Pos 4 Timeout of 256 clock cycles Pos 5 Timeout of 512 clock cycles Pos 6 Timeout of 1024 clock cycles Pos 7 Timeout of 2048 clock cycles Pos 8 Timeout of 4096 clock cycles A1JP331 Bus Error Timer Enable Enables Bus Error Timer 1 2 Enable Jumper 6264 62256 273...

Page 46: ...are development under Linux Cygwin and other environments Its assembly language support uses AT T mnemonics Table 22 Basic m68k elf Assembler Script With the script named m the project files are all assumed to have the file name projName with their appropriate extension by file type m projName m68k elf as m68000 o 1 o 1 s Assemble source code specified in the command line to create object file m68...

Page 47: ...or optimum speed BlockFillB trival version Implements memory fill function with a byte value Input D0 L Block length to fill D1 B Byte fill value A0 L Target block base address Output None Registers Destroyed A0 D0 L D1 L BLOCKFILLB Label to indicate the start of the BLOCKFILLB routine return if fill length is zero SUB L 1 D0 Subtract one from the fill space byte count because DBF loop control ins...

Page 48: ...2 Transfer the target address s least significant bit LSB into the Carry condition code flag BCC BLOCKFILLB_ALIGNED If the address s LSB is clear then the address is even and the starting address is 16 bit word aligned in memory With the fill position aligned to an even address 16 bit transfers may be used to write to memory to take advantage of the full data bus width return if fill length is zer...

Page 49: ...nsfer skip past the 32 bit transfer loop SUB L 1 D2 Subtract one from the fill space 32 bit transfer count because DBF loop control instruction terminates on occurrence of 1 BLOCKFILLB_LONGLOOP Label for internal fill loop of 32 bit transfers MOVE L D1 A0 Write four bytes at a time and advance the position pointer by four bytes DBF D2 BLOCKFILLB_LONGLOOP Subtract one from the 32 bit transfer count...

Page 50: ... execution of the routine by returning to the calling parent 8 3 Software Notes on the MB68k 100 Upon initialization the SVS sets the Supervisor Stack Pointer to the same location used to begin software execution The stack pointer typically must be initialized in software before the stack is used An interrupt is acknowledged in the interrupt service routine by clearing the corresponding enable bit...

Page 51: ...into an on board memory bank Jumper settings may be set as indicated in section 7 14 to specify the device type Figure 13 On Board ROM Installation 3 Set Up the Start Vector Selector The SVS s Start Vector Address Selector jumper A1JP180 must be specified to point to the intended start up memory address for the processor to locate the software Refer to section 7 8 The Start Vector Selector SVS for...

Page 52: ...erns that would have driven fundamental differences in the design were it to be done over again 1 Both sets of stack connectors could be positioned adjacent to each other in the layout for improved signal path impedance and signal integrity Signals present on other connectors could also be grouped in closer proximity for the same reason This system however is only designed to operate at 10MHz and ...

Page 53: ...eset condition The reason for this is that the processor immediately resumes data bus activity upon releasing its assertion of RESET but the design assumes the data bus be zero during this reset period through the Reset Pulse Generator delay The peripherals may therefore latch the arbitrary data bus state as they initialize from their reset Workarounds include a Positioning a zero in software code...

Page 54: ...00 project s controlled documentation tree MB68k 100 Schematic MB68k 100 x MB68k 100 Layout MB68k 100 x Manufacturing Data MB68k 100 Manufacturing Data 68000 Motherboard BOM MB68k 100 Parts List MB68k 100 Motherboard Assembly Procedure MB68k 100 Assembly Procedure MB68k 100 Motherboard Test Procedure MB68k 100 Test Procedure TstExamp MB68k 100 Test Support Example Software TemplateShell MB68k 100 ...

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