M68EML08GZ16 Emulation Module - Version 4.0
User’s Manual
28
Support Information
MOTOROLA
Support Information
3.3 Logic Analyzer Connectors J1 and J13
Connectors J1 and J13 are the EML08GZ16 logic analyzer connectors.
Figure 3-3 and Table 3-3 give pin assignments and signal descriptions for
connector J1, which has pod 1 signals. Figure 3-4 and Table 3-4 give pin
assignments and signal descriptions for connector J13, which has pod 2
signals.
Figure 3-3 Logic Analyzer Connector J1 Pin Assignments
J1
NC 1
•
•
2
NC
T12 3
•
•
4
LBOX
RST_B 5
•
•
6
NC
TEST 7
•
•
8
EMUX
TEST 9
•
•
10
LRW
LIR_B 11
•
•
12
AD7
AD6 13
•
•
14
AD5
AD4 15
•
•
16
AD3
AD2 17
•
•
18
AD1
AD0 19
•
•
20
GND
Table 3-3 Logic Analyzer Connector J1 Signal Descriptions
Pin
Label
Signal
1, 2, 6
NC
No connection
3
T12
SYSTEM BUS CLOCK — Clock that matches the internal emulation MCU
bus clock
4
LBOX
LAST BUS CYCLE — Output signal that the emulator asserts to
indicate that the target system MCU is in the last bus cycle of an
instruction
.
5
RST_B
COP RESET — Active-low output signal indicating (1) the target driving its
reset pin, or (2) the platform board driving a reset to the emulator module.
7, 9
TEST
Test pins are used only during system development and factory test.
8
EMUX
MUXED CONTROL
— Output from the emulation MCU that, during
different phases of the clock, drives R/W, LIR_B, and LAST signals.
10
LRW
LATCHED READ/WRITE — Output signal from the target MCU. If high, the
target MCU is reading. If low, the target MCU is writing.
11
LIR_B
LOAD INSTRUCTION REGISTER — Active-low output signal indicating
that the target MCU
is fetching an instruction.
12 — 19
AD7 — AD0
PFB DATA BUS (lines 7—0) — Outputs the data lines going to the platform
board.
20
GND
GROUND
