Receiver Front-End
Introduction/Theory of Operation
3.1-25
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the
magnitude of the loop current is increased by enabling the IADAPT line (U5701-31) for a certain
software programmable time (Adapt Mode). The adapt mode timer is started by a low to high
transient of the FRACN CE line. When the synthesizer is within the lock range the current is
determined only by the resistors connected to CPBIAS 1, CPBIAS 2, or the internal current source.
A settled synthesizer loop is indicated by a high level of signal LOCK DET (U5701-2).
LOCK DET adds up with signal SQ DET, weighted by resistors R0113, R0114, and is routed to one
of the
µ
P´s ADCs input U0101-43. From the voltage weighted by the resistors the
µ
P determines
whether SQ DET, LOCK DET or both are active.
In order to modulate the PLL the two spot modulation method is utilized. Via pin 8 (MODIN) on
U5701 the audio signal is applied to both the A/D converter (low freq path) as well as the balance
attenuator (high freq path). The A/D converter converts the low frequency analogue modulating
signal into a digital code that is applied to the loop divider, thereby causing the carrier to deviate. The
balance attenuator is used to adjust the VCO’s deviation sensitivity to high frequency modulating
signals. The output of the balance attenuator is present at the MODOUT port (U5701-28) and
connected to the VCO modulation diode D5731 via L5731, C5732.
VHF (136-174MHz) SPECIFIC CIRCUIT DESCRIPTION
11.0
Receiver Front-End
The receiver is able to cover the VHF range from 136 to 174 MHz. It consists of four major blocks:
front-end, mixer, first IF section and IF IC. Antenna signal pre-selection is performed by two varactor
tuned bandpass filters. A double balanced schottky diode mixer converts the signal to the first IF at
45.1 MHz.
Two crystal filters in the first IF section and two ceramic filters in the second IF section provide the
required selectivity. The second IF at 455 kHz is mixed, amplified and demodulated in the IF IC. The
processing of the demodulated audio signal is performed by an audio processing IC located in the
controller section.
11.1
Front-End Band-Pass Filter and Pre-Amplifier
A two pole pre-selector filter tuned by the dual varactor diode D3301 pre-selects the incoming signal
(PA RX) from the antenna switch to reduce spurious effects to following stages. The tuning voltage
(FE CNTL VLTG) ranging from 2 volts to 8 volts is controlled by a Digital to Analogue (D/A) converter
(U0731-11) in the controller section. A dual hot carrier diode (D3303) limits any inband signal to
0dBm to prevent damage to the pre-amplifier.
The RF pre-amplifier is an SMD device (Q3301) with collector base feedback to stabilize gain,
impedance, and intermodulation. The collector current of approximately 11-16 mA, drawn from the
voltage 9V3 via L3302, is controlled by a current source composed of Q3302, R3302, R3300, and
R3311 - R3313. In transmit mode the high K9V1 signal fed through diode D3300 switches off the
current source and in turn the pre-amplifier. In receive mode K9V1 must be low to switch on the
current source. A 3 dB pad (R3306 - R3308 and R3316 - R3318) stabilizes the output impedance
and intermodulation performance.
Summary of Contents for GM1200E
Page 2: ...ii ...
Page 4: ...Cautions and Warnings iv ...
Page 6: ...Cautions and Warnings vi ...
Page 8: ...Contents viii Detailed Service Manual ...
Page 10: ...Table of Contents 1 ii Introduction ...
Page 14: ...Table of Contents 2 ii Control Head Level 3 Information ...
Page 16: ...Table of Contents 2 1 ii Introduction Theory of Operation ...
Page 24: ...Table of Contents 2 2 ii PCB Schematic Diagram and Parts List ...
Page 26: ...Table of Contents 3 ii UHF VHF Radio Level 3 Information ...
Page 30: ...Table of Contents 3 1 iv Introduction Theory of Operation ...
