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Serial Host Interface

Serial Host Interface Programming Model

MOTOROLA

DSP56367

9-7

The SHI interrupt vector table is shown in Table 9-1 and the exception priorities generated by
the SHI are shown in Table 9-2.

9.5.1

SHI INPUT/OUTPUT SHIFT REGISTER (IOSR)—HOST SIDE

The variable length Input/Output Shift Register (IOSR) can be viewed as a serial-to-parallel
and parallel-to-serial buffer in the SHI. The IOSR is involved with every data transfer in both
directions (read and write). In compliance with the I

2

C and SPI bus protocols, data is shifted

in and out MSB first. In 8-bit data transfer modes, the most significant byte of the IOSR is
used as the shift register. In 16-bit data transfer modes, the two most significant bytes become
the shift register. In 24-bit transfer modes, the shift register uses all three bytes of the IOSR
(see Figure 9-5).

Table 9-1 SHI Interrupt Vectors

Program Address

Interrupt Source

VBA:$0040

SHI Transmit Data

VBA:$0042

SHI Transmit Underrun Error

VBA:$0044

SHI Receive FIFO Not Empty

VBA:$0048

SHI Receive FIFO Full

VBA:$004A

SHI Receive Overrun Error

VBA:$004C

SHI Bus Error

Table 9-2 SHI Internal Interrupt Priorities

Priority

Interrupt

Highest

SHI Bus Error

SHI Receive Overrun Error

SHI Transmit Underrun Error

SHI Receive FIFO Full

SHI Transmit Data

Lowest

SHI Receive FIFO Not Empty

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Summary of Contents for DSP56367

Page 1: ... 0 Published 02 01 DSP56367UM D Motorola Order Number DSP56367 24 Bit Digital Signal Processor User s Manual Motorola Incorporated Semiconductor Products Sector 6501 William Cannon Drive West Austin TX 78735 8598 ...

Page 2: ...n or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life Buyer a...

Page 3: ...1 Host Interface HDI08 1 12 1 5 2 General Purpose Input Output GPIO 1 12 1 5 3 Triple Timer TEC 1 13 1 5 4 Enhanced Serial Audio Interface ESAI 1 13 1 5 5 Enhanced Serial Audio Interface 1 ESAI_1 1 13 1 5 6 Serial Host Interface SHI 1 14 1 5 7 Digital Audio Transmitter DAX 1 14 Section 2 Signal Connection Descriptions 2 1 2 1 Signal Groupings 2 1 2 2 Power 2 4 2 3 Ground 2 4 2 4 Clock and PLL 2 5 ...

Page 4: ...I I2 C Protocol Timing 3 62 3 13 1 Programming the Serial Clock 3 63 3 14 Enhanced Serial Audio Interface Timing 3 66 3 15 Digital Audio Transmitter Timing 3 72 3 16 Timer Timing 3 73 3 17 GPIO Timing 3 74 3 18 JTAG Timing 3 75 Section 4 Design Considerations 4 1 4 1 Thermal Design Considerations 4 1 4 2 Electrical Design Considerations 4 3 4 3 Power Consumption Considerations 4 4 4 4 PLL Performa...

Page 5: ... Model 7 1 7 2 1 Port B Signals and Registers 7 1 7 2 2 Port C Signals and Registers 7 2 7 2 3 Port D Signals and Registers 7 2 7 2 4 Port E Signals and Registers 7 2 7 2 5 Timer Event Counter Signals 7 2 Section 8 Host Interface HDI08 8 1 8 1 Introduction 8 1 8 2 HDI08 Features 8 1 8 2 1 Interface DSP side 8 1 8 2 2 Interface Host Side 8 2 8 3 HDI08 Host Port Signals 8 4 8 4 HDI08 Block Diagram 8...

Page 6: ... 14 8 5 6 10 HPCR Host Data Strobe Polarity HDSP Bit 9 8 14 8 5 6 11 HPCR Host Address Strobe Polarity HASP Bit 10 8 15 8 5 6 12 HPCR Host Multiplexed bus HMUX Bit 11 8 15 8 5 6 13 HPCR Host Dual Data Strobe HDDS Bit 12 8 15 8 5 6 14 HPCR Host Chip Select Polarity HCSP Bit 13 8 16 8 5 6 15 HPCR Host Request Polarity HRP Bit 14 8 16 8 5 6 16 HPCR Host Acknowledge Polarity HAP Bit 15 8 16 8 5 7 Data...

Page 7: ...Characteristics Of The SPI Bus 9 3 9 4 SHI Clock Generator 9 4 9 5 Serial Host Interface Programming Model 9 4 9 5 1 SHI Input Output Shift Register IOSR Host Side 9 7 9 5 2 SHI Host Transmit Data Register HTX DSP Side 9 8 9 5 3 SHI Host Receive Data FIFO HRX DSP Side 9 8 9 5 4 SHI Slave Address Register HSAR DSP Side 9 9 9 5 4 1 HSAR Reserved Bits Bits 19 17 0 9 9 9 5 4 2 HSAR I2C Slave Address H...

Page 8: ...9 7 1 SPI Slave Mode 9 22 9 7 2 SPI Master Mode 9 23 9 7 3 I2 C Slave Mode 9 24 9 7 3 1 Receive Data in I2 C Slave Mode 9 25 9 7 3 2 Transmit Data In I2 C Slave Mode 9 26 9 7 4 I2 C Master Mode 9 27 9 7 4 1 Receive Data in I2 C Master Mode 9 28 9 7 4 2 Transmit Data In I2 C Master Mode 9 28 9 7 5 SHI Operation During DSP Stop 9 29 Section 10 Enhanced Serial Audio Interface ESAI 10 1 10 1 Introduct...

Page 9: ...2 9 TCR Transmit Network Mode Control TMOD1 TMOD0 Bits 8 910 19 10 3 2 10 TCR Tx Slot and Word Length Select TSWS4 TSWS0 Bits 10 1410 21 10 3 2 11 TCR Transmit Frame Sync Length TFSL Bit 15 10 22 10 3 2 12 TCR Transmit Frame Sync Relative Timing TFSR Bit 16 10 24 10 3 2 13 TCR Transmit Zero Padding Control PADC Bit 17 10 24 10 3 2 14 TCR Reserved Bit Bits 18 10 24 10 3 2 15 TCR Transmit Section Pe...

Page 10: ...F1 Bit 1 10 35 10 3 5 3 SAICR Serial Output Flag 2 OF2 Bit 2 10 35 10 3 5 4 SAICR Reserved Bits Bits 3 5 9 23 10 36 10 3 5 5 SAICR Synchronous Mode Selection SYN Bit 6 10 36 10 3 5 6 SAICR Transmit External Buffer Enable TEBE Bit 7 10 36 10 3 5 7 SAICR Alignment Control ALC Bit 8 10 36 10 3 6 ESAI Status Register SAISR 10 38 10 3 6 1 SAISR Serial Input Flag 0 IF0 Bit 0 10 38 10 3 6 2 SAISR Serial ...

Page 11: ...itializing Just the ESAI Receiver Section 10 57 Section 11 Enhanced Serial Audio Interface 1 ESAI_1 11 1 11 1 Introduction 11 1 11 2 ESAI_1 Data and Control Pins 11 3 11 2 1 Serial Transmit 0 Data Pin SDO0_1 11 3 11 2 2 Serial Transmit 1 Data Pin SDO1_1 11 3 11 2 3 Serial Transmit 2 Receive 3 Data Pin SDO2_1 SDI3_1 11 3 11 2 4 Serial Transmit 3 Receive 2 Data Pin SDO3_1 SDI2_1 11 3 11 2 5 Serial T...

Page 12: ...ster PRRE 11 17 11 5 3 Port E Data register PDRE 11 18 Section 12 Digital Audio Transmitter 12 1 12 1 Introduction 12 1 12 2 DAX Signals 12 2 12 3 DAX Functional Overview 12 3 12 4 DAX Programming Model 12 4 12 5 DAX Internal Architecture 12 5 12 5 1 DAX Audio Data Register XADR 12 5 12 5 2 DAX Audio Data Buffers XADBUFA XADBUFB 12 6 12 5 3 DAX Audio Data Shift Register XADSR 12 6 12 5 4 DAX Non A...

Page 13: ...nd Registers 12 15 12 7 1 Port D Control Register PCRD 12 16 12 7 2 Port D Direction Register PRRD 12 16 12 7 3 Port D Data Register PDRD 12 17 Section 13 Timer Event Counter 13 1 13 1 Introduction 13 1 13 2 Timer Event Counter Architecture 13 1 13 2 1 Timer Event Counter Block Diagram 13 1 13 2 2 Individual Timer Block Diagram 13 2 13 3 Timer Event Counter Programming Model 13 3 13 3 1 Prescaler ...

Page 14: ...r Pulse Mode 1 13 15 13 4 1 3 Timer Toggle Mode 2 13 16 13 4 1 4 Timer Event Counter Mode 3 13 17 13 4 2 Signal Measurement Modes 13 17 13 4 2 1 Measurement Accuracy 13 18 13 4 2 2 Measurement Input Width Mode 4 13 18 13 4 2 3 Measurement Input Period Mode 5 13 19 13 4 2 4 Measurement Capture Mode 6 13 20 13 4 3 Pulse Width Modulation PWM Mode 7 13 21 13 4 4 Watchdog Modes 13 22 13 4 4 1 Watchdog ...

Page 15: ... D 1 2 Interrupt Addresses D 1 D 1 3 Interrupt Priorities D 1 D 1 4 Host Interface Quick Reference D 1 D 1 5 Programming Sheets D 1 D 2 Internal I O Memory MAp D 2 D 3 Interrupt Vector Addresses D 7 D 4 Interrupt Source Priorities within an IPL D 10 D 5 Host Interface Quick Reference D 12 D 6 Programming Sheets D 15 Appendix E Power Consumption Benchmark E 1 Appendix F IBIS Model F 1 Index 1 ...

Page 16: ...xvi MOTOROLA CONTENTS Paragraph Number Title Page Number ...

Page 17: ...esses 3 32 3 14 DRAM Out of Page Wait States Selection Guide 3 33 3 15 DRAM Out of Page Read Access 3 42 3 16 DRAM Out of Page Write Access 3 43 3 17 DRAM Refresh Access 3 44 3 18 Asynchronous Bus Arbitration Timing 3 45 3 19 Asynchronous Bus Arbitration Timing 3 46 3 20 Host Interrupt Vector Register IVR Read Timing Diagram 3 49 3 21 Read Timing Diagram Non Multiplexed Bus 3 50 3 22 Write Timing ...

Page 18: ...s for MSW X X CE 1 MS 0 SC 1 5 8 5 11 Memory Maps for MSW 0 0 CE 0 MS 1 SC 1 5 9 5 12 Memory Maps for MSW 0 1 CE 0 MS 1 SC 1 5 9 5 13 Memory Maps for MSW 1 0 CE 0 MS 1 SC 1 5 10 5 14 Memory Maps for MSW 0 0 CE 1 MS 1 SC 1 5 10 5 15 Memory Maps for MSW 0 1 CE 1 MS 1 SC 1 5 11 5 16 Memory Maps for MSW 1 0 CE 1 MS 1 SC 1 5 11 6 1 Interrupt Priority Register P 6 8 6 2 Interrupt Priority Register C 6 8...

Page 19: ...AI Block Diagram 10 2 10 2 TCCR Register 10 10 10 3 ESAI Clock Generator Functional Block Diagram 10 11 10 4 ESAI Frame Sync Generator Functional Block Diagram 10 13 10 5 TCR Register 10 15 10 6 Normal and Network Operation 10 20 10 7 Frame Length Selection 10 23 10 8 RCCR Register 10 26 10 9 RCR Register 10 30 10 10 SAICR Register 10 35 10 11 SAICR SYN Bit Operation 10 37 10 12 SAISR Register 10 ...

Page 20: ... 12 11 12 5 Clock Multiplexer Diagram 12 12 12 6 Examples of data organization in memory 12 15 12 7 Port D Control Register PCRD 12 16 12 8 Port D Direction Register PRRD 12 16 12 9 Port D Data Register PDRD 12 18 13 1 Timer Event Counter Block Diagram 13 2 13 2 Timer Block Diagram 13 3 13 3 Timer Module Programmer s Model 13 4 13 4 Timer Prescaler Load Register TPLR 13 5 13 5 Timer Prescaler Coun...

Page 21: ...ontrol Register D 33 D 19 ESAI Common Control Register D 34 D 20 ESAI Status Register D 35 D 21 ESAI_1 Multiplex Control Register D 36 D 22 ESAI_1 Transmit Clock Control Register D 37 D 23 ESAI_1 Transmit Control Register D 38 D 24 ESAI_1 Receive Clock Control Register D 39 D 25 ESAI_1 Receive Control Register D 40 D 26 ESAI_1 Common Control Register D 41 D 27 ESAI_1 Status Register D 42 D 28 DAX ...

Page 22: ...xxii MOTOROLA List of Figures Figure Number Title Page Number ...

Page 23: ...upt Timing 3 9 3 8 SRAM Read and Write Accesses 3 17 3 9 DRAM Page Mode Timings One Wait State Low Power Apps 3 23 3 10 DRAM Page Mode Timings Two Wait States 3 24 3 11 DRAM Page Mode Timings Three Wait States 3 27 3 12 DRAM Page Mode Timings Four Wait States 3 29 3 13 DRAM Out of Page and Refresh Timings Four Wait States 3 33 3 14 DRAM Out of Page and Refresh Timings Eight Wait States 3 35 3 15 D...

Page 24: ...08 Host Side Register Map 8 20 8 9 TREQ RREQ Interrupt Mode HDM 2 0 000 or HM 1 0 00 8 22 8 10 TREQ RREQ DMA Mode HM1 0 or HM0 0 8 22 8 11 HDRQ 8 22 8 12 Host Mode Bit Definition 8 23 8 13 INIT Command Effect 8 24 8 14 Host Request Status HREQ 8 27 8 15 Host Side Registers After Reset 8 29 9 1 SHI Interrupt Vectors 9 7 9 2 SHI Internal Interrupt Priorities 9 7 9 3 SHI Noise Reduction Filter Mode 9...

Page 25: ...ty 12 4 12 3 Clock Source Selection 12 8 12 4 Preamble Bit Patterns 12 11 12 5 Examples of DMA configuration 12 14 12 6 DAX Port GPIO Control Register Functionality 12 17 13 1 Prescaler Source Selection 13 6 13 2 Timer Control Bits for Timer 0 13 8 13 3 Timer Control Bits for Timers 1 and 2 13 9 13 4 Inverse Bit 13 9 14 1 Signal Identification by Name 14 3 14 2 Signal Identification by Pin Number ...

Page 26: ...xxvi MOTOROLA List of Tables Table Number Title Page Number ...

Page 27: ...hich describes the CPU core programming models and instruction set details This document as well as Motorola s DSP development tools can be obtained through a local Motorola Semiconductor Sales Office or authorized distributor To receive the latest information on this DSP access the Motorola DSP home page at the address given on the front cover of this document This manual contains the following s...

Page 28: ...RFACE SHI Describes the serial input output interface providing a path for communication and program coefficient data transfers between the DSP and an external host processor The SHI can also communicate with other serial peripheral devices SECTION 10 ENHANCED SERIAL AUDIO INTERFACE ESAI Describes one of the full duplex serial port for serial communication with a variety of serial devices SECTION ...

Page 29: ...o least significant bit LSB When several related bits are discussed they are referenced as AA n m where n m For purposes of description the bits are presented as if they are contiguous within a register However this is not always the case Refer to the programming model diagrams or to the programmer s sheets to see the exact location of bits within a register When a bit is described as set its valu...

Page 30: ...C The word reset is used in four different contexts in this manual the reset signal written as RESET the reset instruction written as RESET the reset operating state written as Reset and the reset function written as reset Note 1 PIN is a generic term for any pin on the chip 2 Ground is an acceptable low voltage level See the appropriate data sheet for the range of acceptable low voltage levels ty...

Page 31: ...eted to applications that require digital audio compression decompression sound field processing acoustic equalization and other digital audio algorithms The DSP56367 offers 150 million instructions per second MIPS using an internal 150 MHz clock at 1 8 V and 100 million instructions per second MIPS using an internal 100 MHz clock at 1 5 V Changes in core functionality specific to the DSP56367 are...

Page 32: ...NAL DATA BUS EXTAL PROGRAM RAM INSTR CACHE 3K x 24 PROGRAM ROM 40K x 24 Bootstrap PROGRAM INTERRUPT CONTROLLER PROGRAM DECODE CONTROLLE PROGRAM ADDRESS GENERATOR YAB XAB PAB YDB XDB PDB GDB MODA IRQA MODB IRQB DATA ALU 24X24 56 56 BIT MAC TWO 56 BIT ACCUMULATORS BARREL SHIFTER MODC IRQC PLL OnCE HOST INTER FACE DAX SPDIF Tx INTER FA CE 4 16 X MEMORY RAM 13K X 24 ROM 32K x 24 Y MEMORY RAM 7K X 24 R...

Page 33: ...pheral features are described in this manual DSP56300 modular chassis 150 Million Instructions Per Second MIPS with a 150 MHz clock at internal logic supply QVCCL of 1 8V 100 Million Instructions Per Second MIPS with a 100 MHz clock at internal logic supply QVCCL of 1 5V Object Code Compatible with the 56K core Data ALU with a 24 x 24 bit multiplier accumulator and a 56 bit barrel shifter 16 bit a...

Page 34: ...smitters master or slave I2 S Sony AC97 network and other programmable protocols The ESAI_1 shares four of the data pins with ESAI and ESAI_1 does NOT support HCKR and HCKT high frequency clocks Serial Host Interface SHI SPI and I2 C protocols multi master capability 10 word receive FIFO support for 8 16 and 24 bit words Byte wide parallel Host Interface HDI08 with DMA support Triple Timer module ...

Page 35: ... The DSP56300 core provides the following functional blocks Data arithmetic logic unit Data ALU Address generation unit AGU Program control unit PCU Bus interface unit BIU DMA controller with six channels Instruction cache controller PLL based clock oscillator OnCE module JTAG TAP Memory In addition the DSP56367 provides a set of on chip peripherals described in Section 1 Peripheral Overview on pa...

Page 36: ... be used as a source operand for the immediately following arithmetic operation without a time penalty i e without a pipeline stall 1 4 1 2 Multiplier Accumulator MAC The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and performs all of the calculations on data operands In the case of arithmetic instructions the unit accepts as many as three input operands and outputs...

Page 37: ...The contents of the associated modifier register specifies the type of arithmetic to be used in the address register update calculation The modifier value is decoded in the Address ALU 1 4 3 PROGRAM CONTROL UNIT PCU The PCU performs instruction prefetch instruction decoding hardware DO loop control and exception processing The PCU implements a seven stage pipeline and controls the different proces...

Page 38: ...e data exchange between blocks the following buses are implemented Peripheral input output expansion bus PIO_EB to peripherals Program memory expansion bus PM_EB to program memory X memory expansion bus XM_EB to X memory Y memory expansion bus YM_EB to Y memory Global data bus GDB between registers in the DMA AGU OnCE PLL BIU and PCU as well as the memory mapped registers in the peripherals DMA da...

Page 39: ...lock generator in the DSP56300 core is composed of two main blocks the PLL which performs clock input division frequency multiplication and skew elimination and the clock generator CLKGEN which performs low power division and clock pulse generation PLL based clocking Allows change of low power divide factor DF without loss of lock Provides output clock with skew elimination Provides a wide range o...

Page 40: ...pherals so a user can examine registers memory or on chip peripherals This facilitates hardware and software development on the DSP56300 core processor OnCE module functions are provided through the JTAG TAP signals More information on the OnCE module is provided in DSP56300 Family Manual On Chip Emulation Module 1 4 8 ON CHIP MEMORY The memory space of the DSP56300 core is partitioned into progra...

Page 41: ...ctions In addition to the core features previously discussed the DSP56367 provides the following peripherals 8 bit parallel host interface HDI08 with DMA support to external hosts As many as 37 user configurable general purpose input output GPIO signals Timer event counter TEC module containing three independent timers Memory switch mode in on chip memory Four external interrupt mode control lines...

Page 42: ...tions and addressing modes Since the host bus may operate asynchronously with the DSP core clock the HDI08 registers are divided into 2 banks The host side bank is accessible to the external host and the DSP side bank is accessible to the DSP core The HDI08 supports the following three classes of interfaces Host processor MCU connection DMA controller GPIO port Host port pins not in use may be con...

Page 43: ...sed by the timer it can be used as a General Purpose Input Output Pin Refer to Section 13 Timer Event Counter 1 5 4 ENHANCED SERIAL AUDIO INTERFACE ESAI The ESAI provides a full duplex serial port for serial communication with a variety of serial devices including one or more industry standard codecs other DSPs microprocessors and peripherals that implement the Motorola SPI serial protocol The ESA...

Page 44: ...rated circuit control I2 C bus The SHI supports either the SPI or I2C bus protocol as required from a slave or a single master device To minimize DSP overhead the SHI supports single double and triple byte data transfers The SHI has a 10 word receive FIFO that permits receiving up to 30 bytes before generating a receive interrupt reducing the overhead for data reception For more information on the...

Page 45: ...150 million instructions per second MIPS using an internal 150 MHz clock at 1 8 V and 100 million instructions per second MIPS using an internal 100 MHz clock at 1 3 3V Table 2 1 DSP56367 Functional Signal Groupings Functional Group Number of Signals Detailed Description Power VCC 20 Table 2 2 Ground GND 18 Table 2 3 Clock and PLL 3 Table 2 4 Address bus Port A1 18 Table 2 5 Data bus 24 Table 2 6 ...

Page 46: ...e GPIO port signals which are multiplexed with the HDI08 signals 3 Port C signals are the GPIO port signals which are multiplexed with the ESAI signals 4 Port D signals are the GPIO port signals which are multiplexed with the DAX signals 5 Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals Table 2 1 DSP56367 Functional Signal Groupings Continued Functional Group...

Page 47: ...WER GNDQ 4 SPDIF TRANSMITTER DAX ADO PD1 ACI PD0 TIMER 0 TIO0 TIO0 HREQ SCK SCL MISO SDA SS HA2 MOSI HA0 TMS PARALLEL HOST PORT HDI08 DSP56367 HAD 7 0 PB0 PB7 HAS HA0 PB8 HA8 HA1 PB9 HA9 HA2 PB10 HRW HRD PB11 HDS HWR PB12 HCS HA10 PB13 HOREQ HTRQ PB14 HACK HRRQ PB15 SERIAL AUDIO INTERFACE ESAI TDI SERIAL HOST INTERFACE SHI GNDS 2 VCCS 2 FST PC4 HCKT PC5 SCKR PC0 FSR PC1 HCKR PC2 SDO0 PC11 SDO0_1 P...

Page 48: ...e tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors There are four VCCD inputs VCCC 2 Bus Control Power VCCC is an isolated power for the bus control I O drivers This input must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors There are two VCCC inputs VCCH Host Power VCCH is a...

Page 49: ...tors There is one GNDH connection GNDS 2 SHI ESAI ESAI_1 DAX and Timer Ground GNDS is an isolated ground for the SHI ESAI ESAI_1 DAX and Timer This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors There are two GNDS connections Table 2 4 Clock and PLL Signals Signal Name Type State during Reset Signal Description ...

Page 50: ... the signals are tri stated To minimize power dissipation A0 A17 do not change state when external memory spaces are not being accessed Table 2 6 External Data Bus Signals Signal Name Type State during Reset Signal Description D0 D23 Input Output Tri stated Data Bus When the DSP is the bus master D0 D23 are active high bidirectional input outputs that provide the bidirectional data bus for externa...

Page 51: ...ro wait state access cannot be extended by TA deassertion otherwise improper operation may result TA can operate synchronously or asynchronously depending on the setting of the TAS bit in the operating mode register OMR TA functionality may not be used while performing DRAM type accesses otherwise improper operation may result BR Output Output deasserted Bus Request BR is an active low output neve...

Page 52: ...Signal Name Type State during Reset Signal Description MODA IRQA Input Input Mode Select A External Interrupt Request A MODA IRQA is an active low Schmitt trigger input internally synchronized to the DSP clock MODA IRQA selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction pr...

Page 53: ...ct D External Interrupt Request D MODD IRQD is an active low Schmitt trigger input internally synchronized to the DSP clock MODD IRQD selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing MODA MODB MODC and MODD select one of 16 initial chip operating modes latched...

Page 54: ...gnal is line 0 of the host address input bus HAS HAS Input Host Address Strobe When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected this signal is the host address strobe HAS Schmitt trigger input The polarity of the address strobe is programmable but is configured active low HAS following reset PB8 Input output or disconnected Port B 8 When the HDI08 is con...

Page 55: ...he polarity of the data strobe is programmable but is configured as active low HRD after reset PB11 Input Output or Disconnected Port B 11 When the HDI08 is configured as GPIO this signal is individually programmed as input output or internally disconnected The default state after reset for this signal is GPIO disconnected This input is 3 3V tolerant HDS HDS Input GPIO disconnected Host Data Strob...

Page 56: ...ed this signal is the transmit host request HTRQ output The polarity of the host request is programmable but is configured as active low HTRQ following reset The host request may be programmed as a driven or open drain output PB14 Input output or disconnected Port B 14 When the HDI08 is configured as GPIO this signal is individually programmed as input output or internally disconnected The default...

Page 57: ... is tri stated during hardware software and individual reset Thus there is no need for an external pull up in this state This input is 3 3V tolerant MISO Input or output Tri stated SPI Master In Slave Out When the SPI is configured as a master MISO is the master data input line The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data This signal is a S...

Page 58: ...deasserted the SHI ignores SCK clocks and keeps the MISO output signal in the high impedance state HA2 Input I2 C Slave Address 2 This signal uses a Schmitt trigger input when configured for the I2 C mode When configured for the I2 C Slave mode the HA2 signal is used to form the slave device address HA2 is ignored in the I2 C master mode This signal is tri stated during hardware software and indiv...

Page 59: ...m clock PC5 Input output or disconnected Port C 5 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This input is 3 3V tolerant FSR Input or output GPIO disconnected Frame Sync for Receiver This is the receiver frame sync input output signal In the asynchronous mode SYN 0 the FS...

Page 60: ...nput flag IF0 the data value at the pin will be stored in the IF0 bit in the SAISR register synchronized by the frame sync in normal mode or the slot in network mode PC0 Input output or disconnected Port C 0 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This input is 3 3V to...

Page 61: ...Port E 8 signal The default state after reset is GPIO disconnected This input is 3 3V tolerant SDO2 SD O2_1 Output GPIO disconnected Serial Data Output 2 When programmed as a transmitter SDO2 is used to transmit data from the TX2 serial transmit shift register When enabled for ESAI_1 operation this is the ESAI_1 Serial Data Output 2 SDI3 SDI 3_1 Input Serial Data Input 3 When programmed as a recei...

Page 62: ... the ESAI_1 Serial Data Output 0 PC11 PE1 1 Input output or disconnected Port C 11 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected When enabled for ESAI_1 GPIO this is the Port E 11 signal The default state after reset is GPIO disconnected This input is 3 3V tolerant Table 2 11 Enhanced Serial Audio Interface Signals Continued...

Page 63: ... Transmitter_1 This is the transmitter frame sync input output signal For synchronous mode this signal is the frame sync for both transmitters and receivers For asynchronous mode FST is the frame sync for the transmitters only The direction is determined by the transmitter frame sync direction TFSD bit in the ESAI transmit clock control register TCCR PE4 Input output or disconnected Port E 4 When ...

Page 64: ... state after reset is GPIO disconnected This input cannot tolerate 3 3V SDO4_1 Output GPIO disconnected Serial Data Output 4_1 When programmed as a transmitter SDO4 is used to transmit data from the TX4 serial transmit shift register SDI1_1 Input Serial Data Input 1_1 When programmed as a receiver SDI1 is used to receive serial data into the RX1 serial receive shift register PE7 Input output or di...

Page 65: ...TIO0 is used as input When timer 0 functions in watchdog timer or pulse modulation mode TIO0 is used as output The default mode after reset is GPIO input This can be changed to output or configured as a timer input output through the timer 0 control status register TCSR0 If TIO0 is not being used it is recommended to either define it as GPIO output immediately at the beginning of operation or leav...

Page 66: ...ut TDO is a test data serial output signal used for test instructions and data TDO is tri statable and is actively driven in the shift IR and shift DR controller states TDO changes on the falling edge of TCK TMS Input Input Test Mode Select TMS is an input signal used to sequence the test controller s state machine TMS is sampled on the rising edge of TCK and has an internal pull up resistor This ...

Page 67: ...f timing requirements adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum A maximum specification is calculated using a worst case variation of process parameter values in one direction The minimum specification CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields However...

Page 68: ...lerant input voltages VIN GND 0 3 to VCC 0 7 V Current drain per pin excluding VCC and GND I 10 mA Operating temperature range TJ 0 to 95 C Storage temperature TSTG 55 to 125 C Note 1 GND 0 V VCCP VCCQL 1 8 V 5 TJ 0 C to 95 C CL 50 pF All other VCC 3 3 V 5 TJ 0 C to 95 C CL 50 pF 2 Absolute maximum ratings are stress ratings only and functional operation at the maximum is not guaranteed Stress bey...

Page 69: ...nd Materials International 805 East Middlefield Rd Mountain View CA 94043 415 964 5111 Measurements were done with parts mounted on thermal test boards conforming to specification EIA JESD51 3 2 Junction to case thermal resistance is based on measurements using a cold plate per SEMI G30 88 with the exception that the cold plate temperature is used for the case temperature Table 3 2 Thermal Charact...

Page 70: ... 0 7 SHI I2C mode VIHP 1 5 VCC 0 7 EXTAL VIHX 0 8 VCC VCC Input low voltage D 0 23 BG BB TA ESAI_1 except SDO4_1 VIL 0 3 0 8 V MOD1 IRQ1 RESET PINIT NMI and all JTAG ESAI Timer HDI08 DAX ESAI_1 only SDO4_1 SHI SPI mode VILP 0 3 0 8 SHI I2C mode VILP 0 3 0 3 x VCC EXTAL VILX 0 3 0 2 x VCC Input leakage current IIN 10 10 µA High impedance off state input current 2 4 V 0 4 V ITSI 10 10 µA Output high...

Page 71: ...s 2 The Power Consumption Considerations section provides a formula to compute the estimated current requirements in Normal mode In order to obtain these results all inputs must be terminated i e not allowed to float Measurements are based on synthetic intensive DSP benchmarks The power consumption numbers in this specification are 90 of the measured results of this benchmark This reflects typical...

Page 72: ...led and MF 4 0 47 ETC PDF DF MF 0 53 ETC PDF DF MF Internal clock low period TL With PLL disabled ETC With PLL enabled and MF 4 0 49 ETC PDF DF MF 0 51 ETC PDF DF MF With PLL enabled and MF 4 0 47 ETC PDF DF MF 0 53 ETC PDF DF MF Internal clock cycle time with PLL enabled TC ETC PDF DF MF Internal clock cycle time with PLL disabled TC 2 ETC Instruction cycle time ICYC TC Note 1 DF Division Factor ...

Page 73: ...xternal clock should be 3 ns maximum Ef 0 120 0 2 EXTAL input high1 2 With PLL disabled 46 7 53 3 duty cycle6 ETH 3 89 ns With PLL enabled 42 5 57 5 duty cycle6 3 54 ns 157 0 µs 3 EXTAL input low1 2 With PLL disabled 46 7 53 3 duty cycle6 ETL 3 89 ns With PLL enabled 42 5 57 5 duty cycle6 3 54 ns 157 0 µs 4 EXTAL cycle time2 With PLL disabled ETC 8 33 ns With PLL enabled 8 33 ns 273 1 µs 7 Instruc...

Page 74: ...wer operating frequencies therefore when a lower clock frequency is used the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met Table 3 6 PLL Characteristics Characteristics Min Max Unit VCO frequency when PLL enabled MF Ef 2 PDF 30 240 MHz PLL external capacitor PCAP pin to VCCP CPCAP 1 pF MF 4 MF 580 100 MF 780 140 MF 4 MF 83...

Page 75: ...p time 30 0 ns 14 Mode select hold time 0 0 ns 15 Minimum edge triggered interrupt request assertion width 5 5 ns 16 Minimum edge triggered interrupt request deassertion width 5 5 ns 17 Delay from IRQA IRQB IRQC IRQD NMI assertion to external memory access address out valid Caused by first interrupt instruction fetch 4 25 TC 2 0 37 4 ns Caused by first interrupt instruction execution 7 25 TC 2 0 6...

Page 76: ...MR Bit 6 0 PLC ETC PDF 128 K PLC 2 TC ms PLL is not active during Stop PCTL Bit 17 0 and Stop delay is not enabled OMR Bit 6 1 PLC ETC PDF 23 75 0 5 TC ms PLL is active during Stop PCTL Bit 17 1 Implies No Stop Delay 8 25 0 5 TC 64 6 72 9 ns 26 Duration of level sensitive IRQA assertion to ensure interrupt service when exiting Stop 2 3 PLL is not active during Stop PCTL Bit 17 0 and Stop delay is ...

Page 77: ...ns DMA 8TC 66 7 ns IRQ NMI edge trigger 8TC 66 7 ns IRQ level trigger 12TC 100 0 ns 28 DMA Requests Rate Data read from HDI08 ESAI ESAI_1 SHI DAX 6TC 50 0 ns Data write to HDI08 ESAI ESAI_1 SHI DAX 7TC 58 0 ns Timer 2TC 16 7 IRQ NMI edge trigger 3TC 25 0 ns Table 3 7 Reset Stop Mode Select and Interrupt Timing No Characteristics Expression Min Max Unit ...

Page 78: ...allel with the stop delay counter and stop recovery will end when the last of these two events occurs the stop delay counter completes count or PLL lock procedure completion PLC value for PLL disable is 0 The maximum value for ETC is 4096 maximum MF divided by the desired internal frequency i e for 150 MHz it is 4096 150 MHz 27 3 µs During the stabilization period TC TH and TL will not be constant...

Page 79: ...Specifications Reset Stop Mode Select and Interrupt Timing MOTOROLA DSP56367 3 13 Figure 3 2 Reset Timing VIH RESET Reset Value First Fetch All Pins A0 A17 8 9 10 AA0460 ...

Page 80: ...nd Interrupt Timing Figure 3 3 External Fast Interrupt Timing A0 A17 RD a First Interrupt Instruction Execution General Purpose I O IRQA IRQB IRQC IRQD NMI b General Purpose I O IRQA IRQB IRQC IRQD NMI WR 20 21 19 17 18 First Interrupt Instruction Execution Fetch ...

Page 81: ...egative Edge Triggered Figure 3 5 Operating Mode Select Timing Figure 3 6 Recovery from Stop State Using IRQA Interrupt Service IRQA IRQB IRQC IRQD NMI IRQA IRQB IRQC IRQD NMI 15 16 AA0463 RESET MODA MODB MODC MODD PINIT VIH IRQA IRQB IRQD NMI VIH VIL VIH VIL 13 14 AA0465 First Instruction Fetch IRQA A0 A17 24 25 AA0466 ...

Page 82: ...Figure 3 7 Recovery from Stop State Using IRQA Interrupt Service Figure 3 8 External Memory Access DMA Source Timing IRQA A0 A17 First IRQA Interrupt Instruction Fetch 26 25 AA0467 29 DMA Source Address First Interrupt Instruction Execution A0 A17 RD WR IRQA IRQB IRQC IRQD NMI AA110 ...

Page 83: ...S 2 TC 4 0 4 WS 7 46 0 ns WS 3 TC 4 0 WS 8 87 0 ns 101 Address and AA valid to WR assertion tAS 0 25 TC 2 0 WS 1 0 1 ns 1 25 TC 2 0 WS 4 8 4 ns 102 WR assertion pulse width tWP 1 5 TC 4 0 WS 1 8 5 ns All frequencies WS TC 4 0 2 WS 3 12 7 ns WS 0 5 TC WS 4 19 0 ns 103 WR deassertion to address not valid tWR 0 25 TC 2 0 1 WS 3 0 1 ns 1 25 TC 2 0 4 WS 7 8 4 ns 2 25 TC WS 8 14 7 ns All frequencies 1 7...

Page 84: ... ns 109 Data hold time from WR deassertion tDH 0 25 TC 2 0 1 WS 3 0 1 ns 1 25 TC 2 0 4 WS 7 8 4 ns 2 25 TC 2 0 WS 8 16 7 ns 110 WR assertion to data active 0 75 TC 3 7 WS 1 2 5 ns 0 25 TC 3 7 2 WS 3 0 0 0 25 TC 3 7 WS 4 0 0 111 WR deassertion to data high impedance 0 25 TC 0 2 1 WS 3 2 3 ns 1 25 TC 0 2 4 WS 7 10 6 2 25 TC 0 2 WS 8 18 9 112 Previous RD deassertion to data active write 1 25 TC 4 0 1...

Page 85: ... deassertion to address not valid 0 25 TC 2 0 1 WS 3 0 1 ns 1 25 TC 2 0 4 WS 7 8 4 ns 2 25 TC 2 0 WS 8 16 7 ns 118 TA setup before RD or WR deassertion4 0 25 TC 2 0 4 1 ns 119 TA hold after RD or WR deassertion 0 0 ns Note 1 WS is the number of wait states specified in the BCR 2 Timings 100 107 are guaranteed by design not tested 3 All timings for 100 MHz are measured from 0 5 Vcc to 05 Vcc 4 In t...

Page 86: ...3 20 DSP56367 MOTOROLA Specifications External Memory Expansion Port Port A Figure 3 9 SRAM Read Access A0 A17 RD WR D0 D23 AA0 AA2 115 105 106 113 104 116 117 100 AA0468 TA 119 Data In 118 ...

Page 87: ...Specifications External Memory Expansion Port Port A MOTOROLA DSP56367 3 21 Figure 3 10 SRAM Write Access A0 A17 WR RD Data Out D0 D23 AA0 AA2 100 102 101 107 114 108 109 103 TA 119 118 ...

Page 88: ...appropriate table a designer may choose to evaluate whether fewer wait states might be used by determining which timing prevents operation at 100 MHz running the chip at a slightly lower frequency e g 95 MHz using faster DRAM if it becomes available and control factors such as capacitive and resistive load to improve overall system performance Figure 3 11 DRAM Page Mode Wait States Selection Guide...

Page 89: ...Previous CAS deassertion to RAS deassertion tRHCP 2 TC 4 0 96 0 62 7 ns 137 CAS assertion pulse width tCAS 0 75 TC 4 0 33 5 21 0 ns 138 Last CAS deassertion to RAS deassertion4 BRW 1 0 00 tCRP 1 75 TC 6 0 81 5 52 3 ns BRW 1 0 01 3 25 TC 6 0 156 5 102 2 ns BRW 1 0 10 4 25 TC 6 0 206 5 135 5 ns BRW 1 0 11 6 25 TC 6 0 306 5 202 1 ns 139 CAS deassertion pulse width tCP 0 5 TC 4 0 21 0 12 7 ns 140 Colu...

Page 90: ...e DCR 2 The refresh period is specified in the DCR 3 All the timings are calculated for the worst case Some of the timings are better for specific cases e g tPC equals 2 TC for read after read or write after write sequences 4 BRW 1 0 DRAM control register bits defines the number of wait states that should be inserted in each DRAM out of page access 5 RD deassertion will always occur after CAS deas...

Page 91: ... Last CAS deassertion to RAS deassertion5 BRW 1 0 00 tCRP 2 0 TC 6 0 24 4 19 0 ns BRW 1 0 01 3 5 TC 6 0 47 2 37 8 ns BRW 1 0 10 4 5 TC 6 0 62 4 50 3 ns BRW 1 0 11 6 5 TC 6 0 92 8 75 3 ns 139 CAS deassertion pulse width tCP 1 25 TC 4 0 14 9 11 6 ns 140 Column address valid to CAS assertion tASC TC 4 0 11 2 8 5 ns 141 CAS assertion to column address not valid tCAH 1 75 TC 4 0 22 5 17 9 ns 142 Last c...

Page 92: ...WR assertion to data active 0 75 TC 0 3 11 1 9 1 ns 156 WR deassertion to data high impedance 0 25 TC 3 8 3 1 ns Note 1 The number of wait states for Page mode access is specified in the DCR 2 The refresh period is specified in the DCR 3 The asynchronous delays specified in the expressions are valid for DSP56367 4 All the timings are calculated for the worst case Some of the timings are better for...

Page 93: ...sertion pulse width tCAS 2 TC 4 0 16 0 ns 138 Last CAS deassertion to RAS assertion5 BRW 1 0 00 tCRP 2 25 TC 6 0 ns BRW 1 0 01 3 75 TC 6 0 ns BRW 1 0 10 4 75 TC 6 0 41 5 ns BRW 1 0 11 6 75 TC 6 0 61 5 ns 139 CAS deassertion pulse width tCP 1 5 TC 4 0 11 0 ns 140 Column address valid to CAS assertion tASC TC 4 0 6 0 ns 141 CAS assertion to column address not valid tCAH 2 5 TC 4 0 21 0 ns 142 Last c...

Page 94: ...it states for Page mode access is specified in the DCR 2 The refresh period is specified in the DCR 3 The asynchronous delays specified in the expressions are valid for DSP56367 4 All the timings are calculated for the worst case Some of the timings are better for specific cases e g tPC equals 4 TC for read after read or write after write sequences 5 BRW 1 0 DRAM control register bits defines the ...

Page 95: ...assertion to RAS assertion5 BRW 1 0 00 tCRP 2 75 TC 6 0 ns BRW 1 0 01 4 25 TC 6 0 BRW 1 0 10 5 25 TC 6 0 37 7 BRW 1 0 11 7 25 TC 6 0 54 4 139 CAS deassertion pulse width tCP 2 TC 4 0 12 7 ns 140 Column address valid to CAS assertion tASC TC 4 0 4 3 ns 141 CAS assertion to column address not valid tCAH 3 5 TC 4 0 25 2 ns 142 Last column address valid to RAS deassertion tRAL 5 TC 4 0 37 7 ns 143 WR ...

Page 96: ...The refresh period is specified in the DCR 3 The asynchronous delays specified in the expressions are valid for DSP56367 4 All the timings are calculated for the worst case Some of the timings are better for specific cases e g tPC equals 3 TC for read after read or write after write sequences 5 BRW 1 0 DRAM control register bits defines the number of wait states that should be inserted in each DRA...

Page 97: ...OLA DSP56367 3 31 Figure 3 12 DRAM Page Mode Write Accesses RAS CAS A0 A17 WR RD D0 D23 Column Row Data Out Data Out Data Out Last Column Column Add Address Address Address 136 135 131 139 141 137 140 142 147 144 151 148 146 155 156 150 138 145 143 149 AA0473 ...

Page 98: ...emory Expansion Port Port A Figure 3 13 DRAM Page Mode Read Accesses RAS CAS A0 A17 WR RD D0 D23 Column Last Column Column Row Data In Data In Data In Add Address Address Address 136 135 131 137 140 141 142 143 152 133 153 132 138 139 134 154 AA0474 ...

Page 99: ... valid read tRAC 2 75 TC 7 5 130 0 84 2 ns 159 CAS assertion to data valid read tCAC 1 25 TC 7 5 55 0 34 2 ns 160 Column address valid to data valid read tAA 1 5 TC 7 5 67 5 42 5 ns 161 CAS deassertion to data not valid read hold time tOFF 0 0 0 0 ns 162 RAS deassertion to RAS assertion tRP 1 75 TC 4 0 83 5 54 3 ns Chip Frequency MHz DRAM Type tRAC ns 100 80 70 50 66 80 100 4 Wait States 8 Wait St...

Page 100: ...s not valid tCAH 1 75 TC 4 0 83 5 54 3 ns 175 RAS assertion to column address not valid tAR 3 25 TC 4 0 158 5 104 3 ns 176 Column address valid to RAS deassertion tRAL 2 TC 4 0 96 0 62 7 ns 177 WR deassertion to CAS assertion tRCS 1 5 TC 3 8 71 2 46 2 ns 178 CAS deassertion to WR assertion tRCH 0 75 TC 3 7 33 8 21 3 ns 179 RAS deassertion to WR assertion tRRH 0 25 TC 3 7 8 8 4 6 ns 180 CAS asserti...

Page 101: ... in the DCR 2 The refresh period is specified in the DCR 3 RD deassertion will always occur after CAS deassertion therefore the restricted timing is tOFF and not tGZ 4 Reduced DSP clock speed allows use of DRAM out of page access with four Wait states See Figure 2 17 Table 3 14 DRAM Out of Page and Refresh Timings Eight Wait States No Characteristics4 Symbol Expression3 66 MHz 80 MHz Unit Min Max ...

Page 102: ... 4 0 37 7 30 4 ns 171 Row address valid to RAS assertion tASR 3 25 TC 4 0 45 2 36 6 ns 172 RAS assertion to row address not valid tRAH 1 75 TC 4 0 22 5 17 9 ns 173 Column address valid to CAS assertion tASC 0 75 TC 4 0 7 4 5 4 ns 174 CAS assertion to column address not valid tCAH 3 25 TC 4 0 45 2 36 6 ns 175 RAS assertion to column address not valid tAR 5 75 TC 4 0 83 1 67 9 ns 176 Column address ...

Page 103: ...resh tRPC 1 75 TC 4 0 22 5 17 9 ns 191 RD assertion to RAS deassertion tROH 8 5 TC 4 0 124 8 102 3 ns 192 RD assertion to data valid tGA 7 5 TC 7 5 106 1 ns 7 5 TC 6 5 87 3 ns 193 RD deassertion to data not valid4 tGZ 0 0 0 0 0 0 ns 194 WR assertion to data active 0 75 TC 0 3 11 1 9 1 ns 195 WR deassertion to data high impedance 0 25 TC 3 8 3 1 ns Note 1 The number of wait states for out of page a...

Page 104: ...AS assertion to CAS assertion tRCD 2 5 TC 4 0 21 0 29 0 ns 168 RAS assertion to column address valid tRAD 1 75 TC 4 0 13 5 21 5 ns 169 CAS deassertion to RAS assertion tCRP 5 75 TC 4 0 53 5 ns 170 CAS deassertion pulse width tCP 4 25 TC 4 0 38 5 ns 171 Row address valid to RAS assertion tASR 4 25 TC 4 0 38 5 ns 172 RAS assertion to row address not valid tRAH 1 75 TC 4 0 13 5 ns 173 Column address ...

Page 105: ...94 WR assertion to data active 0 75 TC 0 3 7 2 ns 195 WR deassertion to data high impedance 0 25 TC 2 5 ns Note 1 The number of wait states for out of page access is specified in the DCR 2 The refresh period is specified in the DCR 3 The asynchronous delays specified in the expressions are valid for DSP56367 4 RD deassertion will always occur after CAS deassertion therefore the restricted timing i...

Page 106: ...w address not valid tRAH 2 75 TC 4 0 18 9 ns 173 Column address valid to CAS assertion tASC 0 75 TC 4 0 2 2 ns 174 CAS assertion to column address not valid tCAH 6 25 TC 4 0 48 1 ns 175 RAS assertion to column address not valid tAR 9 75 TC 4 0 77 2 ns 176 Column address valid to RAS deassertion tRAL 7 TC 4 0 54 3 ns 177 WR deassertion to CAS assertion tRCS 5 TC 3 8 37 9 ns 178 CAS deassertion to W...

Page 107: ...H 15 5 TC 4 0 125 2 ns 192 RD assertion to data valid tGA 14 TC 5 7 111 0 ns 193 RD deassertion to data not valid3 tGZ 0 0 ns 194 WR assertion to data active 0 75 TC 0 3 5 9 ns 195 WR deassertion to data high impedance 0 25 TC 2 1 ns Note 1 The number of wait states for out of page access is specified in the DCR 2 The refresh period is specified in the DCR 3 RD deassertion will always occur after ...

Page 108: ... Memory Expansion Port Port A Figure 3 15 DRAM Out of Page Read Access RAS CAS A0 A17 WR RD D0 D23 Data Row Address Column Address In 157 163 165 162 162 169 170 171 168 167 164 166 173 174 175 172 177 176 191 160 168 159 193 161 192 158 179 AA0476 ...

Page 109: ...t A MOTOROLA DSP56367 3 43 Figure 3 16 DRAM Out of Page Write Access RAS CAS A0 A17 WR RD D0 D23 Data Out Column Address Row Address 162 163 165 162 157 169 170 167 168 164 166 171 173 174 176 172 181 175 180 188 182 184 183 187 185 194 186 195 AA0477 ...

Page 110: ...3 44 DSP56367 MOTOROLA Specifications External Memory Expansion Port Port A Figure 3 17 DRAM Refresh Access RAS CAS WR 157 163 162 162 190 170 165 189 177 AA0478 ...

Page 111: ...ndow from BG input negation 2 5 Tc 5 25 8 ns 251 Delay from BB assertion to BG assertion 2 Tc 5 21 7 ns Note 1 Bit 13 in the OMR register must be set to enter Asynchronous Arbitration mode 2 If Asynchronous Arbitration mode is active none of the timings in Table 3 17 is required 3 In order to guarantee timings 250 and 251 it is recommended to assert BG inputs to different 56300 devices on the same...

Page 112: ...synchronization delay from BB assertion to the time this assertion is exposed to other 56300 components which are potential masters on the same bus If BG input is asserted before that time a situation of BG asserted and BB negated may cause another 56300 component to assume mastership at the same time Therefore some non overlap period between one BG input active to another BG input active is requi...

Page 113: ...put setup time before HACK write deassertion 9 9 ns 325 Host data input hold time after write data strobe deassertion 8 Host data input hold time after HACK write deassertion 3 3 ns 326 Read data strobe assertion to output data active from high impedance 4 HACK read assertion to output data active from high impedance 3 3 ns 327 Read data strobe assertion to output data valid 4 HACK read assertion ...

Page 114: ...request assertion for Last Data Register write 5 8 10 2 TC 16 7 ns 340 Delay from data strobe assertion to host request deassertion for Last Data Register read or write HROD 0 5 9 10 19 1 ns 341 Delay from data strobe assertion to host request deassertion for Last Data Register read or write HROD 1 open drain Host Request 5 9 10 11 300 0 ns 342 Delay from DMA HACK deassertion to HOREQ assertion ns...

Page 115: ...r is followed by a read from the RXL RXM or RXH registers without first polling RXDF or HREQ bits or waiting for the assertion of the HOREQ signal 7 This timing is applicable only if two consecutive reads from one of these registers are executed 8 The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode 9 The data strobe is host read HRD or host write HWR in...

Page 116: ...ROLA Specifications Parallel Host Interface HDI08 Timing Figure 3 21 Read Timing Diagram Non Multiplexed Bus HRD HDS HA0 HA2 HCS HD0 HD7 HOREQ 327 332 319 318 317 330 329 337 336 328 326 338 341 340 333 AA0484 HRRQ HTRQ ...

Page 117: ...ions Parallel Host Interface HDI08 Timing MOTOROLA DSP56367 3 51 Figure 3 22 Write Timing Diagram Non Multiplexed Bus HWR HDS HA0 HA2 HCS HD0 HD7 HOREQ HRRQ HTRQ 336 331 337 321 320 324 325 339 340 341 333 AA0485 ...

Page 118: ...cifications Parallel Host Interface HDI08 Timing Figure 3 23 Read Timing Diagram Multiplexed Bus HRD HDS HA8 HA10 HAS HAD0 HAD7 HOREQ HRRQ HTRQ Address Data 317 318 319 328 329 327 326 335 336 337 334 341 340 338 323 AA0486 322 ...

Page 119: ...allel Host Interface HDI08 Timing MOTOROLA DSP56367 3 53 Figure 3 24 Write Timing Diagram Multiplexed Bus HWR HDS HA8 HA10 HOREQ HRRQ HTRQ HAS HAD0 HAD7 Address Data 320 321 325 324 335 341 339 336 334 340 322 323 AA0487 ...

Page 120: ...iming Figure 3 25 Host DMA Write Timing Diagram Figure 3 26 Host DMA Read Timing Diagram HOREQ Output HACK Input H0 H7 Input Data Valid TXH M L Write 320 321 343 342 324 344 325 326 317 318 327 328 329 Data Valid HOREQ Output HACK Input H0 H7 Output RXH Read 343 342 342 ...

Page 121: ... tSPICC min Maste r Bypassed 6 TC 46 96 ns Narrow 6 TC 152 202 ns Wide 6 TC 223 273 ns 142 Serial clock high period Maste r Bypassed 0 5 tSPICC 10 38 ns Narrow 0 5 tSPICC 10 91 ns Wide 0 5 tSPICC 10 126 5 ns Slave Bypassed 2 5 TC 12 32 8 ns Narrow 2 5 TC 102 122 8 ns Wide 2 5 TC 189 209 8 ns 143 Serial clock low period Maste r Bypassed 0 5 tSPICC 10 38 ns Narrow 0 5 tSPICC 10 91 ns Wide 0 5 tSPICC...

Page 122: ...mpling edge to data input not valid Maste r Slav e Bypassed 2 5 TC 10 30 8 ns Narrow 2 5 TC 30 50 8 ns Wide 2 5 TC 50 70 8 ns 150 SS assertion to data out active Slave 2 2 ns 151 SS deassertion to data high impedance2 Slave 9 9 ns 152 SCK edge to data out valid data out delay time Maste r Slav e Bypassed 2 TC 33 49 7 ns Narrow 2 TC 123 139 7 ns Wide 2 TC 210 226 7 ns 153 SCK edge to data out not v...

Page 123: ...CPHA 0 Slave 2 5 TC 30 50 8 ns 160 SS deassertion pulse width CPHA 0 Slave TC 6 14 3 ns 161 HREQ in assertion to first SCK edge Maste r Bypassed 0 5 tSPICC 2 5 TC 43 111 8 ns Narrow 0 5 tSPICC 2 5 TC 43 164 8 ns Wide 0 5 tSPICC 2 5 TC 43 200 3 ns 162 HREQ in deassertion to last SCK sampling edge HREQ in set up time CPHA 1 Maste r 0 0 ns 163 First SCK edge to HREQ in not asserted HREQ in hold time ...

Page 124: ...Interface SPI Protocol Timing Figure 3 27 SPI Master Timing CPHA 0 SS Input SCK CPOL 0 Output SCK CPOL 1 Output MISO Input Valid MOSI Output MSB Valid LSB MSB LSB HREQ Input 141 142 143 144 144 141 144 144 143 142 148 149 149 148 152 153 163 161 AA027 ...

Page 125: ...ming MOTOROLA DSP56367 3 59 Figure 3 28 SPI Master Timing CPHA 1 SS Input SCK CPOL 0 Output SCK CPOL 1 Output MISO Input Valid MOSI Output MSB Valid LSB MSB LSB HREQ Input 141 142 143 144 144 141 144 144 143 142 148 148 149 152 153 163 161 162 149 AA0272 ...

Page 126: ... Protocol Timing Figure 3 29 SPI Slave Timing CPHA 0 SS Input SCK CPOL 0 Input SCK CPOL 1 Input MISO Output MOSI Input MSB LSB MSB LSB HREQ Output 141 142 143 144 144 141 144 144 143 142 154 150 152 153 148 149 159 157 153 151 Valid Valid 148 149 147 160 146 AA027 ...

Page 127: ...MOTOROLA DSP56367 3 61 Figure 3 30 SPI Slave Timing CPHA 1 SS Input SCK CPOL 0 Input SCK CPOL 1 Input MISO Output MOSI Input MSB LSB MSB LSB HREQ Output 141 142 143 144 144 144 144 143 142 150 152 148 149 158 153 151 Valid Valid 148 147 146 152 149 157 AA027 ...

Page 128: ...me THD STA 4 0 0 6 µs 175 SCL low period TLOW 4 7 1 3 µs 176 SCL high period THIGH 4 0 1 3 µs 177 SCL and SDA rise time TR 1000 20 0 1 Cb 300 ns 178 SCL and SDA fall time TF 300 20 0 1 Cb 300 ns 179 Data set up time TSU DAT 250 100 ns 180 Data hold time THD DAT 0 0 0 0 0 9 µs 181 DSP clock frequency FDSP Filters bypassed 10 6 28 5 MHz Narrow filters enabled 11 8 39 7 MHz Wide filters enabled 13 1 ...

Page 129: ...l clock cycle from 187 Last SCL edge to HREQ output not deasserted TAS RQO ns Filters bypassed 2 TC 30 46 7 46 7 Narrow filters enabled 2 TC 80 96 7 96 7 Wide filters enabled 2 TC 135 151 6 151 6 188 HREQ in assertion to first SCL edge TAS RQI 0 5 TI2CCP 0 5 TC 21 ns Filters bypassed 4440 1041 Narrow filters enabled 4373 999 Wide filters enabled 4373 958 189 First SCL edge to HREQ in not asserted ...

Page 130: ...8 33ns operating in a standard mode I2 C environment FSCL 100 kHz i e TSCL 10µs TR 1000ns with wide filters enabled TI 2 CCP 10µs 2 5 8 33ns 223ns 1000ns 8756ns Choosing HRS 0 gives HDM 7 0 8756ns 2 8 33ns 8 1 64 67 Thus the HDM 7 0 value should be programmed to 41 65 The resulting TI 2 CCP will be TI2CCP TC 2 HDM 7 0 1 7 1 HRS 1 TI2CCP 8 33ns 2 65 1 7 1 0 1 TI2CCP 8 33ns 2 66 8 8796 48ns Table 3 ...

Page 131: ...ions Serial Host Interface SHI I2C Protocol Timing MOTOROLA DSP56367 3 65 Figure 3 31 I2C Timing Start SCL HREQ SDA ACK MSB LSB Stop 171 Stop 173 176 175 177 178 180 179 172 186 182 183 189 174 188 184 187 AA027 ...

Page 132: ... out bl high 37 0 22 0 x ck i ck a ns 434 RXC rising edge to FSR out bl low 37 0 22 0 x ck i ck a ns 435 RXC rising edge to FSR out wr high6 39 0 24 0 x ck i ck a ns 436 RXC rising edge to FSR out wr low6 39 0 24 0 x ck i ck a ns 437 RXC rising edge to FSR out wl high 36 0 21 0 x ck i ck a ns 438 RXC rising edge to FSR out wl low 37 0 22 0 x ck i ck a ns 439 Data in setup time before RXC SCK in sy...

Page 133: ...m high impedance 31 0 17 0 x ck i ck ns 453 TXC rising edge to transmitter 0 drive enable assertion 34 0 20 0 x ck i ck ns 454 TXC rising edge to data out valid 23 0 5 TC 21 0 27 2 21 0 x ck i ck ns 455 TXC rising edge to data out high impedance7 31 0 16 0 x ck i ck ns 456 TXC rising edge to transmitter 0 drive enable deassertion7 34 0 20 0 x ck i ck ns 457 FST input bl wr setup time before TXC fa...

Page 134: ...ord length relative 4 TXC SCKT pin transmit clock RXC SCKR pin receive clock FST FST pin transmit frame sync FSR FSR pin receive frame sync HCKT HCKT pin transmit high frequency clock HCKR HCKR pin receive high frequency clock 5 For the internal clock the external clock cycle is defined by Icyc and the ESAI control register 6 The word relative frame sync signal waveform relative to the clock opera...

Page 135: ...t FST Word Out Data Out Transmitter 0 Drive Enable FST Bit In FST Word In Flags Out Note In network mode output flag transitions can occur at the start of each time slot within the frame In normal mode the output flag state is asserted for the entire frame period First Bit 430 432 446 447 450 451 455 454 454 452 459 456 453 461 457 458 460 461 462 431 AA0490 ...

Page 136: ...Enhanced Serial Audio Interface Timing Figure 3 33 ESAI Receiver Timing RXC Input Output FSR Bit Out FSR Word Out Data In FSR Bit In FSR Word In Flags In Last Bit First Bit 430 432 433 437 438 440 439 443 441 442 443 445 444 431 434 AA0491 ...

Page 137: ...Specifications Enhanced Serial Audio Interface Timing MOTOROLA DSP56367 3 71 Figure 3 34 ESAI HCKT Timing Figure 3 35 ESAI HCKR Timing HCKT SCKT output 464 463 HCKR SCKR output 465 463 ...

Page 138: ...frequency see note 1 2 x TC 60 MHz 220 ACI period 2 TC 16 7 ns 221 ACI high duration 0 5 TC 4 2 ns 222 ACI low duration 0 5 TC 4 2 ns 223 ACI rising edge to ADO valid 1 5 TC 12 5 ns Note In order to assure proper operation of the DAX the ACI frequency should be less than 1 2 of the DSP56367 internal clock frequency For example if the DSP56367 is running at 150 MHz internally the ACI frequency shou...

Page 139: ...MER TIMING Figure 3 37 TIO Timer Event Input Restrictions Table 3 24 Timer Timing No Characteristics Expression 120 MHz Uni t Mi n Ma x 480 TIO Low 2 TC 2 0 18 7 ns 481 TIO High 2 TC 2 0 18 7 ns Note VCC 1 8 V 0 09 V TJ 0 C to 95 C CL 50 pF TIO 481 480 AA0492 ...

Page 140: ...0 2 ns 493 EXTAL edge to GPIO in not valid GPIO in hold time 1 8 ns 4942 Fetch to EXTAL edge before GPIO change 6 75 TC 1 8 54 5 ns 495 GPIO out rise time 13 ns 496 GPIO out fall time 13 ns Note 1 VCC 1 8 V 0 09 V TJ 0 C to 95 C CL 50 pF 2 Valid only when PLL enabled with multiplication factor equal to one Valid GPIO Input GPIO Output EXTAL Input Fetch the instruction MOVE X0 X R0 X0 contains the ...

Page 141: ...CK rise and fall times 0 0 3 0 ns 504 Boundary scan input data setup time 5 0 ns 505 Boundary scan input data hold time 24 0 ns 506 TCK low to output data valid 0 0 40 0 ns 507 TCK low to output high impedance 0 0 40 0 ns 508 TMS TDI data setup time 5 0 ns 509 TMS TDI data hold time 25 0 ns 510 TCK low to TDO data valid 0 0 44 0 ns 511 TCK low to TDO high impedance 0 0 44 0 ns Note 1 VCC 1 8 V 0 0...

Page 142: ...ess Port Timing Diagram TCK Input Data Inputs Data Outputs Data Outputs Data Outputs VIH VIL Input Data Valid Output Data Valid Output Data Valid 505 504 506 507 506 AA0497 TCK Input TDI Input TDO Output TDO Output TDO Output VIH VIL Input Data Valid Output Data Valid Output Data Valid TMS 508 509 510 511 510 AA0498 ...

Page 143: ...r example the user can change the air flow around the device add a heat sink change the mounting arrangement on the printed circuit board PCB or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB This model is most useful for ceramic packages with heat sinks some 90 of the heat flow is dissipated through the case to the heat sink and out to the ambient ...

Page 144: ...in this data sheet are determined using the first definition From a practical standpoint that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments In natural convection using the junction to case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a jun...

Page 145: ...RQD and TA pins Maximum PCB trace lengths on the order of 15 cm 6 inches are recommended Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits All inputs must be terminated i e not allowed to float using CMOS...

Page 146: ...e following formula where C node pin capacitance V voltage swing f frequency of node pin toggle The maximum internal current ICCImax value reflects the typical possible switching of the internal buses on best case operation conditions which is not necessarily a real application case The typical internal current ICCItyp value reflects the average switching of the internal buses on typical operating...

Page 147: ... example F2 could be 66 MHz and F1 could be 33 MHz The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application 4 4 PLL PERFORMANCE ISSUES The following explanations should be considered as general observations on expected PLL behavior There is no testing that verifies these exact numbers These observations were me...

Page 148: ...4 6 DSP56367 MOTOROLA Design Considerations PLL Performance Issues ...

Page 149: ...the CE Cache Enable MSW0 MSW1 and MS Memory Switch control bits in the OMR register and by the SC bit in the Status Register The internal data and program memory configurations are shown in Table 5 1 The address ranges for the internal memory are shown in Table 5 2 and Table 5 3 The memory maps for each memory configuration are shown in Figure 5 1 to Figure 5 16 ...

Page 150: ...7K 1K 40K 192 8K 7K 32K 8K 1 0 1 1 0 4K 1K 40K 192 11K 7K 32K 8K X X 0 0 1 3K n a n a n a 13K 7K 32K 8K X X 1 0 1 2K 1K n a n a 13K 7K 32K 8K 0 0 0 1 1 10K n a n a n a 8K 5K 32K 8K 0 1 0 1 1 8K n a n a n a 8K 7K 32K 8K 1 0 0 1 1 5K n a n a n a 11K 7K 32K 8K 0 0 1 1 1 9K 1K n a n a 8K 5K 32K 8K 0 1 1 1 1 7K 1K n a n a 8K 7K 32K 8K 1 0 1 1 1 4K 1K n a n a 11K 7K 32K 8K Table 5 2 On chip RAM Memory L...

Page 151: ... 1 X 0000 0FFF enabled 0000 2BFF 0000 1BFF Table 5 3 On chip ROM Memory Locations Bit Settings ROM Memory Locations MSW1 MSW0 CE MS SC Prog ROM Boot ROM X Data ROM Y Data ROM X X X X 0 FF1000 FFAFFF FF0000 FF00BF 004000 00BFFF 004000 005FFF X X X X 1 no access no access 004000 00BFFF 004000 005FFF Table 5 2 On chip RAM Memory Locations Bit Settings RAM Memory Locations MSW1 MSW0 CE MS SC Prog RAM ...

Page 152: ...AL RAM EXTERNAL I O 80 words 006000 004000 ROM 8K INTERNAL INT RESERVED EXTERNAL FF0000 INTERNAL RESERVED FFF000 FFFF80 EXTERNAL FFFFB0 INTERNAL I O 48 words 004000 INT RESERVED PROGRAM FFFFFF 000000 000800 2K INTERNAL RAM X DATA FFFFFF 000000 003400 13K INTERNAL RAM INTERNAL I O Y DATA FF1000 FFFF80 40K INTERNAL ROM FFB000 128 words 00C000 ROM 32K INTERNAL INTERNAL EXTERNAL BOOT ROM FF0000 FF00C0...

Page 153: ...EXTERNAL I O 80 words 006000 004000 ROM 8K INTERNAL INT RESERVED EXTERNAL FF0000 INTERNAL RESERVED FFF000 FFFF80 EXTERNAL FFFFB0 INTERNAL I O 48 words 004000 INT RESERVED PROGRAM FFFFFF 000000 001C00 7K INTERNAL RAM X DATA FFFFFF 000000 002000 8K INTERNAL RAM INTERNAL I O Y DATA FF1000 FFFF80 40K INTERNAL ROM FFB000 128 words 00C000 ROM 32K INTERNAL INTERNAL BOOT ROM FF0000 FF00C0 RESERVED INTERNA...

Page 154: ...ds 006000 004000 ROM 8K INTERNAL INT RESERVED EXTERNAL FF0000 INTERNAL RESERVED FFF000 FFFF80 EXTERNAL FFFFB0 INTERNAL I O 48 words 004000 INT RESERVED INT RESERVED 002400 EXTERNAL 1K RAM 002800 PROGRAM FFFFFF 000000 002400 9K INTERNAL RAM X DATA FFFFFF 000000 002000 8K INTERNAL RAM INTERNAL I O Y DATA FF1000 FFFF80 40K INTERNAL ROM FFB000 128 words 00C000 ROM 32K INTERNAL INTERNAL EXTERNAL BOOT R...

Page 155: ...06000 004000 ROM 8K INTERNAL INT RESERVED EXTERNAL FF0000 INTERNAL RESERVED FFF000 FFFF80 EXTERNAL FFFFB0 INTERNAL I O 48 words 004000 INT RESERVED INT RESERVED 002400 1K I CACHE ENABLED PROGRAM FFFFFF 000000 001000 4K INTERNAL RAM X DATA FFFFFF 000000 002C00 11K INTERNAL RAM INTERNAL I O Y DATA FF1000 FFFF80 40K INTERNAL ROM FFB000 128 words 00C000 ROM 32K INTERNAL INTERNAL EXTERNAL BOOT ROM FF00...

Page 156: ... INTERNAL EXTERNAL EXTERNAL FFFF 0000 1C00 7K INTERNAL RAM EXTERNAL I O FFB0 82 words 6000 4000 ROM 8K INTERNAL INT RESERVED EXTERNAL INTERNAL I O 46 words FF80 4000 INT RESERVED PROGRAM FFFF 0000 0800 2K INTERNAL RAM X DATA FFFF 0000 3400 13K INTERNAL RAM INTERNAL I O Y DATA FF80 128 words C000 ROM 32K INTERNAL EXTERNAL EXTERNAL FFFF 0000 1C00 7K INTERNAL RAM EXTERNAL I O FFB0 80 words 6000 4000 ...

Page 157: ...RNAL EXTERNAL EXTERNAL FFFF 0000 1400 5K INTERNAL RAM EXTERNAL I O FFB0 80 words 6000 4000 ROM 8K INTERNAL INT RESERVED EXTERNAL INTERNAL I O 48words FF80 INT RESERVED 4000 PROGRAM FFFF 0000 1C00 7K INTERNAL RAM X DATA FFFF 0000 2000 8K INTERNAL RAM INTERNAL I O Y DATA FF80 128 words C000 ROM 32K INTERNAL EXTERNAL EXTERNAL FFFF 0000 1C00 7K INTERNAL RAM EXTERNAL I O FFB0 80 words 6000 4000 ROM 8K ...

Page 158: ...EXTERNAL FFFF 0000 1C00 7K INTERNAL RAM EXTERNAL I O FFB0 80 words 6000 4000 ROM 8K INTERNAL INT RESERVED EXTERNAL INTERNAL I O 48 words FF80 INT RESERVED 4000 2400 2800 1000 INT RESERVED 1K RAM PROGRAM FFFF 0000 2400 9K INTERNAL RAM X DATA FFFF 0000 2000 8K INTERNAL RAM INTERNAL I O Y DATA FF80 128 words C000 ROM 32K INTERNAL EXTERNAL EXTERNAL FFFF 0000 1400 5K INTERNAL RAM EXTERNAL I O FFB0 80 w...

Page 159: ...FFFF 0000 1C00 7K INTERNAL RAM EXTERNAL I O FFB0 80 words 6000 4000 ROM 8K INTERNAL INT RESERVED EXTERNAL INTERNAL I O 48 words FF80 INT RESERVED 4000 1K I CACHE ENABLED INT RESERVED 2400 PROGRAM FFFF 0000 4K INTERNAL RAM X DATA FFFF 0000 2C00 11K INTERNAL RAM INTERNAL I O Y DATA FF80 128 words C000 ROM 32K INTERNAL EXTERNAL EXTERNAL FFFF 0000 1C00 7K INTERNAL RAM EXTERNAL I O FFB0 80 words 6000 4...

Page 160: ...ce code in Bootstrap ROM Contents on page Appendix A 1 5 1 4 DYNAMIC MEMORY CONFIGURATION SWITCHING The internal memory configuration is altered by re mapping RAM modules from Y and X data memory into program memory space and vice versa The contents of the switched RAM modules are preserved The memory can be dynamically switched from one configuration to another by changing the MS MSW0 or MSW1 bit...

Page 161: ... condition Special attention should be given when running a memory switch routine using the OnCE port Running the switch routine in Trace mode for example can cause the switch to complete after the MS bit change while the DSP is in Debug mode As a result subsequent instructions might be fetched according to the new memory configuration after the switch and thus might execute improperly 5 1 5 EXTER...

Page 162: ...DRESS ATTRIBUTE REGISTER 3 AAR3 pin not available X FFFFF5 ID REGISTER IDR DMA X FFFFF4 DMA STATUS REGISTER DSTR X FFFFF3 DMA OFFSET REGISTER 0 DOR0 X FFFFF2 DMA OFFSET REGISTER 1 DOR1 X FFFFF1 DMA OFFSET REGISTER 2 DOR2 X FFFFF0 DMA OFFSET REGISTER 3 DOR3 DMA0 X FFFFEF DMA SOURCE ADDRESS REGISTER DSR0 X FFFFEE DMA DESTINATION ADDRESS REGISTER DDR0 X FFFFED DMA COUNTER DCO0 X FFFFEC DMA CONTROL RE...

Page 163: ...X FFFFD0 DAX CONTROL REGISTER XCTR X FFFFCF RESERVED X FFFFCE RESERVED X FFFFCD RESERVED X FFFFCC RESERVED X FFFFCB RESERVED X FFFFCA RESERVED PORT B X FFFFC9 HOST PORT GPIO DATA REGISTER HDR X FFFFC8 HOST PORT GPIO DIRECTION REGISTER HDDR HDI08 X FFFFC7 HOST TRANSMIT REGISTER HOTX X FFFFC6 HOST RECEIVE REGISTER HORX X FFFFC5 HOST BASE ADDRESS REGISTER HBAR X FFFFC4 HOST PORT CONTROL REGISTER HPCR...

Page 164: ...FFFAA ESAI RECEIVE DATA REGISTER 2 RX2 X FFFFA9 ESAI RECEIVE DATA REGISTER 1 RX1 X FFFFA8 ESAI RECEIVE DATA REGISTER 0 RX0 X FFFFA7 RESERVED X FFFFA6 ESAI TIME SLOT REGISTER TSR X FFFFA5 ESAI TRANSMIT DATA REGISTER 5 TX5 X FFFFA4 ESAI TRANSMIT DATA REGISTER 4 TX4 X FFFFA3 ESAI TRANSMIT DATA REGISTER 3 TX3 X FFFFA2 ESAI TRANSMIT DATA REGISTER 2 TX2 X FFFFA1 ESAI TRANSMIT DATA REGISTER 1 TX1 X FFFFA...

Page 165: ... REGISTER TCPR2 X FFFF84 TIMER 2 COUNT REGISTER TCR2 X FFFF83 TIMER PRESCALER LOAD REGISTER TPLR X FFFF82 TIMER PRESCALER COUNT REGISTER TPCR X FFFF81 RESERVED X FFFF80 RESERVED ESAI MUX PIN CONTROL Y FFFFAF MUX PIN CONTROL REGISTER EMUXR Y FFFFAE RESERVED Y FFFFAD RESERVED Y FFFFAC RESERVED Y FFFFAB RESERVED Y FFFFAA RESERVED Y FFFFA9 RESERVED Y FFFFA8 RESERVED Y FFFFA7 RESERVED Y FFFFA6 RESERVED...

Page 166: ...1 STATUS REGISTER SAISR_1 Y FFFF92 RESERVED Y FFFF91 RESERVED Y FFFF90 RESERVED Y FFFF8F RESERVED Y FFFF8E RESERVED Y FFFF8D RESERVED Y FFFF8C RESERVED Y FFFF8B ESAI_1 RECEIVE DATA REGISTER 3 RX3_1 Y FFFF8A ESAI_1 RECEIVE DATA REGISTER 2 RX2_1 Y FFFF89 ESAI_1 RECEIVE DATA REGISTER 1 RX1_1 Y FFFF88 ESAI_1 RECEIVE DATA REGISTER 0 RX0_1 Y FFFF87 RESERVED Y FFFF86 ESAI_1 TIME SLOT REGISTER TSR_1 Y FFF...

Page 167: ...n details specific to the DSP56367 These include the following Operating modes Bootstrap program Interrupt sources and priorities DMA request sources OMR PLL control register AA control registers JTAG BSR For more information on specific registers or modules in the DSP56300 core refer to the DSP56300 Family Manual DSP56300FM AD ...

Page 168: ...usly asserted according to its AAR settings The APD bit is cleared by hardware reset Table 6 1 Operating Mode Register OMR SCS EOM COM 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PEN MSW 1 0 SENWRPEOVEUN XYS ATE APD ABE BRT TAS BE CDP1 0 MS SD EBD MD MC MB MA PEN Patch Enable ATE Address Tracing Enable MS Master memory Switch Mode MSW1 Memory switch mode 1 APD Address Priority Di...

Page 169: ...e contents of the Program ROM This is done by using the Instruction Cache to supply the instruction word instead of the Program ROM The Patch Enable function is activated by setting bit 23 PEN in the OMR Register The PEN bit is cleared by hardware reset The Instruction Cache should be initialized with the new instructions according to the following procedure These steps should be executed from ext...

Page 170: ...nable 1 bset M_PAE omr PatchEnable 1 move 800000 r1 any external address move 128 n1 128 for 1K ICACHE sector size move M_PROMS PATCH_OFSET r2 dup 8 punlock r1 n1 initialize TAGs to different values endm plock r2 lock patch s sector start mid end move PATCH_DATA_START r1 replace ROM code by PATCH do PATCH_DATA_END PATCH_DATA_START 1 PATCH_LOOP movem p r1 x0 movem x0 p r2 nop Do loop restriction PA...

Page 171: ...t Vector Description 0 0 0 0 0 C00000 Expanded mode 1 0 0 0 1 FF0000 Bootstrap from byte wide memory 2 0 0 1 0 FF0000 Jump to PROM starting address 3 0 0 1 1 FF0000 Reserved 4 0 1 0 0 FF0000 Reserved 5 0 1 0 1 FF0000 Bootstrap from SHI slave SPI mode 6 0 1 1 0 FF0000 Bootstrap from SHI slave I2C mode HCKFR 1 100ns filter enabled 7 0 1 1 1 FF0000 Bootstrap from SHI slave I2 C mode HCKR 0 8 1 0 0 0 ...

Page 172: ...p code expects to read a 24 bit word specifying the number of program words a 24 bit word specifying the address to start loading the program words and then a 24 bit word for each program word to be loaded The program words will be stored in contiguous PRAM memory locations starting at the specified starting address After reading the program words program execution starts from the same address whe...

Page 173: ...s The interrupt priority registers are shown in Figure 6 1 and Figure 6 2 The Interrupt Priority Level bits are defined in Table 6 4 The interrupt vectors are shown in Table 6 6 and the interrupt priorities are shown in Table 6 5 Mode F As in Mode C but HDI08 is set for interfacing to Motorola 68302 bus Table 6 4 Interrupt Priority Level Bits IPL bits Interrupts Enabled Interrupt Priority Level xx...

Page 174: ...PL DAX IPL ESAI_1 IPL ESL11 TAL0 TAL1 DAL0 DAL1 reserved TRIPLE TIMER IPL Reserved bit Read as zero should be written with zero for future compatibility ESL10 IAL0 IAL1 IAL2 IBL0 IBL1 IBL2 ICL0 ICL1 ICL2 0 1 2 3 4 5 6 7 8 9 10 11 IRQA IPL IRQA mode IRQB IPL IRQB mode IRQC IPL IRQC mode IRQD IPL D0L0 D0L1 D1L0 D1L1 23 22 21 20 19 18 17 16 15 14 13 12 DMA0 IPL DMA1 IPL D2L0 D2L1 D3L0 D3L1 D4L0 D4L1 ...

Page 175: ... Interrupt IRQD External Interrupt DMA Channel 0 Interrupt DMA Channel 1 Interrupt DMA Channel 2 Interrupt DMA Channel 3 Interrupt DMA Channel 4 Interrupt DMA Channel 5 Interrupt ESAI Receive Data with Exception Status ESAI Receive Even Data ESAI Receive Data ESAI Receive Last Slot ESAI Transmit Data with Exception Status ESAI Transmit Last Slot ESAI Transmit Even Data ESAI Transmit Data SHI Bus E...

Page 176: ...lot ESAI_1 Transmit Data with Exception Status ESAI_1 Transmit Last Slot ESAI_1 Transmit Even Data Lowest ESAI_1 Transmit Data Table 6 6 DSP56367 Interrupt Vectors Interrupt Starting Address Interrupt Priority Level Range Interrupt Source VBA 00 3 Hardware RESET VBA 02 3 Stack Error VBA 04 3 Illegal Instruction VBA 06 3 Debug Request Interrupt VBA 08 3 Trap VBA 0A 3 Non Maskable Interrupt NMI VBA ...

Page 177: ...ceive Data With Exception Status VBA 36 0 2 ESAI Receive Last Slot VBA 38 0 2 ESAI Transmit Data VBA 3A 0 2 ESAI Transmit Even Data VBA 3C 0 2 ESAI Transmit Data with Exception Status VBA 3E 0 2 ESAI Transmit Last Slot VBA 40 0 2 SHI Transmit Data VBA 42 0 2 SHI Transmit Underrun Error VBA 44 0 2 SHI Receive FIFO Not Empty VBA 46 0 2 Reserved VBA 48 0 2 SHI Receive FIFO Full VBA 4A 0 2 SHI Receive...

Page 178: ... 2 Reserved VBA 6C 0 2 Reserved VBA 6E 0 2 Reserved VBA 70 0 2 ESAI_1 Receive Data VBA 72 0 2 ESAI_1 Receive Even Data VBA 74 0 2 ESAI_1 Receive Data With Exception Status VBA 76 0 2 ESAI_1 Receive Last Slot VBA 78 0 2 ESAI_1 Transmit Data VBA 7A 0 2 ESAI_1 Transmit Even Data VBA 7C 0 2 ESAI_1 Transmit Data with Exception Status VBA 7E 0 2 ESAI_1 Transmit Last Slot VBA 80 0 2 Reserved VBA FE 0 2 R...

Page 179: ...sting Device 00000 External IRQA pin 00001 External IRQB pin 00010 External IRQC pin 00011 External IRQD pin 00100 Transfer Done from DMA channel 0 00101 Transfer Done from DMA channel 1 00110 Transfer Done from DMA channel 2 00111 Transfer Done from DMA channel 3 01000 Transfer Done from DMA channel 4 01001 Transfer Done from DMA channel 5 01010 DAX Transmit Data 01011 ESAI Receive Data RDF 1 011...

Page 180: ...e Crystal Range XTLR bit controls the on chip crystal oscillator transconductance The on chip crystal oscillator is not used on the DSP56367 since no XTAL pin is available The XTLR bit is set to zero during hardware reset in the DSP56367 6 6 4 XTAL DISABLE BIT XTLD The XTAL Disable Bit XTLD is set to 1 XTAL disabled during hardware reset in the DSP56367 6 7 DEVICE IDENTIFICATION ID REGISTER The De...

Page 181: ...in data and are controlled by an associated control bit in the boundary scan register The boundary scan register bit definitions are described in Table 6 10 Table 6 8 Identification Register Configuration 23 16 15 12 11 0 Reserved Revision Number Derivative Number 00 0 367 Table 6 9 JTAG Identification Register Configuration 31 28 27 22 21 12 11 1 0 Version Information Customer Part Number Sequenc...

Page 182: ...t Data 19 D11 Input Output Data 95 HAD7 Control 20 D10 Input Output Data 96 HAD7 Input Output Data 21 D9 Input Output Data 97 HAS A0 Control 22 D8 Input Output Data 98 HAS A0 Input Output Data 23 D7 Input Output Data 99 HA8 A1 Control 24 D6 Input Output Data 100 HA8 A1 Input Output Data 25 D5 Input Output Data 101 HA9 A2 Control 26 D4 Input Output Data 102 HA9 A2 Input Output Data 27 D3 Input Outp...

Page 183: ...KT Control 50 A1 Output3 Data 126 SCKT Input Output Data 51 A0 Output3 Data 127 FSR Control 52 BG Input Data 128 FSR Input Output Data 53 AA0 Control 129 FST Control 54 AA0 Output3 Data 130 FST Input Output Data 55 AA1 Control 131 SDO5 SDI0 Control 56 AA1 Output3 Data 132 SDO5 SDI0 Input Output Data 57 RD Output3 Data 133 SDO4 SDI1 Control 58 WR Output3 Data 134 SDO4 SDI1 Input Output Data 59 BB C...

Page 184: ... Data 70 SCKT_1 Control 146 SCK SCL Control 71 SCKT_1 Input Output Data 147 SCK SCL Input Output Data 72 CAS Control 148 MISO SDA Control 73 CAS Output3 Data 149 MISO SDA Input Output Data 74 AA2 Control 150 MOSI HA0 Control 75 AA2 Output3 Data 151 MOSI HA0 Input Output Data Table 6 10 DSP56367 BSR Bit Definition Continued Bit Pin Name Pin Type BSR Cell Type Bit Pin Name Pin Type BSR Cell Type ...

Page 185: ...hich can be controlled separately or as groups Port B up to 16 GPIO signals shared with the HDI08 signals Port C 12 GPIO signals shared with the ESAI signals Port D two GPIO signals shared with the DAX signals Port E 10 GPIO signals shared with the ESAI_1 signals Timer one GPIO signal shared with the timer event counter signal 7 2 1 PORT B SIGNALS AND REGISTERS When HDI08 is disabled all 16 HDI08 ...

Page 186: ... in Section 12 Digital Audio Transmitter 7 2 4 PORT E SIGNALS AND REGISTERS Port E has 10 signals shared with the ESAI_1 Six of the ESAI_1 signals have their own pin so each of the six signals if not used as an ESAI_1 signal can be configured individually as a GPIO signal The other four ESAI_1 signals share pins with the ESAI For these shared pins if the pin is not being used by the ESAI Port C an...

Page 187: ...synchronously to the DSP core clock therefore the HDI08 registers are divided into 2 banks The host register bank is accessible to the external host and the DSP register bank is accessible to the DSP core The HDI08 supports three classes of interfaces Host processor Microcontroller MCU connection interface DMA controller interface General purpose I O GPIO port 8 2 HDI08 FEATURES 8 2 1 INTERFACE DS...

Page 188: ... BTST JCLR JSCLR JSET JSSET simplify I O service routines 8 2 2 INTERFACE HOST SIDE Sixteen signals are provided to support non multiplexed or multiplexed buses H0 H7 HAD0 HAD7 Host data bus H7 H0 or host multiplexed address data bus HAD0 HAD7 HAS HA0 Address strobe HAS or Host address line HA0 HA8 HA1 Host address line HA8 or Host address line HA1 HA9 HA2 Host address line HA9 or Host address lin...

Page 189: ...st to DSP Host Command Handshaking Protocols Software polled Interrupt driven Interrupts are compatible with most processors including the MC68000 8051 HC11 and Hitachi H8 Cycle stealing DMA with initialization Dedicated Interrupts Separate interrupt lines for each interrupt source Special host commands force DSP core interrupts under host processor control which are useful for the following Real ...

Page 190: ...and HACK may be individually programmed as GPIO pins if they are not needed for their HDI08 function Summary of the HDI08 signals Table 8 1 HDI08 Signal Summary HDI08 Port Pin Multiplexed address data bus Mode Non Multiplexed bus Mode GPIO Mode HAD0 HAD7 HAD0 HAD7 H0 H7 PB0 PB7 HAS HA0 HAS HAS HA0 PB8 HA8 HA1 HA8 HA1 PB9 HA9 HA2 HA9 HA2 PB10 HCS HA10 HA10 HCS HCS PB13 Table 8 2 Strobe Signals Supp...

Page 191: ...DDR HCR HSR HDR 24 24 24 24 24 DSP Peripheral Data Bus 8 8 8 8 8 8 5 3 HOST Bus Address Comparator 3 8 8 RXM 24 24 HBAR ISR 8 HOR HOT 24 Core DMA Data Bus 24 24 8 RXH 8 HCR Host Control Register HSR Host Status Register HPCR Host Port Control Register HBAR Host Base Address register HOTX Host Transmit register HORX Host Receive register HDDR Host Data Direction Register HDR Host Data Register ICR ...

Page 192: ...sists of two data registers and six control registers All registers can be accessed by the DSP core but not by the external processor Data registers are 24 bit registers used for high speed data transfer to and from the DSP They are as follows Host Data Receive Register HORX Host Data Transmit Register HOTX The control registers are 16 bit registers used to control the HDI08 functions The eight MS...

Page 193: ...ta from being overwritten data should not be written to the HOTX until the HTDE flag is set Note When writing data to a peripheral device there is a two cycle pipeline delay until any status bits affected by the operation are updated If the programmer reads any of those status bits within the next two cycles the bit will not reflect its current status See the DSP56300 24 Bit Digital Signal Process...

Page 194: ...communication HF2 and HF3 may be set or cleared by the DSP core HF2 and HF3 are reflected in the interface status register ISR on the host side such that if they are modified by the DSP software the host processor can read the modified values by reading the ISR These two flags are not designated for any specific purpose but are general purpose flags They can be used individually or as encoded pair...

Page 195: ...e HOREQ signal to request data transfer The HACK input signal is used as a DMA transfer acknowledge input If the DMA direction is from DSP to host the contents of the selected register are driven onto the host data bus Table 8 5 HDM 2 0 Functionality HDM Mode 2 1 0 Description ICR 0 0 0 DMA operation disabled 1 0 0 DMA Operation Enabled Host may set HM1 or HM0 in the ICR to enable DMA transfers 0 ...

Page 196: ...s the DSP CPU interrupt rate is reduced by a factor of 2 or 3 respectively from the host request rate i e for every two or three host processor data transfers of one byte each there is only one 24 bit DSP CPU interrupt If HDM1 or HDM0 are set the HM 1 0 bits in the ICR register reflect the value of HDM 1 0 The HDM 2 0 bits should be changed only while HEN is cleared in the HPCR 8 5 3 6 HCR Reserve...

Page 197: ...egister CVR HC and HCP are cleared by the HDI08 hardware when the interrupt request is serviced by the DSP core The host can clear HC which also clears HCP 8 5 4 4 HSR Host Flags 0 1 HF0 HF1 Bits 3 4 HF0 and HF1 bits are used as a general purpose flags for host to DSP communication HF0 and HF1 may be set or cleared by the host HF0 and HF1 reflect the status of host flags HF0 and HF1 in the ICR reg...

Page 198: ...e chip select logic is shown in Figure 8 5 8 5 5 1 HBAR Base Address BA 10 3 Bits 0 7 These bits define the base address where the host side registers are mapped into the bus address space 8 5 5 2 HBAR Reserved Bits 8 15 These bits are reserved They read as zero and should be written with zero for future compatibility Figure 8 5 Self Chip Select logic Figure 8 4 Host Base Address Register HBAR X F...

Page 199: ...d bus mode then HA8 HA1 is used as host address line 8 HA8 If this bit is cleared and the HDI08 is used in multiplexed bus mode then HA8 HA1 is configured as GPIO pin according to the value of HDDR and HDR registers HA8EN is ignored when the HDI08 is not in the multiplexed bus mode HMUX 0 8 5 6 3 HPCR Host Address Line 9 Enable HA9EN Bit 2 If the HA9EN bit is set and the HDI08 is used in multiplex...

Page 200: ...is enabled as Host Interface If cleared the HDI08 is not active and all the HDI08 pins are configured as GPIO pins according to the value of HDDR and HDR registers 8 5 6 8 HPCR Reserved Bit 7 This bit is reserved It reads as zero and should be written with zero for future compatibility 8 5 6 9 HPCR Host Request Open Drain HROD Bit 8 The HROD bit controls the output drive of the host request signal...

Page 201: ...a non multiplexed type of bus and the address lines are taken from the HDI08 input signals 8 5 6 13 HPCR Host Dual Data Strobe HDDS Bit 12 If the HDDS bit is cleared the HDI08 operates in the single strobe bus mode In this mode the bus has a single data strobe signal for both reads and writes If HDDS is set the HDI08 operates in the dual strobe bus mode In this mode the bus has two separate data s...

Page 202: ...tive low outputs If HRP is set and host requests are enabled the HTRQ and HRRQ signals are active high outputs 8 5 6 16 HPCR Host Acknowledge Polarity HAP Bit 15 If the HAP bit is cleared the host acknowledge HACK signal is configured as an active low input and the HDI08 drives the contents of the HIVR register onto the host bus when the HACK signal is low If HAP is set HACK is configured as an ac...

Page 203: ...RESET signal The software reset SW is caused by executing the RESET instruction The individual reset IR Figure 8 10 Host Data Register HDR X FFFFC9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 8 6 HDR and HDDR Functionality HDDR HDR DRxx Dxx GPIO pina a Defined by the selected configuration non GPIO pina 0 Read only bit The value read is the bin...

Page 204: ...owledges interrupts caused by the host processor by jumping to the appropriate interrupt service routine The three possible interrupts are as follows Host command Transmit data register empty Receive data register full Although there is a set of vectors reserved for host command use the host command can access any interrupt vector in the interrupt vector table The DSP interrupt service routine Tab...

Page 205: ...the host bus the HDI08 appears to be eight byte wide registers Separate transmit and receive data registers are double buffered to allow the DSP core and host processor to transfer data efficiently at high speed The host may access the HDI08 asynchronously by using polling techniques or interrupt based techniques The HDI08 appears to the host processor as a memory mapped peripheral occupying 8 byt...

Page 206: ...rate One of the most innovative features of the host interface is the host command feature With this feature the host processor can issue vectored interrupt requests to the DSP core The host may select any of 128 DSP interrupt routines to be executed by writing a vector address register in the HDI08 This flexibility allows the host programmer to execute up to 128 pre programmed functions inside th...

Page 207: ...he host request signal HOREQ or HRRQ is asserted if RXDF is set In the DMA modes where HDM 2 0 100 and HM1 0 or HM0 0 RREQ must be set and TREQ must be cleared to direct DMA transfers from DSP to host In the other DMA modes RREQ is ignored Table 8 9 summarizes the effect of RREQ and TREQ on the HOREQ HTRQ and HRRQ signals 8 6 1 2 ICR Transmit Request Enable TREQ Bit 1 In interrupt mode HDM 2 0 000...

Page 208: ...s reflected in the HSR on the DSP side of the HDI08 Table 8 9 TREQ RREQ Interrupt Mode HDM 2 0 000 or HM 1 0 00 TREQ RREQ HDRQ 0 HDRQ 1 HOREQ signal HTRQ signal HRRQ signal 0 0 No Interrupts Polling No Interrupts Polling No Interrupts Polling 0 1 RXDF Request Interrupt No Interrupts Polling RXDF Request Interrupt 1 0 TXDE Request Interrupt TXDE Request Interrupt No Interrupts Polling 1 1 RXDF and ...

Page 209: ...ded as reserved 8 6 1 7 ICR Host Mode Control HM1 and HM0 bits Bits 5 6 Bits 6 and 5 function as read write HM 1 0 bits only when the HCR bits HDM 2 0 100 See Table 8 5 The HM0 and HM1 bits select the transfer mode of the HDI08 as shown in Table 8 12 When both HM1 and HM0 are cleared the DMA mode is disabled and the interrupt mode is enabled In interrupt mode the TREQ and RREQ control bits are use...

Page 210: ...ely from the host request rate i e for every two or three host processor data transfers of one byte each there is only one 24 bit DSP CPU interrupt If either HDM1 or HDM0 in the HCR register are set bits 6 and 5 become read only bits that reflect the value of HDM 1 0 8 6 1 8 ICR Initialize Bit INIT Bit 7 The INIT bit is used by the host processor to force initialization of the HDI08 hardware Durin...

Page 211: ...or otherwise unused addresses provided they have been pre programmed in the DSP HV 6 0 is set to 32 vector location 0064 by hardware software individual and stop resets 8 6 2 2 CVR Host Command Bit HC Bit 7 The HC bit is used by the host processor to handshake the execution of host command interrupts Normally the host processor sets HC to request the host command interrupt from the DSP core When t...

Page 212: ... transmit byte registers are transferred to the HORX register TXDE is cleared when the transmit TXL or TXH according to HLEND bit register is written by the host processor TXDE can be set by the host processor using the initialize feature TXDE may be used to assert the external HOREQ signal if the TREQ bit is set Regardless of whether the TXDE interrupt is enabled TXDE indicates whether the TX reg...

Page 213: ... interrupt source has been enabled by the associated request enable bit in the ICR HREQ is set if one or more of the two enabled interrupt sources is set 8 6 4 INTERRUPT VECTOR REGISTER IVR The IVR is an 8 bit read write register which typically contains the interrupt vector number used with MC68000 Family processor vectored interrupts Only the host processor can read and write this register The c...

Page 214: ...r the host processor When the host reads the receive byte register at host address 7 the RXDF bit is cleared 8 6 6 TRANSMIT BYTE REGISTERS TXH TXM TXL The transmit byte registers are viewed as three 8 bit write only registers by the host processor These registers are the transmit high register TXH the transmit middle register TXM and the transmit low register TXL These registers send data to the h...

Page 215: ... GPIO with all 16 signals disconnected External circuitry connected to the HDI08 may need external pull up pull down resistors until the signals are configured for operation The registers cleared are the HPCR HDDR and HDR Selection between GPIO and HDI08 is made by clearing HPCR bits 6 through 1 for GPIO or setting these bits for HDI08 functionality If the HDI08 is in GPIO mode the HDDR configures...

Page 216: ... is not connected to the host processor and HACK must be deasserted to ensure IVR data is not being driven on H0 H7 when other registers are being polled The host processor first performs a data read transfer to read the ISR register This allows the host processor to assess the status of the HDI08 1 If RXDF 1 the receive byte registers are full and therefore a data read can be performed by the hos...

Page 217: ... If either the HOREQ HTRQ or the HRRQ signal or both are connected to the host processor interrupt inputs the HDI08 can request service from the host processor by asserting one of these signals The HOREQ HTRQ and or the HRRQ signal is asserted when TXDE 1 and or RXDF 1 and the corresponding enable bit TREQ or RREQ respectively is set This is depicted in Figure 8 16 HOREQ HTRQ and HRRQ are normally...

Page 218: ...t processor reads the ISR to determine how to respond to an interrupt generated by the DSP Instead the DSP automatically sources the contents of the IVR on the data bus when the host processor acknowledges the interrupt by asserting HACK The contents of the IVR are placed on the host data bus while HOREQ and HACK are simultaneously asserted The IVR data tells the MC680XX host processor which inter...

Page 219: ... up to 30 bytes before generating a receive interrupt reducing the overhead for data reception When configured in the SPI mode the SHI can perform the following functions Identify its slave selection in slave mode Simultaneously transmit shift out and receive shift in serial data Directly operate with 8 16 and 24 bit words Generate vectored interrupts separately for receive and transmit events and...

Page 220: ...HI as a normal memory mapped peripheral using standard polling or interrupt programming techniques and DMA transfers Memory mapping allows DSP communication with the SHI registers to be accomplished using standard instructions and addressing modes In addition the MOVEP instruction allows interface to memory and memory to interface data transfers without going through an intermediate register The D...

Page 221: ...ter on the master side and the other on the slave side Thus the data bytes in the master device and slave device are exchanged The MISO and MOSI data pins are used for transmitting and receiving serial data When the SPI is configured as a master MISO is the master data input line and MOSI is the master data output line When the SPI is configured as a slave device MISO is the slave data output line...

Page 222: ...PI master mode a bus error is generated the HCSR HBER bit is set 9 4 SHI CLOCK GENERATOR The SHI clock generator generates the SHI serial clock if the interface operates in the master mode The clock generator is disabled if the interface operates in the slave mode except in I2 C mode when the HCKFR bit is set in the HCKR register When the SHI operates in the slave mode the clock is external and is...

Page 223: ...l Host Interface Programming Model MOTOROLA DSP56367 9 5 DSP side see Figure 9 4 and Section 9 5 2 through Section 9 5 6 for detailed information Figure 9 3 SHI Programming Model Host Side 0 I O Shift Register IOSR IOSR 23 AA0418 ...

Page 224: ...with 0 for future compatibility HDM5 HFM1 0 7 6 5 4 3 2 1 HDM6 HDM7 HFM0 HDM2 HDM0 HDM1 HRS HDM3 HDM4 CPHA CPOL SHI Clock Control Register HCKR X FFFF90 0 23 HTX 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 HEN 0 7 6 5 4 3 2 1 HM1 HI 2 C HM0 HRQE0 HMST HRNE HBER HRFF HROE HBUSY HRQE1 HIDLE SHI Control Status Register HCSR HRIE0 HRIE1 HTUE HTDE HTIE X FFFF91 FIFO 10 Words Deep HBIE HFIFO 8 15 14 1...

Page 225: ...MSB first In 8 bit data transfer modes the most significant byte of the IOSR is used as the shift register In 16 bit data transfer modes the two most significant bytes become the shift register In 24 bit transfer modes the shift register uses all three bytes of the IOSR see Figure 9 5 Table 9 1 SHI Interrupt Vectors Program Address Interrupt Source VBA 0040 SHI Transmit Data VBA 0042 SHI Transmit ...

Page 226: ...p mode and during hardware reset software reset and individual reset In the 8 bit data transfer mode the most significant byte of the HTX is transmitted in the 16 bit mode the two most significant bytes and in the 24 bit mode all the contents of HTX is transferred 9 5 3 SHI HOST RECEIVE DATA FIFO HRX DSP SIDE The 24 bit host receive data FIFO HRX is a 10 word deep First In First Out FIFO register ...

Page 227: ...ro for future compatibility 9 5 4 2 HSAR I2 C Slave Address HA 6 3 HA1 Bits 23 20 18 Part of the I2 C slave device address is stored in the read write HA 6 3 HA1 bits of HSAR The full 7 bit slave device address is formed by combining the HA 6 3 HA1 bits with the HA0 and HA2 pins to obtain the HA 6 0 slave device address The full 7 bit slave device address is compared to the received address byte w...

Page 228: ...rammer may select any of four combinations of serial clock SCK phase and polarity when operating in the SPI mode See Figure 9 6 Figure 9 6 SPI Data To Clock Timing Diagram If CPOL is cleared it produces a steady state low value at the SCK pin of the master device whenever data is not being transferred If the CPOL bit is set it produces a high value at the SCK pin of the master device whenever data...

Page 229: ...asserting and asserting the slave device SS line between word transmissions When the SHI is in master mode and CPHA 1 the DSP core should write the next data word to HTX when HTDE 1 clearing HTDE The HTX data is transferred to the shift register for transmission as soon as the shift register is empty HTDE is set when the data is transferred from HTX to the shift register 9 5 5 2 HCKR Prescaler Rat...

Page 230: ...ilters eliminate spikes with durations of up to 50ns This mode is suitable for use in mildly noisy environments and imposes some limitations on the maximum achievable bit rate transfer When HFM 1 0 11 the wide spike tolerance filter mode is selected In this mode the filters eliminate spikes up to 100 ns This mode is recommended for use in noisy environments the bit rate transfer is strictly limite...

Page 231: ...e inhibited output and bidirectional pins are disabled high impedance the HCSR status bits and the transmit receive paths are reset to the same state produced by hardware reset or software reset The individual reset state is entered following a one instruction cycle delay after clearing HEN 9 5 6 2 HCSR I2 C SPI Selection HI2 C Bit 1 The read write control bit HI2 C selects whether the SHI operate...

Page 232: ...idual reset be generated HEN cleared before changing HCKFR HCKFR is cleared during hardware reset and software reset 9 5 6 5 HCSR FIFO Enable Control HFIFO Bit 5 The read write control bit HFIFO selects the receive FIFO size When HFIFO is cleared the FIFO has one level When HFIFO is set the FIFO has 10 levels It is recommended that an SHI individual reset be generated HEN cleared before changing H...

Page 233: ...s transmitted as is If the SHI completes transmitting a word and there is no new data in HTX the clock is suspended after sampling ACK If HIDLE is set when the SHI completes transmitting a word with no new data in HTX a stop event is generated HIDLE determines the acknowledge that the receiver sends after correct reception of a byte If HIDLE is cleared the reception is acknowledged by sending a 0 ...

Page 234: ...atus bit must be polled to determine if HTX is empty If both HTIE and HTDE are set and HTUE is cleared the SHI requests an SHI transmit data interrupt service from the interrupt controller If both HTIE and HTUE are set the SHI requests an SHI transmit underrun error interrupt service from the interrupt controller HTIE is cleared by hardware reset and software reset Note Clearing HTIE masks a pendi...

Page 235: ...ck edge if CPHA 1 it is set at the assertion of SS if CPHA 0 If a transmit interrupt occurs with HTUE set the transmit underrun interrupt vector is generated If a transmit interrupt occurs with HTUE cleared the regular transmit data interrupt vector is generated HTUE is cleared by reading the HCSR and then writing to the HTX register HTUE is cleared by hardware reset software reset SHI individual ...

Page 236: ...FIFO is already full HRFF is set When a receive overrun error occurs the shift register is not transferred to the FIFO If a receive interrupt occurs with HROE set the receive overrun interrupt vector is generated If a receive interrupt occurs with HROE cleared the regular receive data interrupt vector is generated HROE is cleared by reading the HCSR with HROE set followed by reading HRX HROE is cl...

Page 237: ...kHz clock rate are defined The SHI can operate in either mode 9 6 1 OVERVIEW The I2 C bus protocol must conform to the following rules Data transfer may be initiated only when the bus is not busy During data transfer the data line must remain stable whenever the clock line is high Changes in the data line when the clock line is high are interpreted as control signals see Figure 9 7 Figure 9 7 I2C ...

Page 238: ...t This acknowledge bit is a high level put on the bus by the transmitter when the master device generates an extra acknowledge related clock pulse A slave receiver that is addressed must generate an acknowledge after each byte is received Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter The acknowledging device ...

Page 239: ...es the SCL line before proceeding with the data transfer 9 6 2 I2 C DATA TRANSFER FORMATS I2 C bus data transfers follow the following process after the start event a slave device address is sent The address consists of seven address bits and an eighth bit as a data direction bit R W In the data direction bit zero indicates a transmission write and one indicates a request for data read A data tran...

Page 240: ...reset should be generated by clearing the HEN bit The following paragraphs describe programming considerations for each operational mode 9 7 1 SPI SLAVE MODE The SPI slave mode is entered by enabling the SHI HEN 1 selecting the SPI mode HI2 C 0 and selecting the slave mode of operation HMST 0 The programmer should verify that the CPHA and CPOL bits in the HCKR correspond to the external host clock...

Page 241: ...nabled for receive HRQE 1 0 01 is asserted when the IOSR is ready for receive and the HRX FIFO is not full this operation guarantees that the next received data word is stored in the FIFO The HREQ output pin if enabled for transmit HRQE 1 0 10 is asserted when the IOSR is loaded from HTX with a new data word to transfer If HREQ is enabled for both transmit and receive HRQE 1 0 11 it is asserted wh...

Page 242: ...sfers to initiate the transfer of the next word The HRX FIFO contains valid receive data which the DSP can read with either DSP instructions or DMA transfers if the HRNE status bit is set It is recommended that an SHI individual reset HEN cleared be generated before beginning data reception in order to reset the receive FIFO to its initial empty state e g when switching from transmit to receive da...

Page 243: ...en cleared Following a receive initiation data in the SDA line is shifted into IOSR MSB first Following each received byte an acknowledge ACK 0 is sent at the ninth clock pulse via the SDA line Data is acknowledged bytewise as required by the I2 C bus protocol and is transferred to the HRX FIFO when the complete word according to HM 1 0 is filled into IOSR It is the responsibility of the programme...

Page 244: ...rder to terminate the session HTX contents are transferred to IOSR when the complete word according to HM 1 0 has been shifted out It is therefore the responsibility of the programmer to select the correct number of bytes in an I2 C frame so that they fit in a complete number of words For this purpose the slave device address byte does not count as part of the data therefore it is treated separate...

Page 245: ...cated in the high portion of the data word whereas the middle and low portions are ignored Only one byte the slave address byte is shifted out independent of the word length defined by the HM 1 0 bits In order for the DSP to initiate a data transfer the following actions are to be performed The DSP tests the HIDLE status bit If the HIDLE status bit is set the DSP writes the slave device address an...

Page 246: ...set the HIDLE bit at the last required data word As a result the last byte of the next received data word is not acknowledged the slave transmitter releases the SDA line and the SHI generates the stop event and terminates the session In a receive session only the receive path is enabled and the HTX to IOSR transfers are inhibited If the HRNE status bit is set the HRX FIFO contains valid data which...

Page 247: ...SHI proceeds with the transmit session or HIDLE is set the SHI reactivates the clock to generate the stop event and terminate the transmit session 9 7 5 SHI OPERATION DURING DSP STOP The SHI operation cannot continue when the DSP is in the stop state because no DSP clocks are active While the DSP is in the stop state the SHI remains in the individual reset state While in the individual reset state...

Page 248: ...9 30 DSP56367 MOTOROLA Serial Host Interface SHI Programming Considerations ...

Page 249: ...he ESAI and Section 11 describes the ESAI_1 The ESAI and ESAI_1 share 4 data pins This is described in the ESAI_1 section The ESAI block diagram is shown in Figure 10 1 The ESAI is named synchronous because all serial transfers are synchronized to a clock Additional synchronization signals are used to delineate the word frames The normal mode of operation is used to transfer data at a periodic rat...

Page 250: ...RX0 TX5 SDO5 SDI0 PC6 Shift Register RX1 TX4 SDO4 SDI1 PC7 Shift Register RX2 TX3 SDO3 SDI2 PC8 Shift Register RX3 TX2 SDO2 SDI3 PC9 Shift Register TX1 Shift Register TX0 DDB GDB RSMA RSMB TSMA TSMB RCCR RCR TCCR TCR SAICR SAISR TSR TCLK RCLK PC3 SCKT PC4 FST PC5 HCKT PC0 SCKR PC1 FSR PC2 HCKR Clock Frame Sync Generators and Control Logic ...

Page 251: ...riod after the last data bit has been transmitted assuming another data word does not follow immediately If a data word follows immediately there is no high impedance interval SDO0 may be programmed as a general purpose I O pin PC11 when the ESAI SDO0 function is not being used 10 2 2 SERIAL TRANSMIT 1 DATA PIN SDO1 SDO1 is used for transmitting data from the TX1 serial transmit shift register SDO...

Page 252: ...register In the on demand mode with an internally generated bit clock the SDO3 SDI2 pin becomes high impedance for a full clock period after the last data bit has been transmitted assuming another data word does not follow immediately If a data word follows immediately there is no high impedance interval SDO3 SDI2 may be programmed as a general purpose I O pin PC8 when the ESAI SDO3 and SDI2 funct...

Page 253: ...oviding the receivers serial bit clock for the ESAI interface The direction of this pin is determined by the RCKD bit in the RCCR register The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode SYN 0 or as serial flag 0 pin in the synchronous mode SYN 1 When this pin is configured as serial flag pin its direction is determined by the RCKD bit in the...

Page 254: ...nsmitters serial bit clock for the ESAI interface The direction of this pin is determined by the TCKD bit in the TCCR register The SCKT is a clock input or output used by all the enabled transmitters in the asynchronous mode SYN 0 Table 10 1 Receiver Clock Sources asynchronous mode only RHCKD RFSD RCKD Receiver Bit Clock Source OUTPUTS 0 0 0 SCKR 0 0 1 HCKR SCKR 0 1 0 SCKR FSR 0 1 1 HCKR FSR SCKR ...

Page 255: ... asynchronous mode SYN 0 the FSR pin operates as the frame sync input or output used by all the enabled receivers In the synchronous mode SYN 1 it operates as either the serial flag 1 pin TEBE 0 or as the transmitter external buffer enable control TEBE 1 RFSD 1 For further information on pin mode and definition see Table 10 8 and on receiver clock signals see Table 10 1 When this pin is configured...

Page 256: ...1 HIGH FREQUENCY CLOCK FOR TRANSMITTER HCKT HCKT is a bidirectional pin providing the transmitters high frequency clock for the ESAI interface The direction of this pin is determined by the THCKD bit in the TCCR register In the asynchronous mode SYN 0 the HCKT pin operates as the high frequency clock input or output used by all enabled transmitters In the synchronous mode SYN 1 it operates as the ...

Page 257: ...egister synchronized by the frame sync in normal mode or the slot in network mode HCKR may be programmed as a general purpose I O pin PC2 when the ESAI HCKR function is not being used 10 3 ESAI PROGRAMMING MODEL The ESAI can be viewed as five control registers one status register six transmit data registers four receive data registers two transmit slot mask registers two receive slot mask register...

Page 258: ...its specify the divide ratio of the prescale divider in the ESAI transmitter clock generator A divide ratio from 1 to 256 TPM 7 0 00 to FF may be selected The bit clock output is available at the transmit serial bit clock SCKT pin of the DSP The bit clock output is also available internally for use as the bit clock to shift the transmit and receive shift registers The ESAI transmit clock generator...

Page 259: ...H DIVIDER RX SHIFT REGISTER TX SHIFT REGISTER DIVIDE BY 2 PRESCALE DIVIDE BY 1 OR DIVIDE BY 8 DIVIDER DIVIDE BY 1 TO DIVIDE BY 256 TPSR TPM0 TPM7 RX WORD CLOCK TX WORD CLOCK SYN 0 DIVIDE BY 2 PRESCALE DIVIDE BY 1 OR DIVIDE BY 8 DIVIDER DIVIDE BY 1 TO DIVIDE BY 256 FOSC RPSR RPM0 RPM7 RHCKD 1 RHCKD 0 HCKR RHCKD DIVIDER DIVIDE BY 1 TO DIVIDE BY 16 RFP0 RFP3 FOSC THCKD 1 THCKD 0 HCKT THCKD DIVIDER DI...

Page 260: ...nization problems when using the internal DSP clock as source TCKD 1 or THCKD 1 10 3 1 3 TCCR Tx Frame Rate Divider Control TDC4 TDC0 Bits 9 13 The TDC4 TDC0 bits control the divide ratio for the programmable frame rate dividers used to generate the transmitter frame clocks In network mode this ratio may be interpreted as the number of words per frame minus one The divide ratio may range from 2 to...

Page 261: ...t is being driven from an external high frequency clock the TFP3 TFP0 bits specify an additional division ratio in the clock divider chain See Table 10 3 for the specification of the divide ratio The ESAI high frequency clock generator functional diagram is shown in Figure 10 3 FRAME SYNC TRANSMIT FRAME SYNC RECEIVE RX WORD CLOCK TX WORD CLOCK RDC0 RDC4 TDC0 TDC4 RECEIVER FRAME RATE DIVIDER TRANSM...

Page 262: ...ency Clock Polarity THCKP Bit 20 The Transmitter High Frequency Clock Polarity THCKP bit controls on which bit clock edge data and frame sync are clocked out and latched in If THCKP is cleared the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the transmit bit clock If THCKP is set the falling edge of the transmit clock is...

Page 263: ... following paragraphs 10 3 2 1 TCR ESAI Transmit 0 Enable TE0 Bit 0 TE0 enables the transfer of data from TX0 to the transmit shift register 0 When TE0 is set and a frame sync is detected the transmit 0 portion of the ESAI is enabled for that frame When TE0 is cleared the transmitter 0 is disabled after completing transmission of data currently in the ESAI transmit shift register The SDO0 output i...

Page 264: ...s the transmitter 1 after completing transmission of the current data word until the beginning of the next frame During that time period the SDO1 pin remains in the high impedance state The on demand mode transmit enable sequence can be the same as the normal mode or TE1 can be left enabled 10 3 2 3 TCR ESAI Transmit 2 Enable TE2 Bit 2 TE2 enables the transfer of data from TX2 to the transmit shif...

Page 265: ...mission of the current data word until the beginning of the next frame During that time period the SDO3 SDI2 pin remains in the high impedance state The on demand mode transmit enable sequence can be the same as the normal mode or TE3 can be left enabled 10 3 2 5 TCR ESAI Transmit 4 Enable TE4 Bit 4 TE4 enables the transfer of data from TX4 to the transmit shift register 4 When TE4 is set and a fr...

Page 266: ...aring TE5 and setting it again disables the transmitter 5 after completing transmission of the current data word until the beginning of the next frame During that time period the SDO5 SDI0 pin remains in the high impedance state The on demand mode transmit enable sequence can be the same as the normal mode or TE5 can be left enabled 10 3 2 7 TCR Transmit Shift Direction TSHFD Bit 6 The TSHFD bit c...

Page 267: ...is transferred per frame sync during the frame sync time slot as shown in Figure 10 6 In network mode it is possible to transfer a word for every time slot as shown in Figure 10 6 For more details see Section 10 4 Operating Modes In order to comply with AC 97 specifications TSWS4 TSWS0 should be set to 00011 20 bit slot 20 bit word length TFSL and TFSR should be cleared and TDC4 TDC0 should be set...

Page 268: ...RUPT OR DMA REQUEST AND FLAGS SET RECEIVER INTERRUPT OR DMA REQUEST AND FLAGS SET NOTE Interrupts occur and data is transferred once per frame sync Network Mode SERIAL FRAME SYNC TRANSMITTER INTERRUPTS OR DMA REQUEST AND FLAGS SET SLOT 0 SLOT 1 SLOT 2 SLOT 0 SLOT 1 SERIAL DATA RECEIVER INTERRUPT OR DMA REQUEST AND FLAGS SET NOTE Interrupts occur and a word may be transferred at every time slot ...

Page 269: ...n the slot length The possible combinations are shown in Table 10 5 See also the ESAI data path programming model in Figure 10 13 and Figure 10 14 Table 10 5 ESAI Transmit Slot and Word Length Selection TSWS4 TSWS3 TSWS2 TSWS1 TSWS0 SLOT LENGTH WORD LENGTH 0 0 0 0 0 8 8 0 0 1 0 0 12 8 0 0 0 0 1 12 0 1 0 0 0 16 8 0 0 1 0 1 12 0 0 0 1 0 16 0 1 1 0 0 20 8 0 1 0 0 1 12 0 0 1 1 0 16 0 0 0 1 1 20 1 0 0 ...

Page 270: ... TFSL is cleared a word length frame sync is selected If TFSL is set a 1 bit clock period frame sync is selected See Figure 10 7 for examples of frame length selection 0 1 0 1 1 Reserved 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 Table 10 5 ESAI Transmit Slot and Word Length Selection Continued TSWS4 TSWS3 TSWS2 TSWS1 TSWS0 SLOT LE...

Page 271: ...occurs while data is valid DATA DATA SERIAL CLOCK RX TX FRAME SYNC ONE BIT LENGTH TFSL 1 RFSL 1 RX TX SERIAL DATA NOTE Frame sync occurs for one bit time preceding the data DATA DATA SERIAL CLOCK TX FRAME SYNC MIXED FRAME LENGTH TFSL 1 RFSL 0 TX SERIAL DATA RX FRAME SYNC DATA DATA RX SERIAL DATA DATA DATA SERIAL CLOCK TX FRAME SYNC MIXED FRAME LENGTH TFSL 0 RFSL 1 TX SERIAL DATA RX FRAME SYNC DATA...

Page 272: ...smitted If zero padding is enabled PADC 1 zeroes are transmitted after the data word has been transmitted 2 If the data word is right aligned TWA 1 and zero padding is disabled PADC 0 then the first data bit is repeated before the transmission of the data word If zero padding is enabled PADC 1 zeroes are transmitted before the transmission of the data word 10 3 2 14 TCR Reserved Bit Bits 18 This b...

Page 273: ...he TEDE flag thus servicing the interrupt Transmit interrupts with exception have higher priority than transmit even slot data interrupts therefore if exception occurs TUE is set and TEIE is set the ESAI requests an ESAI transmit data with exception interrupt from the interrupt controller 10 3 2 18 TCR Transmit Interrupt Enable TIE Bit 22 The DSP is interrupted when TIE and the TDE flag in the SAI...

Page 274: ...onal diagram is shown in Figure 10 3 10 3 3 2 RCCR Receiver Prescaler Range RPSR Bit 8 The RPSR controls a fixed divide by eight prescaler in series with the variable prescaler This bit is used to extend the range of the prescaler for those cases where a slower bit clock is desired When RPSR is set the fixed prescaler is bypassed When RPSR is cleared the fixed divide by eight prescaler is operatio...

Page 275: ...ck the RFP3 RFP0 bits specify an additional division ration in the clock divider chain See Table 10 6 for the specification of the divide ratio The ESAI high frequency generator functional diagram is shown in Figure 10 3 10 3 3 5 RCCR Receiver Clock Polarity RCKP Bit 18 The Receiver Clock Polarity RCKP bit controls on which bit clock edge data and frame sync are clocked out and latched in If RCKP ...

Page 276: ...lock for the receive shift registers and word length divider and is the output on the SCKR pin In the asynchronous mode when RCKD is cleared the clock source is external the internal clock generator is disconnected from the SCKR pin and an external clock source may drive this pin In the synchronous mode when RCKD is set the SCKR pin becomes the OF0 output flag If RCKD is cleared then the SCKR pin ...

Page 277: ... clock generator becomes the source of the receiver high frequency clock and is the output on the HCKR pin In the asynchronous mode when RHCKD is cleared the receiver high frequency clock source is external the internal clock generator is disconnected from the HCKR pin and an external clock source may drive this pin When RHCKD is cleared HCKR is an input when RHCKD is set HCKR is an output In the ...

Page 278: ...d while receiving a data word the remainder of the word is shifted in and transferred to the RX0 data register If RE0 is set while some of the other receivers are already in operation the first data word received in RX0 will be invalid and must be discarded 10 3 4 2 RCR ESAI Receiver 1 Enable RE1 Bit 1 When RE1 is set and TE4 is cleared the ESAI receiver 1 is enabled and samples data at the SDO4 S...

Page 279: ... already in operation the first data word received in RX3 will be invalid and must be discarded 10 3 4 5 RCR Reserved Bits Bits 4 5 17 18 These bits are reserved They read as zero and they should be written with zero for future compatibility 10 3 4 6 RCR Receiver Shift Direction RSHFD Bit 6 The RSHFD bit causes the receiver shift registers to shift data in MSB first when RSHFD is cleared or LSB fi...

Page 280: ...SWS0 bits are used to select the length of the slot and the length of the data words being received via the ESAI The word length must be equal to or shorter than the slot length The possible combinations are shown in Table 10 11 See also the ESAI data path programming model in Figure 10 13 and Figure 10 14 Table 10 10 ESAI Receive Network Mode Selection RMOD1 RMOD0 RDC4 RDC0 Receiver Network Mode ...

Page 281: ...er i e together with the last bit of the previous data word 10 3 4 12 RCR Receiver Section Personal Reset RPR Bit 19 The RPR control bit is used to put the receiver section of the ESAI in the personal reset state The transmitter section is not affected When RPR is cleared the receiver section may operate normally When RPR is set the receiver section enters the personal reset state immediately When...

Page 282: ...enabled receivers clears the REDF flag thus servicing the interrupt Receive interrupts with exception have higher priority than receive even slot data interrupts therefore if exception occurs ROE is set and REIE is set the ESAI requests an ESAI receive data with exception interrupt from the interrupt controller 10 3 4 15 RCR Receive Interrupt Enable RIE Bit 22 The DSP is interrupted when RIE and t...

Page 283: ...ata bit used to hold data to be send to the OF1 pin When the ESAI is in the synchronous clock mode SYN 1 the FSR pin is configured as the ESAI flag 1 If the receiver frame sync direction bit RFSD is set and the TEBE bit is cleared the FSR pin is the output flag OF1 and data present in the OF1 bit is written to the OF1 pin at the beginning of the frame in normal mode or at the beginning of the next...

Page 284: ...6 SAICR Transmit External Buffer Enable TEBE Bit 7 The Transmitter External Buffer Enable TEBE bit controls the function of the FSR pin when in the synchronous mode If the ESAI is configured for operation in the synchronous mode SYN 1 and TEBE is set while FSR pin is configured as an output RFSD 1 the FSR pin functions as the transmitter external buffer enable control to enable the use of an exter...

Page 285: ...NSMIT FRAME SYNC EXTERNAL RECEIVE FRAME SYNC INTERNAL FRAME SYNC SCKR SCKT EXTERNAL TRANSMIT CLOCK EXTERNAL RECEIVE CLOCK INTERNAL CLOCK ESAI BIT CLOCK NOTE Transmitter and receiver may have different clocks and frame syncs SYNCHRONOUS SYN 1 TRANSMITTER CLOCK FRAME SYNC RECEIVER CLOCK FRAME SYNC SDI SDO FST INTERNAL FRAME SYNC SCKT EXTERNAL CLOCK INTERNAL CLOCK ESAI BIT CLOCK NOTE Transmitter and ...

Page 286: ... RFSD 0 and TEBE 0 indicating that FSR is an input flag and the synchronous mode is selected Data present on the FSR pin is latched during reception of the first received data bit after frame sync is detected The IF1 bit is updated with this data when the receiver shift registers are transferred into the receiver data registers IF1 reads as a zero when it is not enabled Hardware software ESAI indi...

Page 287: ...ISR Receive Data Register Full RDF Bit 8 RDF is set when the contents of the receive shift register of an enabled receiver is transferred to the respective receive data register RDF is cleared when the DSP reads the receive data register of all enabled receivers or cleared by hardware software ESAI individual or STOP reset If RIE is set an ESAI receive data interrupt request is issued when RDF is ...

Page 288: ... request is issued when TUE is set Hardware software ESAI individual and STOP reset clear TUE TUE is also cleared by reading the SAISR with TUE set followed by writing to all the enabled transmit data registers or to TSR 10 3 6 12 SAISR Transmit Data Register Empty TDE Bit 15 TDE is set when the contents of the transmit data register of all the enabled transmitters are transferred to the transmit ...

Page 289: ...e slots are all odd numbered slots 1 3 5 etc Time slots are numbered from zero to N 1 where N is the number of time slots in the frame This flag is set when the contents of the transmit data register of all the enabled transmitters are transferred to the transmit shift registers it is also set for a TSR disabled time slot period in network mode as if data were being transmitted after the TSR was w...

Page 290: ...T 12 BIT 8 BIT a Receive Registers SDO 23 16 15 8 7 0 7 0 7 0 7 0 TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE ESAI TRANSMIT DATA REGISTER WRITE ONLY ESAI TRANSMIT SHIFT REGISTER 23 16 15 8 7 0 7 0 7 0 7 0 TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE NOTES 1 Data is sent MSB first if TSHFD 0 2 24 bit fractional format ALC 0 3 32 bit mode is not shown 4 Data word is left a...

Page 291: ...a is received LSB first if RSHFD 1 2 24 bit fractional format ALC 0 3 32 bit mode is not shown a Receive Registers SDO 23 16 15 8 7 0 7 0 7 0 7 0 TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE ESAI TRANSMIT DATA REGISTER WRITE ONLY ESAI TRANSMIT SHIFT REGISTER 23 16 15 8 7 0 7 0 7 0 7 0 TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE 24 BIT TSWS4 TSWS0 24 BIT DATA 0 0 16 BIT D...

Page 292: ...x becomes full if the associated interrupt is enabled 10 3 9 ESAI TRANSMIT SHIFT REGISTERS The transmit shift registers contain the data being transmitted see Figure 10 13 and Figure 10 14 Data is shifted out to the serial transmit data pins by the selected internal external bit clock when the associated frame sync I O is asserted The number of bits shifted out before the shift registers are consi...

Page 293: ...ters used by the transmitters in network mode to determine for each slot whether to transmit a data word and generate a transmitter empty condition TDE 1 or to tri state the transmitter data pins TSMA and TSMB should each be considered as containing half a 32 bit register TSM See Figure 10 15 and Figure 10 16 Bit number N in TSM TS is the enable disable control bit for transmission in slot number ...

Page 294: ...SR Even if a slot is enabled in TSM the user may chose to write to TSR instead of writing to the transmit data registers TXx This causes all the transmit data pins of the enabled transmitters to be tri stated during the next slot Data written to the TSM affects the next frame transmission The frame being transmitted is not affected by this data and would comply to the last TSM setting Data read fr...

Page 295: ...ve sequence is as usual data which is shifted into the enabled receivers shift registers is transferred to the receive data registers and the RDF flag is set Data written to the RSM affects the next received frame The frame being received is not affected by this data and would comply to the last RSM setting Data read from RSM returns the last written data 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFBB RS11 RS...

Page 296: ...ly if at least one of the ESAI I O pins is programmed as an ESAI pin 10 4 2 ESAI INITIALIZATION The correct way to initialize the ESAI is as follows 1 Hardware software ESAI individual or STOP reset 2 Program ESAI control and time slot registers 3 Write data to all the enabled transmitters 4 Configure at least one pin as ESAI pin During program execution all ESAI pins may be defined as GPIO or dis...

Page 297: ...ceiver data registers clears RDF and REDF 3 ESAI Receive Data Occurs when the receive interrupt is enabled RIE 1 at least one of the enabled receive data registers is full RDF 1 no exception has occurred ROE 0 or REIE 0 and no even slot interrupt has occurred REDF 0 or REDIE 0 Reading all enabled receiver data registers clears RDF 4 ESAI Receive Last Slot Interrupt Occurs if enabled RLIE 1 after t...

Page 298: ...ters or to TSR clears this interrupt request 8 ESAI Transmit Data Occurs when the transmit interrupt is enabled TIE 1 at least one of the enabled transmit data registers is empty TDE 1 no exception has occurred TUE 0 or TEIE 0 and no even slot interrupt has occurred TEDE 0 or TEDIE 0 Writing to all the TX registers of the enabled transmitters or to the TSR clears this interrupt request 10 4 4 OPER...

Page 299: ...ck and sync signals asynchronous operating mode The SYN bit in the SAICR register selects synchronous or asynchronous operation Since the ESAI is designed to operate either synchronously or asynchronously separate receive and transmit interrupts are provided When SYN is cleared the ESAI transmitter and receiver clocks and frame sync sources are independent If SYN is set the ESAI transmitter and re...

Page 300: ...t have to immediately follow the previous frame Gaps of arbitrary periods can occur between frames Enabled transmitters are tri stated during these gaps When operating in the synchronous mode SYN 1 all clocks including the frame sync are generated by the transmitter section 10 4 4 4 Shift Direction Selection Some data formats such as those used by codecs specify MSB first while other data formats ...

Page 301: ...mit data word is transmitted until the first bit of the next transmit data word is transmitted Software may change the OF0 OF2 values thus controlling the SCKR FSR and HCKR pin values for each transmitted word The normal sequence for setting output flags when transmitting data is as follows wait for TDE transmitter empty to be set first write the flags and then write the transmit data to the trans...

Page 302: ...2 PCRC and PRRC Bits Functionality PDC i PC i Port Pin i Function 0 0 disconnected 0 1 GPIO input 1 0 GPIO output 1 1 ESAI 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFBF PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 23 22 21 20 19 18 17 16 15 14 13 12 Reserved bit read as zero should be written with zero for future compatibility Figure 10 19 PCRC Register 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFBE PDC11 PDC10 PDC...

Page 303: ...onfigured as a GPIO input then the corresponding PD i bit reflects the value present on this pin If a port pin i is configured as a GPIO output then the value written into the corresponding PD i bit is reflected on this pin If a port pin i is configured as disconnected the corresponding PD i bit is not reset and contains undefined data 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFBD PD11 PD10 PD9 PD8 PD7 PD6 P...

Page 304: ...are in use during operation Write the first data to be transmitted to the transmitters which are in use during operation This step is needed even if DMA is used to service the transmitters Enable the transmitters and receivers From now on ESAI can be serviced either by polling interrupts or DMA Operation proceeds as follows For internally generated clock and frame sync these signals are active imm...

Page 305: ...c signal either internally or externally generated The transmitter outputs remain tri stated after TEx bit is set until the frame sync occurs From now on the transmitters are operating and can be serviced either by polling interrupts or DMA 10 6 3 INITIALIZING JUST THE ESAI RECEIVER SECTION It is assumed that the ESAI is operational that is at least one pin is defined as an ESAI pin The receiver s...

Page 306: ...10 58 DSP56367 MOTOROLA Enhanced Serial Audio Interface ESAI ESAI Initialization Examples ...

Page 307: ... to the ESAI peripheral described in Section 10 except for minor differences described in this section Refer to the ESAI section for functional information about the ESAI_1 in addition to using the information in this section The ESAI_1 block diagram is shown in Figure 11 1 The ESAI_1 shares 4 pins with the ESAI The ESAI_1 does not have the two high frequency clock pins but otherwise it is identic...

Page 308: ...I0_1 PE6 Shift Register RX1_1 TX4_1 SDO4_1 SDI1_1 PE7 Shift Register RX2_1 TX3_1 SDO3_1 SDI2_1 PE8 Shift Register RX3_1 TX2_1 SDO2_1 SDI3_1 PE9 Shift Register TX1_1 Shift Register TX0_1 DDB GDB RSMA_1 RSMB_1 TSMA_1 TSMB_1 RCCR_1 RCR_1 TCCR_1 TCR_1 SAICR_1 SAISR_1 TSR_1 TCLK RCLK PE3 SCKT_1 PE0 SCKR_1 PE1 FSR_1 shared with SDO0 PC11 shared with SDO1 PC10 shared with SDO2 SDI3 PC9 shared with SDO3 S...

Page 309: ... pin may be used as GPIO PE10 if not used by the ESAI or ESAI_1 The ESAI_1 Multiplex Control Register EMUXR defines if the pin belongs to the ESAI or to the ESAI_1 11 2 3 SERIAL TRANSMIT 2 RECEIVE 3 DATA PIN SDO2_1 SDI3_1 SDO2_1 SDI3_1 transmits data from the TX2_1 serial transmit shift register when programmed as a transmitter pin or receives serial data to the RX3_1 serial receive shift register...

Page 310: ...nctions are not being used 11 2 6 SERIAL TRANSMIT 5 RECEIVE 0 DATA PIN SDO5_1 SDI0_1 SDO5_1 SDI0_1 transmits data from the TX5_1 serial transmit shift register when programmed as transmitter pin or receives serial data to the RX0_1 serial shift register when programmed as a receiver pin SDO5_1 SDI0_1 may be programmed as a general purpose pin PE6 when the ESAI_1 SDO5_1 and SDI0_1 functions are not...

Page 311: ...erface FST_1 may be programmed as a general purpose I O pin PE4 when the ESAI_1 FST_1 function is not being used 11 3 ESAI_1 PROGRAMMING MODEL The ESAI_1 has the following registers One multiplex control register Five control registers One status register Six transmit data registers Four receive data registers Two transmit slot mask registers Two receive slot mask registers One special purpose tim...

Page 312: ...quency clock sources and the directions of the FST_1 and SCKT_1 signals In synchronous mode the bit clock defined for the transmitter determines the receiver bit clock as well TCCR_1 also controls the number of words per frame for the serial data 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFFAF EMUX3 EMUX2 EMUX1 EMUX0 23 22 21 20 19 18 17 16 15 14 13 12 Reserved bit read as zero should be written with zero for ...

Page 313: ...e the transmitter high frequency clock pin It it recommended that THCKP should be kept cleared 11 3 2 3 TCCR_1 Tx High Freq Clock Direction THCKD Bit 23 The ESAI_1 does not have the transmitter high frequency clock pin THCKD must be set for proper ESAI_1 transmitter section operation 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF96 TDC2 TDC1 TDC0 TPSR TPM7 TPM6 TPM5 TPM4 TPM3 TPM2 TPM1 TPM0 23 22 21 20 19 18 17...

Page 314: ...GTH DIVIDER TX WORD LENGTH DIVIDER RX SHIFT REGISTER TX SHIFT REGISTER DIVIDE BY 2 PRESCALE DIVIDE BY 1 OR DIVIDE BY 8 DIVIDER DIVIDE BY 1 TO DIVIDE BY 256 TPSR TPM0 TPM7 RX WORD CLOCK TX WORD CLOCK SYN 0 DIVIDE BY 2 PRESCALE DIVIDE BY 1 OR DIVIDE BY 8 DIVIDER DIVIDE BY 1 TO DIVIDE BY 256 FOSC RPSR RPM0 RPM7 RHCKD 1 DIVIDER DIVIDE BY 1 TO DIVIDE BY 16 RFP0 RFP3 FOSC THCKD 1 DIVIDER DIVIDE BY 1 TO ...

Page 315: ... SYNC TRANSMIT FRAME SYNC RECEIVE RX WORD CLOCK TX WORD CLOCK RDC0 RDC4 TDC0 TDC4 RECEIVER FRAME RATE DIVIDER TRANSMITTER FRAME RATE DIVIDER RECEIVE CONTROL LOGIC TRANSMIT CONTROL LOGIC RFSL TFSL SYNC TYPE SYNC TYPE SYN 0 SYN 1 INTERNAL RX FRAME CLOCK RFSD 1 SYN 1 RFSD 0 SYN 0 RFSD FSR_1 TFSD FST_1 INTERNAL TX FRAME CLOCK FLAG1 IN SYNC MODE FLAG1OUT SYNC MODE ...

Page 316: ... clock generator bit and frame sync rates word length and number of words per frame for the serial data Hardware and software reset clear all the bits of the RCCR_1 register 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF95 TSWS1 TSWS0 TMOD1 TMOD0 TWA TSHFD TE5 TE4 TE3 TE2 TE1 TE0 23 22 21 20 19 18 17 16 15 14 13 12 TLIE TIE TEDIE TEIE TPR PADC TFSR TFSL TSWS4 TSWS3 TSWS2 Reserved bit read as zero should be writ...

Page 317: ...ot have the receiver high frequency clock pin RHCKD must be set for proper ESAI_1 receiver section operation 11 3 5 ESAI_1 RECEIVE CONTROL REGISTER RCR_1 The read write Receive Control Register RCR_1 controls the ESAI_1 receiver section Hardware and software reset clear all the bits in the RCR_1 register Table 11 3 Receiver Clock Sources asynchronous mode only RHCKD RFSD RCKD Receiver Bit Clock So...

Page 318: ...ER SAISR_1 The Status Register SAISR_1 is a read only status register used by the DSP to read the status and serial input flags of the ESAI_1 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF94 ALC TEBE SYN OF2 OF1 OF0 23 22 21 20 19 18 17 16 15 14 13 12 Reserved bit read as zero should be written with zero for future compatibility Figure 11 9 SAICR_1 Register 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF93 RODF REDF RDF ROE R...

Page 319: ...Xx_1 becomes full if the associated interrupt is enabled 11 3 10 ESAI_1 TRANSMIT SHIFT REGISTERS The Transmit Shift Registers contain the data being transmitted Data is shifted out to the serial transmit data pins by the selected internal external bit clock when the associated frame sync I O is asserted The number of bits shifted out before the shift registers are considered empty and may be writt...

Page 320: ...e registers used by the transmitters in network mode to determine for each slot whether to transmit a data word and generate a transmitter empty condition TDE 1 or to tri state the transmitter data pins TSMA_1 and TSMB_1 should each be considered as containing half a 32 bit register TSM_1 See Figure 11 11 and Figure 11 12 Bit number N in TSM_1 TS is the enable disable control bit for transmission ...

Page 321: ...a 32 bit register RSM_1 See Table 11 13 and Table 11 14 Bit number N in RSM_1 RS is an enable disable control bit for receiving data in slot number N 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF9B RS11 RS10 RS9 RS8 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 23 22 21 20 19 18 17 16 15 14 13 12 RS15 RS14 RS13 RS12 Reserved bit read as zero should be written with zero for future compatibility Figure 11 13 RSMA_1 Register 1...

Page 322: ... or disconnected and is active only if at least one of the ESAI_1 I O pins is programmed as belonging to the ESAI_1 11 5 GPIO PINS AND REGISTERS The GPIO functionality of the ESAI_1 port is controlled by three registers Port E Control register PCRE Port E Direction register PRRE and Port E Data register PDRE 11 5 1 PORT E CONTROL REGISTER PCRE The read write 24 bit Port E Control Register PCRE in ...

Page 323: ... Table 11 4 PCRE and PRRE Bits Functionality PDE i PE i Port Pin i Function 0 0 disconnected 0 1 GPIO input 1 0 GPIO output 1 1 ESAI_1 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF9F PE11 PE10 PE9 PE8 PE7 PE6 PE4 PE3 PE1 PE0 23 22 21 20 19 18 17 16 15 14 13 12 Reserved bit read as zero should be written with zero for future compatibility Figure 11 15 PCRE Register 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF9E PDE11 PDE10...

Page 324: ... configured as a GPIO input then the corresponding PD i bit will reflect the value present on this pin If a port pin i is configured as a GPIO output then the value written into the corresponding PD i bit will be reflected on this pin If a port pin i is configured as disconnected the corresponding PD i bit is not reset and contains undefined data 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF9D PD11 PD10 PD9 PD...

Page 325: ...ures the DAX to operate in slave or master mode Supports both master mode and slave mode in a digital audio network If the user selects a divided DSP core clock the DAX will operate in the master mode If the user selects an external clock source the DAX will operate in the slave mode GPIO Each of the two DAX pins can be configured as either GPIO or as specific DAX pin Each pin is independent of th...

Page 326: ...l DAX Clock Input ACI PD0 When the DAX clock is configured to be supplied externally the external clock is applied to the ACI pin The frequency of the external clock must be 256 times 384 times or 512 times the audio sampling frequency 256 Fs 384 Fs or 512 Fs The ACI pin may also be used as a GPIO pin PD0 when the DAX is disabled or when operating from the internal DSP clock 26 XSTR C U V PRTYG Bi...

Page 327: ...for channel A and to the XNADBUF registers for channel B at the beginning of a frame transmission This is called an upload The DAX audio data register empty XADE flag is set when XADR and XADBUFA are empty and if the audio data register empty interrupt is enabled XDIE 1 an interrupt request is sent to the DSP core The interrupt handling routine then sends the non audio data bits to XNADR and the n...

Page 328: ...calculated parity for channel B This completes a frame transmission When the channel B parity is sent the audio data for the next frame stored in XADBUFA and the non audio data bits from the XNADR are uploaded to XADSR 12 4 DAX PROGRAMMING MODEL The programmer accessible DAX registers are shown in Figure 12 2 The registers are described in the following subsections The Interrupt Vector table for t...

Page 329: ...t to the DSP core When channel B is transferred to XADR the XADE bit in the XSTR is cleared XADR can also be accessed by DMA When XADR and XADBUFA are empty the DAX sends a DMA request to the core The DMA first transfers non audio data bits to XNADR optional then transfers channel A and channel B to XADR The XADR can be accessed with two different successive addresses This feature supports sending...

Page 330: ...he channel A subframe is transferred to XADSR at the same time that the three bits of non audio data V bit U bit and C bit for channel A in the DAX non audio data register XNADR are transferred to the three highest order bits of the XADSR At the beginning of the channel B transmission audio and non audio data for channel B are transferred from the XADBUFB and the XNADBUF to the XADSR for shifting ...

Page 331: ...DR bits are reserved They read as 0 and should be written with 0 to ensure compatibility with future device versions 12 5 5 DAX NON AUDIO DATA BUFFER XNADBUF The XNADBUF is a 3 bit register that temporarily holds channel B non audio data XVB XUB and XCB for the current transmission while the channel A data is being transmitted This mechanism provides programmers more instruction cycles to store th...

Page 332: ...interrupt request signal to the DSP if the XBLK and XADE status bits are set When XBIE bit is cleared this interrupt is disabled 12 5 6 4 DAX Clock Input Select XCS 1 0 Bits 3 4 The XCS 1 0 bits select the source of the DAX clock and or its frequency Table 12 3 shows the configurations selected by these bits These bits should be changed only when the DAX is disabled 12 5 6 5 DAX Start Block XSB Bi...

Page 333: ...ta buffers XADBUFA or XADBUFB are empty and the respective audio data upload occurs When a DAX underrun error occurs the previous frame data will be retransmitted in both channels When XAUR is set and the interrupt is enabled XUIE 1 an underrun error interrupt request is sent to the DSP core This allows programmers to write an exception handling routine for this special case The XAUR bit is cleare...

Page 334: ...on audio bit into its biphase mark format and shifts this encoded data out to the ADO output pin synchronously to the biphase clock 12 5 10 DAX PREAMBLE GENERATOR The DAX preamble generator automatically generates one of three preambles in the 8 bit preamble shift register at the beginning of each subframe transmission and shifts it out The generated preambles always start with 0 Bit patterns of p...

Page 335: ...192 frames transmitted See Figure 12 4 for an illustration of the preamble sequence Figure 12 4 Preamble sequence 12 5 11 DAX CLOCK MULTIPLEXER The DAX clock multiplexer selects one of the clock sources and generates the biphase clock 128 Fs and shift clock 64 Fs The clock source can be selected from the following options see also Section 12 5 6 4 DAX Clock Input Select XCS 1 0 Bits 3 4 The intern...

Page 336: ... the DAX 12 6 DAX PROGRAMMING CONSIDERATIONS The following sections describe programming considerations for the DAX 12 6 1 INITIATING A TRANSMIT SESSION To initiate the DAX operation follow this procedure 1 Ensure that the DAX is disabled PC1 and PC0 bits of port control register PCR are cleared 2 Write the non audio data to the corresponding bits in the XNADR register 3 Write the channel A and ch...

Page 337: ...to frame this procedure can be handled within a fast interrupt routine Storing the next frame s audio data in the FIFO clears the XADE bit in the XSTR 12 6 3 BLOCK TRANSFERRED INTERRUPT HANDLING An interrupt with the XBLK vector indicates the end of a block transmission and may require some computation to provide the next non audio data structures that are to be transmitted within the next block W...

Page 338: ...2 0 010 Line transfer mode D3D 0 Not 3D DAM 5 3 000 2D mode DAM 2 0 101 post increment by 1 DDS 1 0 00 X memory space DRS 4 0 01010 DAX is DMA request source Other bits are application dependent DE 1 Enable DMA channel DIE 1 Enable DMA interrupt DTM 2 0 010 Line transfer mode D3D 0 Not 3D DAM 5 3 000 2D mode DAM 2 0 101 post increment by 1 DDS 1 0 00 X memory space DRS 4 0 01010 DAX is DMA request...

Page 339: ... PORT D PINS AND REGISTERS The Port D GPIO functionality of the DAX is controlled by three registers Port D Control Register PCRD Port D Direction Register PRRD and Port D Data Register PDRD Non Audio Data Channel A Channel A Channel B Channel B Non Audio Data Non Audio Data Non Audio Data Channel A Channel A Channel B Channel B 000000 00000B 000005 000004 000003 000002 000001 000007 000006 00000A...

Page 340: ...DIRECTION REGISTER PRRD The read write 24 bit Port D Direction Register controls the direction of the DAX GPIO pins When port pin i is configured as GPIO PDC i controls the port pin direction When PDC i is set the GPIO port pin i is configured as output When PDC i is cleared the GPIO port pin i is configured as input Hardware and software reset clear all PRRD bits Table 12 6 describes the port pin...

Page 341: ... corresponding PD i bit will be reflected on the this pin Hardware and software reset clear all PDRD bits PDC1 PC1 ADO PD1 pin PDC0 PC0 ACI PD0 pin DAX state 0 0 Disconnected 0 0 Disconnected Personal Reset 0 0 Disconnected 0 1 PD0 Input Personal Reset 0 0 Disconnected 1 0 PD0 Output Personal Reset 0 0 Disconnected 1 1 ACI Enabled 0 1 PD1 Input 0 0 Disconnected Personal Reset 0 1 PD1 Input 0 1 PD0...

Page 342: ...itter GPIO PORT D Pins and Registers Figure 12 9 Port D Data Register PDRD 7 PD1 1 PD0 0 4 3 2 5 6 15 12 11 10 13 14 8 9 read as zero should be written with zero for future compatibility 23 20 19 18 21 22 16 17 PDRD Port D Data Register X FFFFD5 ...

Page 343: ...n external signal When TIO0 is configured as an output timer 0 can function as a timer a watchdog timer or a pulse width modulator TIO0 can also function as a GPIO signal 13 2 TIMER EVENT COUNTER ARCHITECTURE The timer module is composed of a common 21 bit prescaler and three independent general purpose 24 bit timer event counters each having its own register set 13 2 1 TIMER EVENT COUNTER BLOCK D...

Page 344: ...egister TCSR a 24 bit read only timer count register TCR a 24 bit write only timer load register TLR a 24 bit read write timer compare register TCPR and logic for clock selection and interrupt DMA trigger generation The timer mode is controlled by the TC 3 0 bits of the timer control status register TCSR Timer modes are described in Section 13 4 Figure 13 1 Timer Event Counter Block Diagram Timer ...

Page 345: ...rds in the X data memory space Either standard polled or interrupt programming techniques can be used to service the timers The timer programming model is shown in Figure 13 3 Figure 13 2 Timer Block Diagram GDB Control Status Register TCSR Counter Timer interrupt Timer Control CLK 2 TIO Compare Register TCPR 24 24 DMA request Logic Load Register Count Register TLR prescaler CLK TCR 24 24 9 2 24 2...

Page 346: ...should be written with 0 for future compatibility 23 0 Timer Load Register TLR 23 22 21 20 19 18 17 16 23 0 Timer Compare Register TCPR PCE TRM TCF TOF TOIE TC2 23 0 Timer Count Register TCR TC3 TCSR0 FFFF8F TCSR1 FFFF8B TCSR2 FFFF87 TLR0 FFFF8E TLR1 FFFF8A TLR2 FFFF86 TCR0 FFFF8C TCR1 FFFF88 TCR2 FFFF84 TCPR0 FFFF8D TCPR1 FFFF89 TCPR2 FFFF85 23 0 Timer Prescaler Load Register TPLR TPLR FFFF83 23 ...

Page 347: ...e from disabled to enabled If PL 20 0 N then the prescaler counts N 1 source clock cycles before generating a prescaler clock pulse Therefore the prescaler divide factor preload value 1 The PL 20 0 bits are cleared by the hardware RESET signal or the software RESET instruction 13 3 2 2 TPLR Prescaler Source PS 1 0 Bits 22 21 The two prescaler source PS bits control the source of the prescaler cloc...

Page 348: ... bit read only register that reflects the current value in the prescaler counter See Figure 13 5 13 3 3 1 TPCR Prescaler Counter Value PC 20 0 Bits 20 0 These 21 bits contain the current value of the prescaler counter 13 3 3 2 TPCR Reserved Bits 23 21 These reserved bits are read as zero and should be written with zero for future compatibility Table 13 1 Prescaler Source Selection PS1 PS0 PRESCALE...

Page 349: ...lue is at the maximum value and a new event causes the counter to be incremented to 000000 the timer generates an overflow interrupt Clearing the TOIE bit disables overflow interrupt generation The TOIE bit is cleared by the hardware RESET signal or the software RESET instruction 13 3 4 3 TCSR Timer Compare Interrupt Enable TCIE Bit 2 The Timer Compare Interrupt Enable TCIE bit is used to enable o...

Page 350: ...Timer 0 Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 Mode Number Mode Function TIO0 Clock 0 0 0 0 0 Timer and GPIO GPIO Internal 0 0 0 1 1 Timer pulse Output Internal 0 0 1 0 2 Timer toggle Output Internal 0 0 1 1 3 Event counter Input External 0 1 0 0 4 Input width measurement Input Internal 0 1 0 1 5 Input period measurement Input Internal 0 1 1 0 6 Capture event Input Internal 0 1 1 1 7 Pu...

Page 351: ...GPIO signal on the TIO0 signal inverted Bit written to GPIO put on TIO0 signal directly Bit written to GPIO inverted and put on TIO0 signal 1 Counter is incremented on the rising edge of the signal from the TIO0 signal Counter is incremented on the falling edge of the signal from the TIO0 signal 2 Counter is incremented on the rising edge of the signal from the TIO0 signal Counter is incremented o...

Page 352: ... counter overflow occurs In measurement 4 5 modes if the TRM and the TE bits are set the counter is preloaded with the TLR value on each appropriate edge of the input signal If the TRM bit is cleared the counter operates as a free running counter and is incremented on each incoming event The TRM bit is cleared by the hardware RESET signal or the software RESET instruction 13 3 4 7 TCSR Direction D...

Page 353: ...f the DO bit is written directly to the TIO0 signal When GPIO mode is disabled writing the DO bit has no effect The DO bit is cleared by the hardware RESET signal or the software RESET instruction This bit is not in use for timers 1 and 2 It should be left cleared 13 3 4 10 TCSR Prescaler Clock Enable PCE Bit 15 The PCE bit is used to select the prescaler clock as the timer source clock When the P...

Page 354: ...3 These reserved bits are read as zero and should be written with zero for future compatibility 13 3 5 TIMER LOAD REGISTER TLR The TLR is a 24 bit write only register In all modes the counter is preloaded with the TLR value after the TE bit in the TCSR is set and a first event occurs The programmer must initialize the TLR to ensure correct operation in the appropriate timer operating modes In time...

Page 355: ... TCR register In measurement modes the TCR is loaded with the current value of the counter on the appropriate edge of the input signal and its value can be read to determine the width period or delay of the leading edge of the input signal When the timer is in measurement modes the TIO0 signal is used for the input signal 13 4 TIMER MODES OF OPERATION Each timer has various operational modes that ...

Page 356: ...access on the TIO0 signal Set the TE bit to clear the counter and enable the timer Load the value the timer is to count into the TCPR The counter is loaded with the TLR value when the first timer clock signal is received The timer clock can be taken from either the DSP56367 clock divided by two CLK 2 or from the prescaler clock output Each subsequent clock signal increments the counter When the co...

Page 357: ...are interrupt is generated if the TCIE bit is set The polarity of the TIO0 signal is inverted for one timer clock period If the TRM bit is set the counter is loaded with the TLR value on the next timer clock and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each timer clock This process is repeated until the TE bit is cleared disabling the timer The valu...

Page 358: ...TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set If the TRM bit is set the counter is loaded with the value of the TLR when the next timer clock is received and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each timer clock This process is repeated until the TE bit is cleared disabling the timer The TLR value in the ...

Page 359: ...high 0 to 1 transitions or high to low 1 to 0 transitions increment the counter If the INV bit is set high to low transitions increment the counter If the INV bit is cleared low to high transitions increment the counter When the counter matches the value contained in the TCPR the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set If the TRM bit is set the counte...

Page 360: ...s set the timer starts on the first high to low 1 to 0 signal transition on the TIO0 signal If the INV bit is cleared the timer starts on the first low to high 0 to 1 transition on the TIO0 signal When the first transition opposite in polarity to the INV bit setting occurs on the TIO0 signal the counter stops The TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is se...

Page 361: ...CLK 2 or the prescaler clock output Each subsequent clock signal increments the counter On the next signal transition of the same polarity that occurs on TIO0 the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set The contents of the counter are loaded into the TCR The TCR then contains the value of the time that elapsed between the two signal transitions on the...

Page 362: ...opriate transition of the external clock detected on the TIO0 signal the TCF bit in the TCSR is set and if the TCIE bit is set a compare interrupt is generated The counter halts The contents of the counter are loaded into the TCR The value of the TCR represents the delay between the setting of the TE bit and the detection of the first clock edge signal on the TIO0 signal If the INV bit is set a hi...

Page 363: ...ter is loaded with the TLR value on the next timer clock and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each timer clock This process is repeated until the timer is disabled by clearing the TE bit TIO0 signal polarity is determined by the value of the INV bit When the counter is started by setting the TE bit the TIO0 signal assumes the value of the IN...

Page 364: ... TCPR the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is also set If the TRM bit is set the counter is loaded with the TLR value on the next timer clock and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each subsequent timer clock This process is repeated until the timer is disabled i e TE is cleared If the counter ove...

Page 365: ... and a compare interrupt is generated if the TCIE bit is also set If the TRM bit is set the counter is loaded with the TLR value on the next timer clock and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each subsequent timer clock When counter overflow has occurred the polarity of the TIO0 output pin is inverted the TOF bit in the TCSR is set and an over...

Page 366: ...timer activity is stopped and the TIO0 signal is disconnected Any external changes that happen to the TIO0 signal is ignored when the DSP56367 is the stop state To ensure correct operation the timers should be disabled before the DSP56367 is placed into the stop state 13 4 7 DMA TRIGGER Each timer can also be used to trigger DMA transfers For this to occur a DMA channel must be programmed to be tr...

Page 367: ... package pinouts and tables describing how the signals described in Section 1 are allocated for the package The DSP56367 is available in a 144 pin LQFP package Table 14 1and Table 14 2 show the pin name assignments for the packages 14 1 1 LQFP PACKAGE DESCRIPTION Top view of the 144 pin LQFP package is shown in Figure 14 1 with its pin outs The package drawing is shown in Figure 14 2 ...

Page 368: ...62 BR 63 BB 64 VCCC 65 GNDC 66 WR 67 RD 68 AA1 69 AA0 70 BG 71 A0 72 SCK SCL 1 SS HA2 2 HREQ 3 SDO0 SDO0_1 4 SDO1 SDO1_1 5 SDO2 SDI3 SDO2_1 SDI3_1 6 SDO3 SDI2 SDO3_1 SDI2_1 7 VCCS 8 GNDS 9 SDO4 SDI1 10 SDO5 SDI0 11 FST 12 FSR 13 SCKT 14 SCKR 15 HCKT 16 HCKR 17 VCCQL 18 GNDQ 19 VCCQH 20 HDS HWR 21 HRW HRD 22 HACK HRRQ 23 HOREQ HTRQ 24 VCCS 25 GNDS 26 ADO 27 ACI 28 TIO0 29 HCS HA10 30 HA9 HA2 31 HA8...

Page 369: ... D16 122 HAD2 41 SDO5_1 SDI0_1 48 A8 84 D17 123 HAD3 40 SS HA2 2 A9 85 D18 124 HAD4 37 TA 62 A10 88 D19 125 HAD5 36 TCK 141 A11 89 D20 128 HAD6 35 TDI 140 A12 92 D21 131 HAD7 34 TDO 139 A13 93 D22 132 HAS HA0 33 TIO0 29 A14 94 D23 133 HCKR 17 TMS 142 A15 97 EXTAL 55 HCKT 16 VCCA 74 A16 98 FSR 13 HCS HA10 30 VCCA 80 A17 99 FSR_1 59 HDS HWR 21 VCCA 86 AA0 70 FST 12 HOREQ HTRQ 24 VCCC 57 AA1 69 FST_1...

Page 370: ...GNDD 130 RD 68 VCCQL 56 D3 105 GNDH 39 RESET 44 VCCQL 91 D4 106 GNDP 47 SCK SCL 1 VCCQL 126 D5 107 GNDQ 19 SCKR 15 VCCP 45 D6 108 GNDQ 54 SCKR_1 60 VCCS 8 D7 109 GNDQ 90 SCKT 14 VCCS 25 D8 110 GNDQ 127 SCKT_1 53 WR 67 Table 14 1 Signal Identification by Name Continued Signal Name Pin No Signal Name Pin No Signal Name Pin No Signal Name Pin No ...

Page 371: ...T 48 SDO5_1 SDI0_1 84 A8 120 GNDD 13 FSR 49 VCCQH 85 A9 121 D15 14 SCKT 50 FST_1 86 VCCA 122 D16 15 SCKR 51 AA2 87 GNDA 123 D17 16 HCKT 52 CAS 88 A10 124 D18 17 HCKR 53 SCKT_1 89 A11 125 D19 18 VCCQL 54 GNDQ 90 GNDQ 126 VCCQL 19 GNDQ 55 EXTAL 91 VCCQL 127 GNDQ 20 VCCQH 56 VCCQL 92 A12 128 D20 21 HDS HWR 57 VCCC 93 A13 129 VCCD 22 HRW HRD 58 GNDC 94 A14 130 GNDD 23 HACK HRRQ 59 FSR_1 95 VCCQH 131 D...

Page 372: ...14 6 DSP56367 MOTOROLA Packaging Pin out and Package Information 35 HAD6 71 BG 107 D5 143 MOSI HA0 36 HAD5 72 A0 108 D6 144 MISO SDA Table 14 2 Signal Identification by Pin Number Continued ...

Page 373: ...Packaging Pin out and Package Information MOTOROLA DSP56367 14 7 14 1 2 LQFP PACKAGE MECHANICAL DRAWING Figure 14 2 DSP56367 144 pin LQFP Package ...

Page 374: ...P56367 MOTOROLA Packaging Ordering Drawings 14 2 ORDERING DRAWINGS The detailed package drawing is available on the Motorola web page at http www mot sps com cgi bin cases pl Use package 918 03 for the search ...

Page 375: ...ginning with address C00000 MD 0 or 008000 MD 1 assuming that an external memory of SRAM type is used The accesses will be performed using 31 wait states with no address attributes selected default area If MD MC MB MA 0001 then it loads a program RAM segment from consecutive byte wide P memory locations starting at P D00000 bits 7 0 The memory is selected by the Address Attribute AA1 and is access...

Page 376: ...rting at the specified starting address After reading the program words program execution starts from the same address where loading started The Host Interface bootstrap load program may be stopped by setting the Host Flag 0 HF0 This will start execution of the loaded program from the specified starting address If MD MC MB MA 1101 then it loads the program RAM from the Host Interface programmed to...

Page 377: ...odified by the bootstrap code All the address lines are enabled and should be connected accordingly If MD MC MB MA 1111 then it loads the program RAM from the Host Interface programmed to operate in the MC68302 IMP bus mode in single strob pin configuration The HOST MC68302 bootstrap code expects accesses that are byte wide The HOST MC68302 bootstrap code expects to read 3 bytes forming a 24 bit w...

Page 378: ...s Register M_HCKR EQU FFFF90 SHI Clock Control Register HRNE EQU 17 SHI FIFO Not Empty flag HI2C EQU 1 SHI I2C Enable Control Bit HCKFR EQU 4 SHI I2C Clock Freeze Control Bit HFM0 EQU 12 SHI I2C Filter Mode Bit 0 HFM1 EQU 13 SHI I2C Filter Mode Bit 1 ORG PL ff0000 PL ff0000 bootstrap code starts at ff0000 START movep 0 X M_OGDB enable OnCE nop 5 NOP instructions needed for test procedure nop nop n...

Page 379: ... bytes Define the address to which to start loading the program to 3 3n bytes while n is the program length defined by the first 3 bytes The program words will be stored in contiguous PRAM memory locations starting at the specified starting address After storing the program words program execution starts from the same address where loading started move A9 r1 prepare SHI control value in r1 HEN 1 H...

Page 380: ... move a1 r1 save it in r1 a0 holds the number of words do a0 _LOOP10 read program words do 3 _LOOP11 Each instruction has 3 bytes movem p r2 a2 Get the 8 LSB from ext P mem asr 8 a a Shift 8 bit data into A1 _LOOP11 Go get another byte movem a1 p r0 Store 24 bit result in P mem nop pipeline delay _LOOP10 and go get another 24 bit word Boot from EPROM done bra FINISH OMR1XXX jclr MC omr BURN_RESER ...

Page 381: ...multiplexed bus with negative strobe pulses dual negative request F MC68302 Single strobe non multiplexed bus with negative strobe pulse single negative request MC68302HOSTLD movep 0000000000111000 x M_HPCR Configure the following conditions HAP 0 Negative host acknowledge HRP 0 Negative host request HCSP 0 Negatice chip select input HDDS 0 Single strobe bus R W and DS HMUX 0 Non multiplexed bus H...

Page 382: ...N 1 Host chip select input enabled HA9EN 0 address 9 enable bit has no meaning in non multiplexed bus HA8EN 0 address 8 enable bit has no meaning non multiplexed bus HGEN 0 Host GPIO pins are disabled bra HDI08CONT HC11HOSTLD movep 0000001000011000 x M_HPCR Configure the following conditions HAP 0 Negative host acknowledge HRP 0 Negative host request HCSP 0 Negatice chip select input HDDS 0 Single...

Page 383: ...ld be set to 0 for future compatability HEN 0 When the HPCR register is modified HEN should be cleared HAEN 0 Host acknowledge is disabled HREN 1 Host requests are enabled HCSEN 1 Host chip select input enabled HA9EN 1 Enable address 9 input HA8EN 1 Enable address 8 input HGEN 0 Host GPIO pins are disabled HDI08CONT bset HEN x M_HPCR Enable the HDI08 to operate as host interface set HEN 1 jclr HRD...

Page 384: ...o to starting Prog addr MD MC MB MA 1001 is used for Burn in code BURN_RESER jclr MB omr BURN IF MD MC MB MA 1001 go to BURN The following modes are reserved some of which are used for internal testing MD MC MB MA 0011 is reserved MD MC MB MA 1010 is reserved MD MC MB MA 1011 is reserved RESERVED bra Code for burn in M_PCRC EQU FFFFBF Port C GPIO Control Register M_PDRC EQU FFFFBD Port C GPIO Data...

Page 385: ...SCKT as output GPIO pin bset SCKT x M_PRRC SCKT toggles means test pass r5 test fail flag 000000 lua r5 r7 r7 test pass flag FFFFFF burnin_loop do 9 burn1 test RAM each pass checks 1 pattern move p r6 x1 pattern for x memory move p r6 x0 pattern for y memory move p r6 y0 pattern for p memory write pattern to all memory locations if EQUALDATA x y ram symmetrical write x and y memory clr a start_dra...

Page 386: ...k dram clr a start_dram r0 restore pointer clear a do n0 _loopd move x r0 a1 a0 a2 0 eor x1 a add a b accumulate error in b move y r0 a1 a0 a2 0 eor x0 a add a b accumulate error in b _loopd else x y ram not symmetrical check xram clr a start_xram r0 restore pointer clear a do n0 _loopx move x r0 a1 a0 a2 0 eor x1 a add a b accumulate error in b _loopx check yram clr a start_yram r1 restore pointe...

Page 387: ...M_PDRC clear SCKT if error enddo terminate the loop normally this instr can be removed in case of shortage bra burn1 and stop execution label1 if no error bchg SCKT x M_PDRC toggle pin and keep on looping burn1 test completion debug enter debug mode if OnCE port enabled this instr can be removed in case of shortage wait enter wait otherwise OnCE port disabled BURN_END ORG PL PL PATTERNS dsm 4 alig...

Page 388: ...L FFAF80 This code fills the unused rom locations with their address dup FFB000 14 dc endm Code segment for testing of ROM Patch This code segment is located in the uppermost addresses of the Program ROM ORG PL FFB000 14 PL FFB000 14 move 80000 r0 move 0 x0 move x0 x r0 move 1 x0 move x0 x r0 move 2 x0 move x0 x r0 move 3 x0 move x0 x r0 move 4 x0 move x0 x r0 move 5 x0 move x0 x r0 move 6 x0 move...

Page 389: ...Bootstrap ROM Contents MOTOROLA DSP56367 A 15 end ...

Page 390: ...A 16 DSP56367 MOTOROLA Bootstrap ROM Contents ...

Page 391: ...opt mex intequ ident 1 0 if DEF I_VEC leave user definition as is else I_VEC equ 0 endif Non Maskable interrupts I_RESET EQU I_VEC 00 Hardware RESET I_STACK EQU I_VEC 02 Stack Error I_ILL EQU I_VEC 04 Illegal Instruction I_IINST EQU I_VEC 04 Illegal Instruction I_DBG EQU I_VEC 06 Debug Request I_TRAP EQU I_VEC 08 Trap ...

Page 392: ...C 16 IRQD DMA Interrupts I_DMA0 EQU I_VEC 18 DMA Channel 0 I_DMA1 EQU I_VEC 1A DMA Channel 1 I_DMA2 EQU I_VEC 1C DMA Channel 2 I_DMA3 EQU I_VEC 1E DMA Channel 3 I_DMA4 EQU I_VEC 20 DMA Channel 4 I_DMA5 EQU I_VEC 22 DMA Channel 5 DAX Interrupts I_DAXTUE EQU I_VEC 28 DAX Underrun Error I_DAXBLK EQU I_VEC 2A DAX Block Transferred I_DAXTD EQU I_VEC 2E DAX Audio Data Empty ESAI Interrupts ...

Page 393: ...us I_ESAITLS EQU I_VEC 3E ESAI Transmit Last Slot SHI Interrupts I_SHITD EQU I_VEC 40 SHI Transmit Data I_SHITUE EQU I_VEC 42 SHI Transmit Underrun Error I_SHIRNE EQU I_VEC 44 SHI Receive FIFO Not Empty I_SHIRFF EQU I_VEC 48 SHI Receive FIFO Full I_SHIROE EQU I_VEC 4A SHI Receive Overrun Error I_SHIBER EQU I_VEC 4C SHI Bus Error Timer Interrupts I_TIM0C EQU I_VEC 54 TIMER 0 compare I_TIM0OF EQU I_...

Page 394: ...SAI1RDE EQU I_VEC 74 ESAI_1 Receive Data With Exception Status I_ESAI1RLS EQU I_VEC 76 ESAI_1 Receive Last Slot I_ESAI1TD EQU I_VEC 78 ESAI_1 Transmit Data I_ESAI1TED EQU I_VEC 7A ESAI_1 Transmit Even Data I_ESAI1TDE EQU I_VEC 7C ESAI_1 Transmit Data With Exception Status I_ESAI1TLS EQU I_VEC 7E ESAI_1 Transmit Last Slot INTERRUPT ENDING ADDRESS I_INTEND EQU I_VEC FF last address of interrupt vect...

Page 395: ... C Control Register M_PRRC EQU FFFFBE Port C Direction Register M_PDRC EQU FFFFBD Port C GPIO Data Register M_PCRD EQU FFFFD7 Port D Control register M_PRRD EQU FFFFD6 Port D Direction Data Register M_PDRD EQU FFFFD5 Port D GPIO Data Register M_PCRE EQU FFFFD7 Port E Control register M_PRRE EQU FFFFD6 Port E Direction Data Register M_PDRE EQU FFFFD5 Port E GPIO Data Register M_OGDB EQU FFFFFC OnCE...

Page 396: ... IRQB Mode Trigger Mode M_ICL EQU 1C0 IRQC Mode Mask M_ICL0 EQU 6 IRQC Mode Interrupt Priority Level low M_ICL1 EQU 7 IRQC Mode Interrupt Priority Level high M_ICL2 EQU 8 IRQC Mode Trigger Mode M_IDL EQU E00 IRQD Mode Mask M_IDL0 EQU 9 IRQD Mode Interrupt Priority Level low M_IDL1 EQU 10 IRQD Mode Interrupt Priority Level high M_IDL2 EQU 11 IRQD Mode Trigger Mode M_D0L EQU 3000 DMA0 Interrupt prio...

Page 397: ...A5 Interrupt Priority Level high Interrupt Priority Register Peripheral IPRP M_ESL EQU 3 ESAI Interrupt Priority Level Mask M_ESL0 EQU 0 ESAI Interrupt Priority Level low M_ESL1 EQU 1 ESAI Interrupt Priority Level high M_SHL EQU C SHI Interrupt Priority Level Mask M_SHL0 EQU 2 SHI Interrupt Priority Level low M_SHL1 EQU 3 SHI Interrupt Priority Level high M_HDL EQU 30 HDI08 Interrupt Priority Leve...

Page 398: ... EQU FFFFF2 DMA Offset Register 1 M_DOR2 EQU FFFFF1 DMA Offset Register 2 M_DOR3 EQU FFFFF0 DMA Offset Register 3 Register Addresses Of DMA0 M_DSR0 EQU FFFFEF DMA0 Source Address Register M_DDR0 EQU FFFFEE DMA0 Destination Address Register M_DCO0 EQU FFFFED DMA0 Counter M_DCR0 EQU FFFFEC DMA0 Control Register Register Addresses Of DMA1 M_DSR1 EQU FFFFEB DMA1 Source Address Register M_DDR1 EQU FFFF...

Page 399: ...ress Register M_DDR4 EQU FFFFDE DMA4 Destination Address Register M_DCO4 EQU FFFFDD DMA4 Counter M_DCR4 EQU FFFFDC DMA4 Control Register Register Addresses Of DMA5 M_DSR5 EQU FFFFDB DMA5 Source Address Register M_DDR5 EQU FFFFDA DMA5 Destination Address Register M_DCO5 EQU FFFFD9 DMA5 Counter M_DCR5 EQU FFFFD8 DMA5 Control Register DMA Control Register M_DSS EQU 3 DMA Source Space Mask DSS0 Dss1 M...

Page 400: ...it 1 M_DRS2 EQU 13 DMA Request Source bit 2 M_DRS3 EQU 14 DMA Request Source bit 3 M_DRS4 EQU 15 DMA Request Source bit 4 M_DCON EQU 16 DMA Continuous Mode M_DPR EQU 60000 DMA Channel Priority M_DPR0 EQU 17 DMA Channel Priority Level low M_DPR1 EQU 18 DMA Channel Priority Level high M_DTM EQU 380000 DMA Transfer Mode Mask DTM2 DTM0 M_DTM0 EQU 19 DMA Transfer Mode 0 M_DTM1 EQU 20 DMA Transfer Mode ...

Page 401: ...CH0 EQU 9 DMA Active Channel 0 M_DCH1 EQU 10 DMA Active Channel 1 M_DCH2 EQU 11 DMA Active Channel 2 EQUATES for Phase Locked Loop PLL Register Addresses Of PLL M_PCTL EQU FFFFFD PLL Control Register PLL Control Register M_MF EQU FFF Multiplication Factor Bits Mask MF0 MF11 M_MF0 EQU 0 Multiplication Factor bit 0 M_MF1 EQU 1 Multiplication Factor bit 1 M_MF2 EQU 2 Multiplication Factor bit 2 M_MF3...

Page 402: ...Factor bit 1 M_DF2 EQU 14 Division Factor bit 2 M_XTLR EQU 15 XTAL Range select bit M_XTLD EQU 16 XTAL Disable Bit M_PSTP EQU 17 STOP Processing State Bit M_PEN EQU 18 PLL Enable Bit M_COD EQU 19 PLL Clock Output Disable Bit M_PD EQU F00000 PreDivider Factor Bits Mask PD0 PD3 M_PD0 EQU 20 PreDivider Factor bit 0 M_PD1 EQU 21 PreDivider Factor bit 1 M_PD2 EQU 22 PreDivider Factor bit 2 M_PD3 EQU 23...

Page 403: ... Wait Control Bit 3 M_BA0W4 EQU 4 Area 0 Wait Control Bit 4 M_BA1W EQU 3E0 Area 1 Wait Control Mask BA1W0 BA14 M_BA1W0 EQU 5 Area 1 Wait Control Bit 0 M_BA1W1 EQU 6 Area 1 Wait Control Bit 1 M_BA1W2 EQU 7 Area 1 Wait Control Bit 2 M_BA1W3 EQU 8 Area 1 Wait Control Bit 3 M_BA1W4 EQU 9 Area 1 Wait Control Bit 4 M_BA2W EQU 1C00 Area 2 Wait Control Mask BA2W0 BA2W2 M_BA2W0 EQU 10 Area 2 Wait Control B...

Page 404: ...Wait States Bits Mask BCW0 BCW1 M_BCW0 EQU 0 In Page Wait States Bit 0 M_BCW1 EQU 1 In Page Wait States Bit 1 M_BRW EQU C Out Of Page Wait States Bits Mask BRW0 BRW1 M_BRW0 EQU 2 Out of Page Wait States bit 0 M_BRW1 EQU 3 Out of Page Wait States bit 1 M_BPS EQU 300 DRAM Page Size Bits Mask BPS0 BPS1 M_BPS0 EQU 4 DRAM Page Size Bits 0 M_BPS1 EQU 5 DRAM Page Size Bits 1 M_BPLE EQU 11 Page Logic Enab...

Page 405: ...ddress Attribute Pin Polarity M_BPEN EQU 3 Program Space Enable M_BXEN EQU 4 X Data Space Enable M_BYEN EQU 5 Y Data Space Enable M_BAM EQU 6 Address Muxing M_BPAC EQU 7 Packing Enable M_BNC EQU F00 Number of Address Bits to Compare Mask BNC0 BNC3 M_BNC0 EQU 8 Number of Address Bits to Compare 0 M_BNC1 EQU 9 Number of Address Bits to Compare 1 M_BNC2 EQU 10 Number of Address Bits to Compare 2 M_BN...

Page 406: ...10 M_BAC11 EQU 23 Address to Compare Bits 11 control and status bits in SR M_C EQU 0 Carry M_V EQU 1 Overflow M_Z EQU 2 Zero M_N EQU 3 Negative M_U EQU 4 Unnormalized M_E EQU 5 Extension M_L EQU 6 Limit M_S EQU 7 Scaling Bit M_I0 EQU 8 Interupt Mask Bit 0 M_I1 EQU 9 Interupt Mask Bit 1 M_S0 EQU 10 Scaling Mode Bit 0 M_S1 EQU 11 Scaling Mode Bit 1 M_SC EQU 13 Sixteen_Bit Compatibility M_DM EQU 14 D...

Page 407: ... Bus Disable bit in OMR M_SD EQU 6 Stop Delay M_MS EQU 7 Memory Switch Mode M_CDP EQU 300 mask for CORE DMA priority bits in OMR M_CDP0 EQU 8 bit 0 of priority bits in OMR Core DMA M_CDP1 EQU 9 bit 1 of priority bits in OMR Core DMA M_BE EQU 10 Burst Enable M_TAS EQU 11 TA Synchronize Select M_BRT EQU 12 Bus Release Timing M_ABE EQU 13 Async Bus Arbitration Enable M_APD EQU 14 Addess Priority Disa...

Page 408: ...ADRA M_XNADR EQU FFFFD1 DAX Non Audio Data Register XNADR M_XCTR EQU FFFFD0 DAX Control Register XCTR status bits in XSTR M_XADE EQU 0 DAX Audio Data Register Empty XADE M_XAUR EQU 1 DAX Trasmit Underrun Error Flag XAUR M_XBLK EQU 2 DAX Block Transferred XBLK non audio bits in XNADR M_XVA EQU 10 DAX Channel A Validity XVA M_XUA EQU 11 DAX Channel A User Data XUA M_XCA EQU 12 DAX Channel A Channel ...

Page 409: ...SB EQUATES for SHI Register Addresses M_HRX EQU FFFF94 SHI Receive FIFO HRX M_HTX EQU FFFF93 SHI Transmit Register HTX M_HSAR EQU FFFF92 SHI I2C Slave Address Register HSAR M_HCSR EQU FFFF91 SHI Control Status Register HCSR M_HCKR EQU FFFF90 SHI Clock Control Register HCKR HSAR bits M_HA6 EQU 23 SHI I2C Slave Address HA6 M_HA5 EQU 22 SHI I2C Slave Address HA5 M_HA4 EQU 21 SHI I2C Slave Address HA4...

Page 410: ...HI Bus Error Interrupt Enable HBIE M_HIDLE EQU 9 SHI Idle HIDLE M_HRQE1 EQU 8 SHI Host Request Enable HRQE1 M_HRQE0 EQU 7 SHI Host Request Enable HRQE0 M_HMST EQU 6 SHI Master Mode HMST M_HFIFO EQU 5 SHI FIFO Enable Control HFIFO M_HCKFR EQU 4 SHI Clock Freeze HCKFR M_HM1 EQU 3 SHI Serial Host Interface Mode HM1 M_HM0 EQU 2 SHI Serial Host Interface Mode HM0 M_HI2C EQU 1 SHI I2c SPI Selection HI2C...

Page 411: ...QU FFFFAF MUX PIN CONTROL REGISTER EMUXR M_RSMB_1 EQU FFFF9C ESAI_1 Receive Slot Mask Register B RSMB_1 M_RSMA_1 EQU FFFF9B ESAI_1 Receive Slot Mask Register A RSMA_1 M_TSMB_1 EQU FFFF9A ESAI_1 Transmit Slot Mask Register B TSMB_1 M_TSMA_1 EQU FFFF99 ESAI_1 Transmit Slot Mask Register A TSMA_1 M_RCCR_1 EQU FFFF98 ESAI_1 Receive Clock Control Register RCCR_1 M_RCR_1 EQU FFFF97 ESAI_1 Receive Contro...

Page 412: ...egister 2 TX2_1 M_TX1_1 EQU FFFF81 ESAI_1 Transmit Data Register 1 TX1_1 M_TX0_1 EQU FFFF80 ESAI_1 Transmit Data Register 0 TX0_1 EQUATES for ESAI Register Addresses M_RSMB EQU FFFFBC ESAI Receive Slot Mask Register B RSMB M_RSMA EQU FFFFBB ESAI Receive Slot Mask Register A RSMA M_TSMB EQU FFFFBA ESAI Transmit Slot Mask Register B TSMB M_TSMA EQU FFFFB9 ESAI Transmit Slot Mask Register A TSMA M_RC...

Page 413: ...t Data Register 5 TX5 M_TX4 EQU FFFFA4 ESAI Transmit Data Register 4 TX4 M_TX3 EQU FFFFA3 ESAI Transmit Data Register 3 TX3 M_TX2 EQU FFFFA2 ESAI Transmit Data Register 2 TX2 M_TX1 EQU FFFFA1 ESAI Transmit Data Register 1 TX1 M_TX0 EQU FFFFA0 ESAI Transmit Data Register 0 TX0 RSMB Register bits M_RS31 EQU 15 ESAI M_RS30 EQU 14 ESAI M_RS29 EQU 13 ESAI M_RS28 EQU 12 ESAI M_RS27 EQU 11 ESAI M_RS26 EQ...

Page 414: ...EQU 12 ESAI M_RS11 EQU 11 ESAI M_RS10 EQU 10 ESAI M_RS9 EQU 9 ESAI M_RS8 EQU 8 ESAI M_RS7 EQU 7 ESAI M_RS6 EQU 6 ESAI M_RS5 EQU 5 ESAI M_RS4 EQU 4 ESAI M_RS3 EQU 3 ESAI M_RS2 EQU 2 ESAI M_RS1 EQU 1 ESAI M_RS0 EQU 0 ESAI TSMB Register bits M_TS31 EQU 15 ESAI M_TS30 EQU 14 ESAI M_TS29 EQU 13 ESAI M_TS28 EQU 12 ESAI M_TS27 EQU 11 ESAI M_TS26 EQU 10 ESAI ...

Page 415: ... M_TS18 EQU 2 ESAI M_TS17 EQU 1 ESAI M_TS16 EQU 0 ESAI TSMA Register bits M_TS15 EQU 15 ESAI M_TS14 EQU 14 ESAI M_TS13 EQU 13 ESAI M_TS12 EQU 12 ESAI M_TS11 EQU 11 ESAI M_TS10 EQU 10 ESAI M_TS9 EQU 9 ESAI M_TS8 EQU 8 ESAI M_TS7 EQU 7 ESAI M_TS6 EQU 6 ESAI M_TS5 EQU 5 ESAI M_TS4 EQU 4 ESAI M_TS3 EQU 3 ESAI M_TS2 EQU 2 ESAI M_TS1 EQU 1 ESAI M_TS0 EQU 0 ESAI ...

Page 416: ...SAI M_RFP EQU 3C000 ESAI MASK M_RFP3 EQU 17 ESAI M_RFP2 EQU 16 ESAI M_RFP1 EQU 15 ESAI M_RFP0 EQU 14 ESAI M_RDC EQU 3E00 ESAI MASK M_RDC4 EQU 13 ESAI M_RDC3 EQU 12 ESAI M_RDC2 EQU 11 ESAI M_RDC1 EQU 10 ESAI M_RDC0 EQU 9 ESAI M_RPSR EQU 8 ESAI M_RPM EQU FF M_RPM7 EQU 7 ESAI M_RPM6 EQU 6 ESAI M_RPM5 EQU 5 ESAI M_RPM4 EQU 4 ESAI M_RPM3 EQU 3 ESAI M_RPM2 EQU 2 ESAI ...

Page 417: ...PR EQU 19 ESAI M_RFSR EQU 16 ESAI M_RFSL EQU 15 ESAI M_RSWS EQU 7C00 ESAI MASK M_RSWS4 EQU 14 ESAI M_RSWS3 EQU 13 ESAI M_RSWS2 EQU 12 ESAI M_RSWS1 EQU 11 ESAI M_RSWS0 EQU 10 ESAI M_RMOD EQU 300 M_RMOD1 EQU 9 ESAI M_RMOD0 EQU 8 ESAI M_RWA EQU 7 ESAI M_RSHFD EQU 6 ESAI M_RE EQU F M_RE3 EQU 3 ESAI M_RE2 EQU 2 ESAI M_RE1 EQU 1 ESAI M_RE0 EQU 0 ESAI TCCR Register bits ...

Page 418: ...P EQU 3C000 M_TFP3 EQU 17 ESAI M_TFP2 EQU 16 ESAI M_TFP1 EQU 15 ESAI M_TFP0 EQU 14 ESAI M_TDC EQU 3E00 M_TDC4 EQU 13 ESAI M_TDC3 EQU 12 ESAI M_TDC2 EQU 11 ESAI M_TDC1 EQU 10 ESAI M_TDC0 EQU 9 ESAI M_TPSR EQU 8 ESAI M_TPM EQU FF M_TPM7 EQU 7 ESAI M_TPM6 EQU 6 ESAI M_TPM5 EQU 5 ESAI M_TPM4 EQU 4 ESAI M_TPM3 EQU 3 ESAI M_TPM2 EQU 2 ESAI M_TPM1 EQU 1 ESAI ...

Page 419: ...I M_PADC EQU 17 ESAI M_TFSR EQU 16 ESAI M_TFSL EQU 15 ESAI M_TSWS EQU 7C00 M_TSWS4 EQU 14 ESAI M_TSWS3 EQU 13 ESAI M_TSWS2 EQU 12 ESAI M_TSWS1 EQU 11 ESAI M_TSWS0 EQU 10 ESAI M_TMOD EQU 300 M_TMOD1 EQU 9 ESAI M_TMOD0 EQU 8 ESAI M_TWA EQU 7 ESAI M_TSHFD EQU 6 ESAI M_TEM EQU 3F M_TE5 EQU 5 ESAI M_TE4 EQU 4 ESAI M_TE3 EQU 3 ESAI M_TE2 EQU 2 ESAI M_TE1 EQU 1 ESAI ...

Page 420: ...I M_OF2 EQU 2 ESAI M_OF1 EQU 1 ESAI M_OF0 EQU 0 ESAI status bits of SAISR M_TODE EQU 17 ESAI M_TEDE EQU 16 ESAI M_TDE EQU 15 ESAI M_TUE EQU 14 ESAI M_TFS EQU 13 ESAI M_RODF EQU 10 ESAI M_REDF EQU 9 ESAI M_RDF EQU 8 ESAI M_ROE EQU 7 ESAI M_RFS EQU 6 ESAI M_IF2 EQU 2 ESAI M_IF1 EQU 1 ESAI M_IF0 EQU 0 ESAI EQUATES for HDI08 ...

Page 421: ...ister HCR HCR bits M_HRIE EQU 0 HOST Receive interrupts Enable M_HOTIE EQU 1 HOST Transmit Interrupt Enable M_HCIE EQU 2 HOST Command Interrupt Enable M_HF2 EQU 3 HOST Flag 2 M_HF3 EQU 4 HOST Flag 3 M_HODM0 EQU 5 HOST DMA Mode Control Bit 0 M_HODM1 EQU 6 HOST DMA Mode Control Bit 1 M_HODM2 EQU 7 HOST DMA Mode Control Bit 2 HSR bits M_HRDF EQU 0 HOST Receive Data Full M_HOTDE EQU 1 HOST Receive Dat...

Page 422: ... EQU 6 HOST Enable M_HROD EQU 8 HOST Request Open Dranin mode M_HDSP EQU 9 HOST Data Strobe Polarity M_HASP EQU a HOST Address Strobe Polarity M_HMUX EQU b HOST Multiplexed bus select M_HDDS EQU c HOST Double Single Strobe select M_HCSP EQU d HOST Chip Select Polarity M_HRP EQU e HOST Request Polarity M_HAP EQU f HOST Acknowledge Polarity HBAR BITS M_BA EQU FF M_BA10 EQU 7 M_BA9 EQU 6 M_BA8 EQU 5 ...

Page 423: ...PR1 EQU FFFF89 TIMER1 Compare Register M_TCR1 EQU FFFF88 TIMER1 Count Register Register Addresses Of TIMER2 M_TCSR2 EQU FFFF87 TIMER2 Control Status Register M_TLR2 EQU FFFF86 TIMER2 Load Reg M_TCPR2 EQU FFFF85 TIMER2 Compare Register M_TCR2 EQU FFFF84 TIMER2 Count Register M_TPLR EQU FFFF83 TIMER Prescaler Load Register M_TPCR EQU FFFF82 TIMER Prescalar Count Register Timer Control Status Registe...

Page 424: ... Output M_PCE EQU 15 Prescaled Clock Enable M_TOF EQU 20 Timer Overflow Flag M_TCF EQU 21 Timer Compare Flag Timer Prescaler Register Bit Flags M_PS EQU 600000 Prescaler Source Mask M_PS0 EQU 21 M_PS1 EQU 22 Timer Control Bits M_TC0 EQU 4 Timer Control 0 M_TC1 EQU 5 Timer Control 1 M_TC2 EQU 6 Timer Control 2 M_TC3 EQU 7 Timer Control 3 end of ioequ asm ...

Page 425: ...nout bit SDO1 inout bit SDOI23 inout bit PINIT in bit SDOI32 inout bit SVCC linkage bit_vector 0 to 1 SGND linkage bit_vector 0 to 1 SDOI41 inout bit SDOI50 inout bit FST inout bit FSR inout bit SCKT inout bit SCKR inout bit HSCKT inout bit HSCKR inout bit QVCC linkage bit_vector 0 to 3 QGND linkage bit_vector 0 to 3 QVCCH linkage bit_vector 0 to 2 HP inout bit_vector 0 to 15 ADO inout bit ACI ino...

Page 426: ..._vector 0 to 23 DVCC linkage bit_vector 0 to 3 DGND linkage bit_vector 0 to 3 MODD in bit MODC in bit MODB in bit MODA in bit MOSI inout bit SDA inout bit SDO41_1 inout bit SDO50_1 inout bit FST_1 inout bit FSR_1 inout bit SCKR_1 inout bit SCKT_1 inout bit use STD_1149_1_1994 all attribute COMPONENT_CONFORMANCE of DSP56367 entity is STD_1149_1_1993 attribute PIN_MAP of DSP56367 entity is PHYSICAL_...

Page 427: ...50 AA 70 69 51 CAS_ 52 SCKT_1 53 EXTAL 55 CVCC 57 65 CGND 58 66 FSR_1 59 SCKR_1 60 PINIT 61 TA_ 62 BR_ 63 BB_ 64 WR_ 67 RD_ 68 BG_ 71 A 72 73 76 77 78 79 82 83 84 85 88 89 92 93 94 97 98 99 AVCC 74 80 86 AGND 75 81 87 96 D 100 101 102 105 106 107 108 109 110 113 114 115 116 117 118 121 122 123 124 125 128 131 132 133 DVCC 103 111 119 129 DGND 104 112 120 130 MODD 134 MODC 135 MODB 136 MODA 137 SDO...

Page 428: ...nufacturer s use 0001001111 sequence number 00000001110 manufacturer identity 1 1149 1 requirement attribute REGISTER_ACCESS of DSP56367 entity is ONCE 8 ENABLE_ONCE DEBUG_REQUEST attribute BOUNDARY_LENGTH of DSP56367 entity is 152 attribute BOUNDARY_REGISTER of DSP56367 entity is num cell port func safe ccell dis rslt 0 BC_1 control 1 1 BC_6 SDO41_1 bidir X 0 1 Z 2 BC_1 MODA input X 3 BC_1 MODB i...

Page 429: ... X 35 1 Z 39 BC_1 A 11 output3 X 35 1 Z num cell port func safe ccell dis rslt 40 BC_1 A 10 output3 X 35 1 Z 41 BC_1 A 9 output3 X 35 1 Z 42 BC_1 A 8 output3 X 45 1 Z 43 BC_1 A 7 output3 X 45 1 Z 44 BC_1 A 6 output3 X 45 1 Z 45 BC_1 control 1 46 BC_1 A 5 output3 X 45 1 Z 47 BC_1 A 4 output3 X 45 1 Z 48 BC_1 A 3 output3 X 45 1 Z 49 BC_1 A 2 output3 X 45 1 Z 50 BC_1 A 1 output3 X 45 1 Z 51 BC_1 A 0 ...

Page 430: ...89 BC_1 control 1 90 BC_6 HP 4 bidir X 89 1 Z 91 BC_1 control 1 92 BC_6 HP 5 bidir X 91 1 Z 93 BC_1 control 1 94 BC_6 HP 6 bidir X 93 1 Z 95 BC_1 control 1 96 BC_6 HP 7 bidir X 95 1 Z 97 BC_1 control 1 98 BC_6 HP 8 bidir X 97 1 Z 99 BC_1 control 1 num cell port func safe ccell dis rslt 100 BC_6 HP 9 bidir X 99 1 Z 101 BC_1 control 1 102 BC_6 HP 10 bidir X 101 1 Z 103 BC_1 control 1 104 BC_6 HP 13 ...

Page 431: ...31 BC_1 control 1 132 BC_6 SDOI50 bidir X 131 1 Z 133 BC_1 control 1 134 BC_6 SDOI41 bidir X 133 1 Z 135 BC_1 control 1 136 BC_6 SDOI32 bidir X 135 1 Z 137 BC_1 control 1 138 BC_6 SDOI23 bidir X 137 1 Z 139 BC_1 control 1 num cell port func safe ccell dis rslt 140 BC_6 SDO1 bidir X 139 1 Z 141 BC_1 control 1 142 BC_6 SDO0 bidir X 141 1 Z 143 BC_1 control 1 144 BC_6 HREQ_ bidir X 143 1 Z 145 BC_1 S...

Page 432: ...C 8 DSP56367 MOTOROLA JTAG BSDL ...

Page 433: ...ts for the major programmable registers on the DSP D 1 1 Peripheral Addresses Table D 1 lists the memory addresses of all on chip peripherals D 1 2 Interrupt Addresses Table D 2 lists the interrupt starting addresses and sources D 1 3 Interrupt Priorities Table D 3 lists the priorities of specific interrupts within interrupt priority levels D 1 4 Host Interface Quick Reference Table D 4 is a quick...

Page 434: ...RESS REGISTER DSR0 X FFFFEE DMA DESTINATION ADDRESS REGISTER DDR0 X FFFFED DMA COUNTER DCO0 X FFFFEC DMA CONTROL REGISTER DCR0 DMA1 X FFFFEB DMA SOURCE ADDRESS REGISTER DSR1 X FFFFEA DMA DESTINATION ADDRESS REGISTER DDR1 X FFFFE9 DMA COUNTER DCO1 X FFFFE8 DMA CONTROL REGISTER DCR1 DMA2 X FFFFE7 DMA SOURCE ADDRESS REGISTER DSR2 X FFFFE6 DMA DESTINATION ADDRESS REGISTER DDR2 X FFFFE5 DMA COUNTER DCO...

Page 435: ... X FFFFC9 HOST PORT GPIO DATA REGISTER HDR X FFFFC8 HOST PORT GPIO DIRECTION REGISTER HDDR HDI08 X FFFFC7 HOST TRANSMIT REGISTER HOTX X FFFFC6 HOST RECEIVE REGISTER HORX X FFFFC5 HOST BASE ADDRESS REGISTER HBAR X FFFFC4 HOST PORT CONTROL REGISTER HPCR X FFFFC3 HOST STATUS REGISTER HSR X FFFFC2 HOST CONTROL REGISTER HCR X FFFFC1 RESERVED X FFFFC0 RESERVED PORT C X FFFFBF PORT C CONTROL REGISTER PCR...

Page 436: ...RECEIVE DATA REGISTER 2 RX2 X FFFFA9 ESAI RECEIVE DATA REGISTER 1 RX1 X FFFFA8 ESAI RECEIVE DATA REGISTER 0 RX0 X FFFFA7 RESERVED X FFFFA6 ESAI TIME SLOT REGISTER TSR X FFFFA5 ESAI TRANSMIT DATA REGISTER 5 TX5 X FFFFA4 ESAI TRANSMIT DATA REGISTER 4 TX4 X FFFFA3 ESAI TRANSMIT DATA REGISTER 3 TX3 X FFFFA2 ESAI TRANSMIT DATA REGISTER 2 TX2 X FFFFA1 ESAI TRANSMIT DATA REGISTER 1 TX1 X FFFFA0 ESAI TRAN...

Page 437: ...2 X FFFF84 TIMER 2 COUNT REGISTER TCR2 X FFFF83 TIMER PRESCALER LOAD REGISTER TPLR X FFFF82 TIMER PRESCALER COUNT REGISTER TPCR X FFFF81 RESERVED X FFFF80 RESERVED ESAI MUX PIN CONTROL Y FFFFAF ESAI MUX PIN CONTROL REGISTER EMUXR Y FFFFAE RESERVED Y FFFFAD RESERVED Y FFFFAC RESERVED Y FFFFAB RESERVED Y FFFFAA RESERVED Y FFFFA9 RESERVED Y FFFFA8 RESERVED Y FFFFA7 RESERVED Y FFFFA6 RESERVED Y FFFFA5...

Page 438: ...ISTER SAISR_1 Y FFFF92 RESERVED Y FFFF91 RESERVED Y FFFF90 RESERVED Y FFFF8F RESERVED Y FFFF8E RESERVED Y FFFF8D RESERVED Y FFFF8C RESERVED Y FFFF8B ESAI_1 RECEIVE DATA REGISTER 3 RX3_1 Y FFFF8A ESAI_1 RECEIVE DATA REGISTER 2 RX2_1 Y FFFF89 ESAI_1 RECEIVE DATA REGISTER 1 RX1_1 Y FFFF88 ESAI_1 RECEIVE DATA REGISTER 0 RX0_1 Y FFFF87 RESERVED Y FFFF86 ESAI_1 TIME SLOT REGISTER TSR_1 Y FFFF85 ESAI_1 T...

Page 439: ...upt Source VBA 10 0 2 IRQA VBA 12 0 2 IRQB VBA 14 0 2 IRQC VBA 16 0 2 IRQD VBA 18 0 2 DMA Channel 0 VBA 1A 0 2 DMA Channel 1 VBA 1C 0 2 DMA Channel 2 VBA 1E 0 2 DMA Channel 3 VBA 20 0 2 DMA Channel 4 VBA 22 0 2 DMA Channel 5 VBA 24 0 2 Reserved VBA 26 0 2 Reserved VBA 28 0 2 DAX Underrun Error VBA 2A 0 2 DAX Block Transferred VBA 2C 0 2 Reserved VBA 2E 0 2 DAX Audio Data Empty VBA 30 0 2 ESAI Rece...

Page 440: ...IMER2 Compare VBA 5E 0 2 TIMER2 Overflow VBA 60 0 2 Host Receive Data Full VBA 62 0 2 Host Transmit Data Empty VBA 64 0 2 Host Command Default VBA 66 0 2 Reserved VBA 68 0 2 Reserved VBA 6A 0 2 Reserved VBA 6C 0 2 Reserved VBA 6E 0 2 Reserved VBA 70 0 2 ESAI_1 Receive Data VBA 72 0 2 ESAI_1 Receive Even Data VBA 74 0 2 ESAI_1 Receive Data With Exception Status VBA 76 0 2 ESAI_1 Receive Last Slot V...

Page 441: ...ogrammer s Reference MOTOROLA DSP56367 D 9 VBA 80 0 2 Reserved VBA FE 0 2 Reserved Table D 2 DSP56367 Interrupt Vectors Continued Interrupt Starting Address Interrupt Priority Level Range Interrupt Source ...

Page 442: ...l Interrupt IRQC External Interrupt IRQD External Interrupt DMA Channel 0 Interrupt DMA Channel 1 Interrupt DMA Channel 2 Interrupt DMA Channel 3 Interrupt DMA Channel 4 Interrupt DMA Channel 5 Interrupt ESAI Receive Data with Exception Status ESAI Receive Even Data ESAI Receive Data ESAI Receive Last Slot ESAI Transmit Data with Exception Status ESAI Transmit Last Slot ESAI Transmit Even Data ESA...

Page 443: ...upt TIMER1 Overflow Interrupt TIMER1 Compare Interrupt TIMER2 Overflow Interrupt TIMER2 Compare Interrupt ESAI_1 Receive Data with Exception Status ESAI_1 Receive Even Data ESAI_1 Receive Data ESAI_1 Receive Last Slot ESAI_1 Transmit Data with Exception Status ESAI_1 Transmit Last Slot ESAI_1 Transmit Even Data Lowest ESAI_1 Transmit Data Table D 3 Interrupt Sources Priorities Within an IPL Contin...

Page 444: ...ansmit Interrupt Enable 0 1 HTRQ interrupt disabled HTRQ interrupt enabled 0 2 HCIE Host Command Interrupt Enable 0 1 HCP interrupt disabled HCP interrupt enabled 0 3 HF2 Host Flag 2 0 4 HF3 Host Flag 3 0 7 5 HDM 2 0 Host DMA Mode 000 100 001 010 011 101 110 111 DMA operation disabled DMA operation enabled 24 bit host to DSP DMA enabled 16 bit host to DSP DMA enabled 8 bit host to DSP DMA enabled ...

Page 445: ...HDS HRD HWR active high this bit is ignored if HEN 0 0 10 HASP Host Address Strobe Polarity 0 1 HAS active low HAS active high this bit is ignored if HEN 0 0 11 HMUX Host Multiplxed Bus 0 1 Seprate address and data lines Multiplexed address data this bit is ignored if HEN 0 0 12 HDDS Host Dual Data Strobe 0 1 Single Data Strobe HDS Double Data Strobe HWR HRD this bit is ignored if HEN 0 0 13 HCSP ...

Page 446: ... if HDM2 HDM0 100 00 7 INIT Initialize 1 Reset data paths according to TREQ and RREQ cleared by HDI08 hardware 0 ISR 0 RXDF Receive Data Register Full 0 1 host receive register is empty host receive register is full 0 0 0 1 TXDE Transmit Data Register Empty 1 0 host transmit register empty host transmit register full 1 1 1 2 TRDY Transmitter Ready 1 0 transmit FIF O 6 deep is empty transmit FIFO i...

Page 447: ...st Interface HDI08 Serial Host Interface SHI Two Enhanced Serial Audio Interfaces ESAI and ESAI_1 Digital Audio Interface DAX Timer Event Controller TEC GPIO Ports B E Each sheet provides room to write in the value of each bit and the hexadecimal value for each register Programmers can photocopy these sheets and reuse them for each application development project For details on the instruction set...

Page 448: ...0 01 10 11 None IPL 0 IPL 0 1 IPL 0 1 2 Carry Overfow Zero Negative Unnormalized U Acc 47 xnor Acc 46 Extension Limit FFT Scaling S Acc 46 xor Acc 45 Reserved Sixteen Bit Compatibilitity Double Precision Multiply Mode Loop Flag DO Forever Flag Sixteenth Bit Arithmetic Reserved Instruction Cache Enable Arithmetic Saturation Rounding Mode Core Priority CP 1 0 Core Priority 00 01 10 11 0 lowest 1 2 3...

Page 449: ...accesses Core DMA accesses Core MSW1 MSW0 0 Chip Operating Mode Register COM System Stack Control Status Register SCS Extended Chip Operating Mode Register COM Operating Mode Register OMR Read Write Reset 00030X Central Processor Reserved Program as 0 Burst Mode Enable TA Synchronize Select Bus Release Timing Stack Extension Space Select Extended Stack Underflow Flag Extended Stack Overflow Flag E...

Page 450: ...r IPR C 23 22 21 20 19 18 16 17 D1L1 IAL2 Trigger 0 Level 1 Neg Edge IRQA Mode IAL1 IAL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 IBL2 Trigger 0 Level 1 Neg Edge IRQB Mode IBL1 IBL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 ICL0 ICL1 ICL2 IDL0 D2L0 D2L1 D3L0 D3L1 D4L0 D4L1 D5L0 D5L1 ICL2 Trigger 0 Level 1 Neg Edge IRQC Mode ICL1 ICL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 ...

Page 451: ... ESAI IPL SHL1 SHL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 SHI IPL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HDL1 HDL0 SHL1 SHL0 ESL1 ESL0 23 22 21 20 19 18 16 17 DAL0 DAL1 TAL0 TAL1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HDL1 HDL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 HDI08 IPL DAL1 DAL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 DAX IPL TAL1 TAL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Ye...

Page 452: ...uty Cycle Clock 1 Pin Held In High State Crystal Range Bit XTLR 0 External Xtal Freq 200KHz 1 External Xtal Freq 200KHz Predivision Factor Bits PD0 PD3 PD3 PD0 Predivision Factor PDF 0 1 2 F 1 2 3 16 Multiplication Factor Bits MF0 MF11 MF11 MF0 Multiplication Factor MF 000 001 002 FFE FFF 1 2 3 4095 4096 Division Factor Bits DF0 DF2 DF2 DF0 Division Factor DF 0 1 2 7 2 0 2 1 2 2 2 7 PSTP and PEN R...

Page 453: ...16 23 22 21 20 Receive High Byte Receive Middle Byte Receive Low Byte Host Receive Register HORX X FFFEC6 Read Only Reset empty Host Receive Data usually read by program 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 23 22 21 20 Transmit High Byte Transmit Middle Byte Transmit Low Byte Host Transmit Data usually loaded by program Host Transmit Register HOTX X FFFEC7 Write Only Reset empty DSP S...

Page 454: ...t Data Empty 1 Write 0 Wait 0 8 6 5 4 3 2 1 0 15 0 Host Receive Interrupt Enable 1 Enable 0 Disable HCIE HRIE HF3 HTIE HF2 Host Flag 2 Host Command Interrupt Enable Host Transmit Interrupt Enable 1 Enable 0 Disable 0 Host Control Register HCR X FFFFC2 Read Write Reset 0 if HRDF 1 if HTDE 1 1 Enable 0 Disable if HCP 1 Host Flag 3 HDI08 7 HDM0 HDM1 HDM2 Host DMA Control Bits See Table 6 5 in Section...

Page 455: ...ble 0 HA9 GPIO 1 HA9 HA9 Host Address Line 8 Enable 0 HA8 GPIO 1 HA8 HA8 Host GPIO Port Enable 0 GPIO Pins Disconnected Host Acknowledge Polarity 0 HACK Active Low 1 HACK Active High Host Chip Select Polarity 0 HCS Active Low Host Dual Data Strobe 0 Single Strobe 1 Dual Strobe Host Multiplexed Bus 0 Nonmultiplexed 1 Multiplexed Host Address Strobe Polarity 0 Strobe Active Low 1 Strobe Active High ...

Page 456: ...pts Enabled DMA On 0 Host DSP 1 DSP Host 0 No Action 1 Initialize DMA HDRQ 0 HDRQ HOREQ HTRQ HACK HRRQ 0 HOREQ HACK 1 HTRQ HRRQ 7 6 5 4 3 2 1 0 Reserved Program as 0 0 RXDF HF3 TXDE HF2 HREQ TRDY Interrupt Status Register ISR 2 R W Reset 0 Transmit Data Register Empty 0 Wait 1 Write Transmitter Ready 0 Data in HI 1 Data Not in HI Host Flags Read Only Receive Data Register Full 0 Wait 1 Read Host R...

Page 457: ...IV4 IV1 IV3 IV7 IV5 Interrupt Vector Register IVR IV2 Contains the interrupt vector or number IV6 7 6 5 4 3 2 1 0 HV0 HV4 HV1 HV3 HC HV5 Command Vector Register CVR HV2 Contains the host command interrupt address HV6 Host Vector Contains Host Command Interrupt Address 2 Host Command Handshakes Executing Host Command Interrupts Processor Side Reset 0F 3 R W Reset 32 1 R W ...

Page 458: ... 4 0 0 0 0 0 0 0 0 0 7 5 Receive Middle Byte Receive High Byte Not Used Receive Low Byte 7 0 7 0 0 7 Host Transmit Data HLEND 0 6 5 4 0 0 0 0 0 0 0 0 0 7 7 Transmit Middle Byte Transmit High Byte Not Used Transmit Low Byte Processor Side 7 0 7 0 0 7 Host Receive Data HLEND 0 6 5 4 0 0 0 0 0 0 0 0 0 7 7 Receive Middle Byte Receive High Byte Not Used Receive Low Byte Transmit Byte Registers 7 0 7 0 ...

Page 459: ...0 0 0 0 0 0 0 0 0 0 0 HA4 0 0 0 0 0 0 0 0 0 0 HDM5 HCKR Divider Modulus HSAR I2 C Slave Address Slave address Bits HA6 HA3 HA1 and external pins HA2 HA0 Slave address after reset 1011 HA2 0 HA0 HFM1 HFM0 SHI Noise Reduction Filter Mode 0 0 Bypassed Filter disabled 0 1 Reserved 1 0 Narrow spike tolerance 1 1 Wide spike tolerance HFM0 HFM1 SHI Clock Control Register HCKR SHI Slave Address Register H...

Page 460: ...3 2 1 0 SHI Host Transmit X FFFF93 Write Only Reset xxxxxx Data Register HTX 19 18 17 16 23 22 21 20 Host Transmit Data Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SHI Host Receive X FFFF94 Read Only Reset xxxxxx Data Register HRX 19 18 17 16 23 22 21 20 Host Receive Data Register SHI Host Receive Data Register HRX FIFO 10 words deep SHI Host Transmit Data Register HTX ...

Page 461: ... 0 Asserted if IOSR ready to transmit new word 1 1 I 2 C Asserted if IOSR ready to transmit or receive SPI Asserted if OISR ready to transmit and receive HIDLE Description 0 Bus busy 1 Stop event HBIE Description 0 Bus Error Interrupt disabled 1 Bus Error Interrupt enabled HTIE Description 0 Transmit Interrupt disabled 1 Transmit Interrupt activated Host Transmit Underrun Error Read Only Status Bi...

Page 462: ... External clock source used Internal clock source TFSD Description 0 1 FST is input FST is output THCKD Description 0 1 HCKT is input HCKT is output THCKP Description 0 1 Transmitter High Frequency Clock Polarity set to clockout Transmitter High Frequency Clock Polarity set to clockout Range 0 F 1 16 See 8 3 1 4 TDC 4 0 Description Divider control Range 00 FF 1 32 See 8 3 1 3 TPM 7 0 Description S...

Page 463: ...st Slot Interrupt enabled TEIE Description 0 1 Transmit Exception Interrupt disabled 0 TSWS 0 4 Description Defines slot and data word length TFSL Description 0 1 ESAI TCR ESAI Transmit Control Register X FFFFB5 Reset 000000 See 8 3 2 10 and table 8 5 TWA Description 0 1 Data left aligned Data right aligned TSHFD Description 0 1 Data shifted out MSB first Data shifted out LSB first TE 0 5 Transmit...

Page 464: ...eiver high frequency clock RCKD Description 0 1 External clock source used Internal clock source RFSD Description 0 1 FSR is input FSR is output RHCKD Description 0 1 HCKR is input HCKR is output RHCKP Description 0 1 Clockout on rising edge of receive clock latch in on falling edge of receive clock Clockout on falling edge of receive clock latch in on rising edge of receive clock Range 0 F 1 16 S...

Page 465: ...nterrupt enabled REDIE Description 0 Receive Even Slot Data Interrupt disabled 1 Receive Even Slot Data Interrupt enabled REIE Description 0 Receive Exception Interrupt disabled 1 Receive Exception Interrupt enabled RPR Description 0 Receiver Normal Operation 1 Receiver Personal Reset RFSL Description 0 Word length frame sync 1 1 bit clock period frame sync RWA Description 0 Data left aligned 1 Da...

Page 466: ...n SYN ESAI SAICR ESAI Common Control Register X FFFFB4 Reset 000000 ALC Description 0 1 Data left aligned to bit 23 Data left aligned to bit 15 Description 0 1 Asynchronous mode Synchronous mode Reserved ALC Description Holds data to send to OFn pin Description Reserved See 8 3 5 1 to 3 OF 2 0 Description Controls FSR pin See 8 3 5 6 and table 8 9 TEBE Application Date Programmer ...

Page 467: ...n 0 1 Receive data register empty Receive data register full REDF RODF TFS TUE TDE TEDE TODE REDF Description 0 1 Receive even data register empty Receive even data register full TODE Description 0 1 Transmit odd data register not empty Transmit odd data register empty TFS Description 0 1 Transmit Frame sync did not occur during word transmission Transmit frame sync occurred during word transmissi...

Page 468: ...egister Y FFFFAF Reset 000000 Reserved Application Date Programmer ESAI_1 EMUX3 EMUXR ESAI ESAI_1 Pin Selection EMUXR bit ESAI pin ESAI_1 pin EMUX0 0 SDO0 PC11 disconnected EMUX0 1 disconnected SDO0_1 PE11 EMUX1 0 SDO1 PC10 disconnected EMUX1 1 disconnected SDO1_1 PE10 EMUX2 0 SDO2 SDI3 PC9 disconnected EMUX2 1 disconnected SDO2_1 SDI3_1 PE9 EMUX3 0 SDO3 SDI2 PC8 disconnected EMUX3 1 disconnected ...

Page 469: ...polarity positive Frame sync polarity negative TFP 3 0 Description Divider control TCKD Description 0 1 External clock source used Internal clock source TFSD Description 0 1 FST_1 is input FST_1 is output THCKD Description 0 1 Reserved Must be set for proper operation THCKP Description 0 1 Keep cleared for proper operation Reserved Range 0 F 1 16 TDC 4 0 Description Divider control Range 00 FF 1 3...

Page 470: ... Transmit Last Slot Interrupt enabled TEIE Description 0 1 Transmit Exception Interrupt disabled 0 TSWS 0 4 Description Defines slot and data word length TFSL Description 0 1 TCR_1 ESAI_1 Transmit Control Register Y FFFF95 Reset 000000 TWA Description 0 1 Data left aligned Data right aligned TSHFD Description 0 1 Data shifted out MSB first Data shifted out LSB first TE 0 5 Transmitter disabled Tra...

Page 471: ...ity positive Frame sync polarity negative RFP 3 0 Description Sets divide rate RCKD Description 0 1 External clock source used Internal clock source RFSD Description 0 1 FSR_1 is input FSR_1 is output RHCKD Description 0 1 Reserved Must be set for proper operation RHCKP Description 0 1 Keep cleared for proper operation Reserved Range 0 F 1 16 RDC 4 0 Description Controls frame rate dividers RPM 7 ...

Page 472: ...upt enabled REIE Description 0 Receive Exception Interrupt disabled 1 Receive Exception Interrupt enabled RPR Description 0 Receiver Normal Operation 1 Receiver Personal Reset RFSL Description 0 Word length frame sync 1 1 bit clock period frame sync RWA Description 0 Data left aligned 1 Data right aligned RE 0 3 Description 0 Receiver disabled 1 Receiver enabled RSHFD Description 0 Data shifted in...

Page 473: ...YN TEBE Description SYN SAICR_1 ESAI_1 Common Control Register Y FFFF94 Reset 000000 ALC Description 0 1 Data left aligned to bit 23 Data left aligned to bit 15 Description 0 1 Asynchronous mode Synchronous mode Reserved ALC Description Holds data to send to OFn pin Description Reserved OF 2 0 Description Controls FSR_1 pin TEBE Application Date Programmer ESAI_1 ...

Page 474: ... register empty Receive data register full REDF RODF TFS TUE TDE TEDE TODE REDF Description 0 1 Receive even data register empty Receive even data register full TODE Description 0 1 Transmit odd data register not empty Transmit odd data register empty TFS Description 0 1 Transmit Frame sync did not occur during word transmission Transmit frame sync occurred during word transmission TUE Description...

Page 475: ...2 11 10 9 8 7 6 5 4 3 2 1 0 DAX Non Audio Data X FFFFD1 Reset 00XX00 Register XNADR 0 0 0 0 0 0 16 17 18 19 20 21 22 23 0 0 0 0 0 0 0 XCB XUB XVB XCA XUA XVA 0 0 0 0 0 Channel A Validity XVA Channel A User Data XUA Channel B Validity XVB Channel B User Data XUB Application Date Programmer Sheet 1 of 2 ...

Page 476: ... 18 19 20 21 22 23 0 0 0 0 0 0 0 XBLK XADE 0 0 0 0 0 0 XCS1 XCS0 DAX Clock Source 0 0 DSP Core Clock f 1024 x fs 0 1 ACI Pin f 256 x fs 1 0 ACI Pin f 384 x fs 1 1 ACI Pin f 512 x fs DAX Status X FFFFD4 Reset 000000 Register XSTR XADE DAX Audio Data Empty 0 Register s full 1 Register s empty XAUR DAX Underrun error 0 No error 1 Underrun error 0 0 0 0 0 0 0 0 XAUR XBIE DAX Block Trans Int Enable 0 D...

Page 477: ... 22 21 20 PS0 PS1 0 Prescaler Preload Value PL 0 20 Reserved Program as 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 23 22 21 20 0 Current Value of Prescaler Counter PC 0 20 Timer Prescaler Load Register TPLR FFFF83 Read Write Reset 000000 Timer Prescaler Count Register TPCR FFFF82 Read Only Reset 000000 Reserved Program as 0 PS 1 0 Prescaler Clock Source 00 Internal CLK 2 01 TIO0 10 Reserv...

Page 478: ... Timer Control Bits 4 7 TC0 TC3 TC 3 0 TIO Clock Mode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 GPIO Output Output Input Input Input Input Output Output Output Internal Internal Internal External Internal Internal Internal Internal Internal Internal Timer Timer Pulse Timer Toggle Event Counter Input Width Input Period Capture Pulse Width Modulation Reserved Wa...

Page 479: ...8E Write Only Reset XXXXXX TLR1 FFFF8A Write Only TLR2 FFFF86 Write Only Timer Compare Register TCPR0 FFFF8D Read Write Reset XXXXXX TCPR1 FFFF89 Read Write TCPR2 FFFF85 Read Write Timer Count Register TCR0 FFFF8C Read Only TCR1 FFFF88 Read Only TCR2 FFFF84 Read Only Reset 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 23 22 21 20 Value Compared to Counter Value 15 14 13 12 11 10 9 8 7 6...

Page 480: ... Direction Register X FFFFC8 Reset 0 HDDR Read Write Host Data DRx 0 PBx is Input DRx 1 PBx is Output 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D5 D4 D3 D2 D1 D0 D6 D15 D14 D13 D12 D8 D11 D9 D10 Register X FFFFC9 Reset Undefined HDR Read Write Host Data Dx holds value of corresponding HDI08 GPIO pin DR7 D7 Function depends on HDDR Port B HDI08 See the HDI08 HPCR Register Figure D 8 for additional Port...

Page 481: ... PD9 PD8 PD7 PD6 PD4 PD3 Port C GPIO Data Register X FFFFBD Reset undefined PDRC Read Write 0 If port pin n is GPIO input then PDn reflects the value on port pin n if port pin n is GPIO output then value written to PDn is reflected on port pin n 3 2 1 0 10 PC3 PC2 PC1 PC0 11 0 1 2 3 PDC10 PDC3 PDC2 PDC1PDC0 PD10 10 PD5 5 PD2 PD1 PD0 2 1 0 PC10 PCn 0 PDCn 0 Port pin PCn disconnected PCn 1 PDCn 0 Po...

Page 482: ...4 3 2 1 0 PD1 PD0 Port D GPIO Data Register X FFFFD5 Reset 0 PDRD Read Write 0 0 If port pin n is GPIO input then PDn reflects the value on port pin n if port pin n is GPIO output then value written to PDn is reflected on port pin n 23 6 5 4 3 2 1 0 PDC1 PDC0 PCn 0 PDCn 0 Port pin PDn disconnected PCn 1 PDCn 0 Port pin PDn configured as input PCn 0 PDCn 1 Port pin PDn configured as output PCn 1 PD...

Page 483: ...FFF9D Reset undefined PDRE Read Write 0 If port pin n is GPIO input then PDn reflects the value on port pin n if port pin n is GPIO output then value written to PDn is reflected on port pin n 3 2 1 0 10 PC3 PC1 PC0 11 0 1 2 3 PDC3 PDC1PDC0 10 5 PD1 PD0 2 1 0 PCn 0 PDCn 0 Port pin PEn disconnected PCn 1 PDCn 0 Port pin PEn configured as input PCn 0 PDCn 1 Port pin PEn configured as output PCn 1 PDC...

Page 484: ...D 52 DSP56367 MOTOROLA Programmer s Reference ...

Page 485: ...nolist I_VEC EQU 000000 Interrupt vectors for program debug only START EQU 8000 MAIN external program starting address INT_PROG EQU 100 INTERNAL program memory starting address INT_XDAT EQU 0 INTERNAL X data memory starting address INT_YDAT EQU 0 INTERNAL Y data memory starting address INCLUDE ioequ asm INCLUDE intequ asm list org P START movep 0123FF x M_BCR BCR Area 3 1 w s SRAM Default 1 w s SR...

Page 486: ...r0 move YDAT_START r1 do YDAT_END YDAT_START YLOAD_LOOP move p r1 x0 move x0 y r0 YLOAD_LOOP jmp INT_PROG PROG_START move 0 r0 move 0 r4 move 3f m0 move 3f m4 clr a clr b move 0 x0 move 0 x1 move 0 y0 move 0 y1 bset 4 omr ebd sbr dor 60 _end mac x0 y0 a x r0 x1 y r4 y1 mac x1 y1 a x r0 x0 y r4 y0 add a b mac x0 y0 a x r0 x1 mac x1 y1 a y r4 y0 move b1 x ff _end bra sbr nop nop nop nop PROG_END nop...

Page 487: ... C2A544 dc A3662D dc A4E762 dc 84F0F3 dc E6F1B0 dc B3829 dc 8BF7AE dc 63A94F dc EF78DC dc 242DE5 dc A3E0BA dc EBAB6B dc 8726C8 dc CA361 dc 2F6E86 dc A57347 dc 4BE774 dc 8F349D dc A1ED12 dc 4BFCE3 dc EA26E0 dc CD7D99 dc 4BA85E dc 27A43F dc A8B10C dc D3A55 dc 25EC6A dc 2A255B dc A5F1F8 dc 2426D1 dc AE6536 dc CBBC37 dc 6235A4 dc 37F0D dc 63BEC2 dc A5E4D3 dc 8CE810 dc 3FF09 dc 60E50E ...

Page 488: ... E27540 XDAT_END YDAT_START org y 0 dc 5B6DA dc C3F70B dc 6A39E8 dc 81E801 dc C666A6 dc 46F8E7 dc AAEC94 dc 24233D dc 802732 dc 2E3C83 dc A43E00 dc C2B639 dc 85A47E dc ABFDDF dc F3A2C dc 2D7CF5 dc E16A8A dc ECB8FB dc 4BED18 dc 43F371 dc 83A556 dc E1E9D7 dc ACA2C4 dc 8135AD dc 2CE0E2 dc 8F2C73 dc 432730 dc A87FA9 dc 4A292E dc A63CCF dc 6BA65C dc E06D65 dc 1AA3A dc A1B6EB dc 48AC48 ...

Page 489: ...62F6C7 dc 6064F4 dc 87E41D dc CB2692 dc 2C3863 dc C6BC60 dc 43A519 dc 6139DE dc ADF7BF dc 4B3E8C dc 6079D5 dc E0F5EA dc 8230DB dc A3B778 dc 2BFE51 dc E0A6B6 dc 68FFB7 dc 28F324 dc 8F2E8D dc 667842 dc 83E053 dc A1FD90 dc 6B2689 dc 85B68E dc 622EAF dc 6162BC dc E4A245 YDAT_END ...

Page 490: ...E 6 DSP56367 MOTOROLA Power Consumption Benchmark ...

Page 491: ...me model_name 1 sck ip5b_io 2 ss_ ip5b_io 3 hreq_ ip5b_io 4 sdo0 ip5b_io 5 sdo1 ip5b_io 6 sdoi23 ip5b_io 7 sdoi32 ip5b_io 8 svcc power 9 sgnd gnd 10 sdoi41 ip5b_io 11 sdoi50 ip5b_io 12 fst ip5b_io 13 fsr ip5b_io 14 sckt ip5b_io 15 sckr ip5b_io 16 hsckt ip5b_io 17 hsckr ip5b_io 18 qvccl power 19 gnd gnd 20 qvcch power 21 hp12 ip5b_io 22 hp11 ip5b_io 23 hp15 ip5b_io 24 hp14 ip5b_io 25 svcc power 26 ...

Page 492: ...5 ipbw_io 49 qvcch power 50 fst_1 ipbw_io 51 aa2 icbc_o 52 cas_ icbc_o 53 sck_1 ipbw_io 54 qgnd gnd 55 cxtldis_ iexlh_i 56 qvccl power 57 cvcc power 58 cgnd gnd 59 fsr_1 ipbw_io 60 sckr1 ipbw_io 61 nmi_ ipbw_i 62 ta_ icbc_o 63 br_ icbc_o 64 bb_ icbc_o 65 cvcc power 66 cgnd gnd 67 wr_ icbc_o 68 rd_ icbc_o 69 aa1 icbc_o 70 aa0 icbc_o 71 bg_ icbc_o 72 eab0 icba_o 73 eab1 icba_o 74 avcc power 75 agnd ...

Page 493: ...dvcc power 104 dgnd gnd 105 edb3 icba_io 106 edb4 icba_io 107 edb5 icba_io 108 edb6 icba_io 109 edb7 icba_io 110 edb8 icba_io 111 dvcc power 112 dgnd gnd 113 edb9 icba_io 114 edb10 icba_io 115 edb11 icba_io 116 edb12 icba_io 117 edb13 icba_io 118 edb14 icba_io 119 dvcc power 120 dgnd gnd 121 edb15 icba_io 122 edb16 icba_io 123 edb17 icba_io 124 edb18 icba_io 125 edb19 icba_io 126 qvccl power 127 q...

Page 494: ...2 3 65e 02 2 50e 00 3 16e 02 2 23e 02 3 14e 02 2 30e 00 2 65e 02 1 88e 02 2 63e 02 2 10e 00 2 14e 02 1 52e 02 2 12e 02 1 90e 00 1 63e 02 1 17e 02 1 61e 02 1 70e 00 1 13e 02 9 25e 01 1 10e 02 1 50e 00 7 83e 01 6 88e 01 7 58e 01 1 30e 00 4 43e 01 4 52e 01 4 17e 01 1 10e 00 1 02e 01 2 15e 01 7 67e 00 9 00e 01 9 69e 03 1 18e 00 7 81e 03 7 00e 01 2 83e 04 5 70e 03 8 42e 04 5 00e 01 1 35e 06 4 53e 05 1 ...

Page 495: ... 02 2 553e 02 5 660e 02 1 500e 00 4 779e 02 2 709e 02 6 023e 02 1 700e 00 4 935e 02 2 803e 02 6 271e 02 1 900e 00 5 013e 02 2 851e 02 6 419e 02 2 100e 00 5 046e 02 2 876e 02 6 494e 02 2 300e 00 5 063e 02 2 892e 02 6 525e 02 2 500e 00 5 075e 02 2 904e 02 6 540e 02 2 700e 00 5 085e 02 2 912e 02 6 549e 02 2 900e 00 5 090e 02 2 876e 02 6 555e 02 3 100e 00 4 771e 02 2 994e 02 6 561e 02 3 300e 00 4 525e...

Page 496: ...02 9 000e 01 2 46e 02 1 43e 02 3 21e 02 1 100e 00 2 84e 02 1 62e 02 3 73e 02 1 300e 00 3 14e 02 1 77e 02 4 18e 02 1 500e 00 3 37e 02 1 88e 02 4 55e 02 1 700e 00 3 55e 02 1 95e 02 4 85e 02 1 900e 00 3 68e 02 2 00e 02 5 09e 02 2 100e 00 3 78e 02 2 04e 02 5 27e 02 2 300e 00 3 85e 02 2 07e 02 5 41e 02 2 500e 00 3 91e 02 2 10e 02 5 51e 02 2 700e 00 3 96e 02 2 12e 02 5 60e 02 2 900e 00 4 01e 02 2 15e 02...

Page 497: ...8e 00 7 81e 03 7 00e 01 2 83e 04 5 70e 03 8 42e 04 5 00e 01 1 35e 06 4 53e 05 1 00e 05 3 00e 01 1 31e 09 3 74e 07 8 58e 09 1 00e 01 2 92e 11 3 00e 09 3 64e 11 0 000e 00 2 44e 11 5 14e 10 2 79e 11 Ramp R_load 50 00 voltage I typ I min I max dV dt_r 1 030 0 465 0 605 0 676 1 320 0 366 dV dt_f 1 290 0 671 0 829 0 122 1 520 0 431 Model ip5b_o Model_type 3 state Polarity Non Inverting C_comp 5 00pF 5 0...

Page 498: ...5e 02 2 912e 02 6 549e 02 2 900e 00 5 090e 02 2 876e 02 6 555e 02 3 100e 00 4 771e 02 2 994e 02 6 561e 02 3 300e 00 4 525e 02 3 321e 02 6 182e 02 3 500e 00 4 657e 02 3 570e 02 6 049e 02 3 700e 00 4 904e 02 3 801e 02 6 178e 02 3 900e 00 5 221e 02 4 029e 02 6 450e 02 4 100e 00 5 524e 02 4 253e 02 6 659e 02 4 300e 00 5 634e 02 4 463e 02 6 867e 02 4 500e 00 5 751e 02 4 645e 02 6 970e 02 4 700e 00 5 63...

Page 499: ...2 2 04e 02 5 27e 02 2 300e 00 3 85e 02 2 07e 02 5 41e 02 2 500e 00 3 91e 02 2 10e 02 5 51e 02 2 700e 00 3 96e 02 2 12e 02 5 60e 02 2 900e 00 4 01e 02 2 15e 02 5 67e 02 3 100e 00 4 04e 02 2 17e 02 5 74e 02 3 300e 00 4 08e 02 2 18e 02 5 79e 02 3 500e 00 4 11e 02 2 20e 02 5 84e 02 3 700e 00 4 14e 02 2 78e 02 5 89e 02 3 900e 00 4 17e 02 1 20e 00 5 94e 02 4 100e 00 4 32e 02 2 15e 01 5 98e 02 4 300e 00 ...

Page 500: ..._r 1 030 0 465 0 605 0 676 1 320 0 366 dV dt_f 1 290 0 671 0 829 0 122 1 520 0 431 Model icba_io Model_type I O Polarity Non Inverting Vinl 0 8000v Vinh 2 000v C_comp 5 00pF 5 00pF 5 00pF Voltage Range 3 3v 3v 3 6v Pulldown voltage I typ I min I max 3 30e 00 5 20e 02 3 65e 02 5 18e 02 3 10e 00 4 69e 02 3 30e 02 4 67e 02 2 90e 00 4 18e 02 2 94e 02 4 16e 02 2 70e 00 3 67e 02 2 59e 02 3 65e 02 2 50e ...

Page 501: ... 01 4 100e 00 1 490e 01 1 451e 01 2 015e 01 4 300e 00 1 501e 00 2 658e 01 2 030e 01 4 500e 00 1 813e 01 3 866e 01 2 385e 01 4 700e 00 3 540e 01 5 076e 01 9 563e 00 4 900e 00 5 269e 01 6 461e 01 2 682e 01 5 100e 00 7 541e 01 8 261e 01 4 409e 01 5 300e 00 1 012e 02 1 006e 02 6 258e 01 5 500e 00 1 270e 02 1 186e 02 8 836e 01 5 700e 00 1 527e 02 1 366e 02 1 141e 02 5 900e 00 1 785e 02 1 546e 02 1 399e...

Page 502: ... 13e 02 2 19e 01 3 700e 00 1 53e 01 8 84e 02 2 21e 01 3 900e 00 1 54e 01 1 26e 00 2 22e 01 4 100e 00 1 57e 01 2 16e 01 2 24e 01 4 300e 00 5 25e 01 4 53e 01 2 27e 01 4 500e 00 2 74e 01 6 89e 01 2 38e 01 4 700e 00 6 14e 01 9 26e 01 7 90e 00 4 900e 00 9 55e 01 1 17e 02 4 20e 01 5 100e 00 1 38e 02 1 52e 02 7 60e 01 5 300e 00 1 89e 02 1 88e 02 1 11e 02 5 500e 00 2 40e 02 2 23e 02 1 61e 02 5 700e 00 2 9...

Page 503: ... 1 139e 02 1 90e 00 8 814e 01 6 454e 01 8 814e 01 1 70e 00 6 236e 01 5 068e 01 6 237e 01 1 50e 00 4 389e 01 3 859e 01 4 389e 01 1 30e 00 2 662e 01 2 651e 01 2 662e 01 1 10e 00 9 358e 00 1 444e 01 9 359e 00 9 00e 01 3 399e 02 2 517e 00 3 554e 02 7 00e 01 3 426e 04 1 577e 02 9 211e 04 5 00e 01 2 840e 06 7 857e 05 1 655e 05 3 00e 01 3 401e 09 6 836e 07 1 946e 08 1 00e 01 6 162e 11 7 379e 09 7 622e 11...

Page 504: ...2 2 331e 02 1 700e 00 1 366e 01 6 746e 02 1 755e 01 1 900e 00 1 404e 01 6 916e 02 1 847e 01 2 100e 00 1 423e 01 7 006e 02 1 907e 01 2 300e 00 1 433e 01 7 059e 02 1 940e 01 2 500e 00 1 440e 01 7 098e 02 1 958e 01 2 700e 00 1 445e 01 7 128e 02 1 970e 01 2 900e 00 1 450e 01 7 154e 02 1 979e 01 3 100e 00 1 454e 01 7 176e 02 1 986e 01 3 300e 00 1 458e 01 7 196e 02 1 993e 01 3 500e 00 1 461e 01 7 223e 0...

Page 505: ... 1 100e 00 9 26e 03 5 30e 03 1 23e 02 1 300e 00 1 03e 02 6 55e 02 1 38e 02 1 500e 00 1 25e 01 6 93e 02 1 70e 01 1 700e 00 1 31e 01 7 19e 02 1 82e 01 1 900e 00 1 36e 01 7 38e 02 1 91e 01 2 100e 00 1 40e 01 7 53e 02 1 97e 01 2 300e 00 1 42e 01 7 65e 02 2 03e 01 2 500e 00 1 44e 01 7 76e 02 2 07e 01 2 700e 00 1 46e 01 7 85e 02 2 10e 01 2 900e 00 1 48e 01 7 93e 02 2 13e 01 3 100e 00 1 49e 01 8 00e 02 2...

Page 506: ... 1 95e 09 1 91e 11 POWER_clamp voltage I typ I min I max 3 30e 00 2 686e 02 1 905e 02 2 686e 02 3 10e 00 2 428e 02 1 725e 02 2 428e 02 2 90e 00 2 170e 02 1 545e 02 2 170e 02 2 70e 00 1 912e 02 1 365e 02 1 912e 02 2 50e 00 1 655e 02 1 185e 02 1 655e 02 2 30e 00 1 397e 02 1 005e 02 1 397e 02 2 10e 00 1 139e 02 8 253e 01 1 139e 02 1 90e 00 8 814e 01 6 454e 01 8 814e 01 1 70e 00 6 236e 01 5 068e 01 6 ...

Page 507: ...00e 01 1 945e 03 9 285e 04 2 307e 03 3 000e 01 5 507e 03 2 640e 03 6 599e 03 5 000e 01 8 649e 03 4 168e 03 1 048e 02 7 000e 01 1 136e 02 5 504e 03 1 393e 02 9 000e 01 1 364e 02 6 636e 03 1 693e 02 1 100e 00 1 547e 02 7 551e 03 1 950e 02 1 300e 00 1 688e 02 8 240e 03 2 162e 02 1 500e 00 9 632e 02 4 783e 02 2 331e 02 1 700e 00 1 012e 01 4 994e 02 1 302e 01 1 900e 00 1 039e 01 5 118e 02 1 369e 01 2 1...

Page 508: ...2e 00 1 433e 01 9 303e 00 9 00e 01 3 838e 02 2 477e 00 4 183e 02 7 00e 01 8 115e 03 1 789e 02 1 045e 02 5 00e 01 5 634e 03 3 503e 03 7 064e 03 3 00e 01 3 370e 03 2 053e 03 4 233e 03 1 00e 01 1 118e 03 6 789e 04 1 410e 03 1 000e 01 1 09e 03 6 56e 04 1 38e 03 3 000e 01 3 12e 03 1 86e 03 3 99e 03 5 000e 01 4 96e 03 2 93e 03 6 39e 03 7 000e 01 6 60e 03 3 87e 03 8 59e 03 9 000e 01 8 04e 03 4 66e 03 1 0...

Page 509: ... 10e 02 1 50e 00 7 83e 01 6 88e 01 7 58e 01 1 30e 00 4 42e 01 4 51e 01 4 17e 01 1 10e 00 1 02e 01 2 15e 01 7 66e 00 9 00e 01 1 03e 02 1 17e 00 9 27e 03 7 00e 01 3 74e 04 5 73e 03 1 14e 03 5 00e 01 1 72e 06 5 06e 05 1 28e 05 3 00e 01 1 67e 09 4 65e 07 1 10e 08 1 00e 01 2 03e 11 4 80e 09 2 71e 11 0 000e 00 1 69e 11 1 61e 09 1 89e 11 POWER_clamp voltage I typ I min I max 3 30e 00 2 677e 02 1 896e 02 ...

Page 510: ...2 3 64e 02 2 50e 00 3 16e 02 2 23e 02 3 13e 02 2 30e 00 2 65e 02 1 88e 02 2 62e 02 2 10e 00 2 14e 02 1 52e 02 2 11e 02 1 90e 00 1 63e 02 1 17e 02 1 60e 02 1 70e 00 1 13e 02 9 24e 01 1 10e 02 1 50e 00 7 82e 01 6 87e 01 7 57e 01 1 30e 00 4 42e 01 4 51e 01 4 16e 01 1 10e 00 1 02e 01 2 15e 01 7 64e 00 9 00e 01 7 17e 03 1 16e 00 4 87e 03 7 00e 01 1 14e 04 4 39e 03 3 03e 04 5 00e 01 4 86e 07 2 55e 05 2 ...

Page 511: ...7e 02 3 10e 00 4 69e 02 3 29e 02 4 66e 02 2 90e 00 4 18e 02 2 94e 02 4 15e 02 2 70e 00 3 67e 02 2 58e 02 3 64e 02 2 50e 00 3 16e 02 2 23e 02 3 13e 02 2 30e 00 2 65e 02 1 88e 02 2 62e 02 2 10e 00 2 14e 02 1 52e 02 2 11e 02 1 90e 00 1 63e 02 1 17e 02 1 60e 02 1 70e 00 1 13e 02 9 24e 01 1 10e 02 1 50e 00 7 82e 01 6 87e 01 7 57e 01 1 30e 00 4 42e 01 4 51e 01 4 17e 01 1 10e 00 1 02e 01 2 15e 01 7 66e 0...

Page 512: ... 1 707e 02 1 643e 02 6 300e 00 2 283e 02 1 885e 02 1 899e 02 6 500e 00 2 539e 02 2 064e 02 2 155e 02 6 600e 00 2 667e 02 2 153e 02 2 283e 02 Pullup voltage I typ I min I max 3 30e 00 2 667e 02 1 885e 02 2 667e 02 3 10e 00 2 411e 02 1 707e 02 2 411e 02 2 90e 00 2 155e 02 1 528e 02 2 155e 02 2 70e 00 1 898e 02 1 350e 02 1 898e 02 2 50e 00 1 642e 02 1 172e 02 1 642e 02 2 30e 00 1 386e 02 9 935e 01 1 ...

Page 513: ...00e 00 2 39e 02 2 23e 02 1 60e 02 5 700e 00 2 90e 02 2 58e 02 2 11e 02 5 900e 00 3 41e 02 2 94e 02 2 62e 02 6 100e 00 3 92e 02 3 29e 02 3 13e 02 6 300e 00 4 43e 02 3 65e 02 3 64e 02 6 500e 00 4 94e 02 4 00e 02 4 15e 02 6 600e 00 5 20e 02 4 18e 02 4 41e 02 GND_clamp voltage I typ I min I max 3 30e 00 5 20e 02 3 65e 02 5 17e 02 3 10e 00 4 69e 02 3 29e 02 4 66e 02 2 90e 00 4 18e 02 2 94e 02 4 15e 02 ...

Page 514: ...06 3 00e 01 8 479e 10 2 484e 07 3 721e 09 1 00e 01 4 420e 11 3 001e 09 4 943e 11 0 000e 00 4 215e 11 1 346e 09 4 543e 11 Ramp R_load 50 00 voltage I typ I min I max dV dt_r 1 140 0 494 0 699 0 978 1 400 0 354 dV dt_f 1 150 0 505 0 642 0 956 1 350 0 350 Model iexlh_i Model_type Input Polarity Non Inverting Vinl 0 8000v Vinh 2 000v C_comp 5 00pF 5 00pF 5 00pF Voltage Range 3 3v 3v 3 6v GND_clamp vol...

Page 515: ...43e 02 1 516e 02 2 143e 02 2 70e 00 1 888e 02 1 339e 02 1 888e 02 2 50e 00 1 633e 02 1 162e 02 1 633e 02 2 30e 00 1 378e 02 9 847e 01 1 378e 02 2 10e 00 1 123e 02 8 076e 01 1 123e 02 1 90e 00 8 682e 01 6 305e 01 8 682e 01 1 70e 00 6 133e 01 4 947e 01 6 133e 01 1 50e 00 4 313e 01 3 766e 01 4 313e 01 1 30e 00 2 614e 01 2 585e 01 2 614e 01 1 10e 00 9 145e 00 1 404e 01 9 145e 00 9 00e 01 1 797e 02 2 3...

Page 516: ...F 26 DSP56367 MOTOROLA IBIS Model ...

Page 517: ... Registers XADRA XADRB 12 5 DAX Audio Data Shift Register XADSR 12 6 12 6 DAX biphase encoder 12 10 DAX Block transfer XBLK flag 12 9 DAX Channel A Channel status XCA bit 12 7 DAX Channel A User data XUA bit 12 6 DAX Channel A Validity XVA bit 12 6 DAX Channel B Channel Status XCB bit 12 7 DAX Channel B User Data XUB bit 12 7 DAX Channel B Validity XVB bit 12 7 DAX Clock input Select bits 12 8 DAX...

Page 518: ...Global Data Bus 1 8 GPIO 1 12 2 21 GPIO ESSI0 Port C 7 2 7 2 GPIO ESSI1 Port D 7 2 GPIO HI08 Port B 7 1 GPIO Timer 7 2 GPIO timing 3 74 Ground 2 4 ground 2 1 2 1 H HA1 HA3 HA6 HSAR I2 C Slave Address 9 9 hardware stack 1 8 HBER HCSR Bus Error 9 18 HBIE HCSR Bus Error Interrupt Enable 9 16 HBUSY HCSR Host Busy 9 18 HCKR SHI Clock Control Register 9 9 HCSR Receive Interrupt Enable Bits 9 16 SHI Cont...

Page 519: ...C register 1 8 Loop Address register LA 1 8 Loop Counter register LC 1 8 M MAC 1 6 Manual Conventions iii iii maximum ratings 3 1 3 2 mechanical drawings 14 8 memory expansion 1 11 external expansion port 1 11 off chip 1 11 on chip 1 10 1 10 Mfax system 14 8 mode control 2 8 2 8 2 9 Mode select timing 3 9 modulo adder 1 7 multiplexed bus timings read 3 52 write 3 53 multiplier accumulator MAC 1 5 ...

Page 520: ... Select 9 11 Prescaler Rate Select 9 11 HCKR Filter Mode 9 12 HCSR Bus Error Interrupt Enable 9 16 FIFO Enable Control 9 14 Host Request Enable 9 15 Idle 9 15 Master Mode 9 14 Serial Host Interface I2 C SPI Selection 9 13 Serial Host Interface Mode 9 13 SHI Enable 9 13 Host Receive Data FIFO DSP Side 9 8 Host Transmit Data Register DSP Side 9 8 HREQ Function In SHI Slave Modes 9 15 HSAR I2 C Slave...

Page 521: ...urement capture 13 20 mode 7 pulse width modulation 13 21 mode 8 reserved 13 22 mode 9 watchdog pulse 13 22 13 23 modes 11 15 reserved 13 24 Timer module architecture 13 1 Timer Prescaler Count Register TPCR 13 6 Timer Prescaler Load Register TPLR 13 5 Timing Digital Audio Transmitter DAX 3 72 Enhanced Serial Audio Interface ESAI 3 68 General Purpose I O GPIO Timing 3 66 OnCE On Chip Emulator Timi...

Page 522: ...Index 6 MOTOROLA Index ...

Page 523: ......

Page 524: ...emiconductors H K Ltd 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po N T Hong Kong 852 26629298 Technical Resource Center 1 800 521 6274 Japan Nippon Motorola Ltd SPD Strategic Planning Office 4 32 1 Nishi Gotanda Shinagawa ku Tokyo Japan 81 3 5487 8488 Internet http www motorola dsp com DSP helpline email dsphelp dsp sps motcom DSP56367UM D Revision 1 0 02 01 ...

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